Commit | Line | Data |
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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
36dffd8f | 14 | #include "imx51.dtsi" |
9daaf31a SG |
15 | |
16 | / { | |
17 | model = "Freescale i.MX51 Babbage Board"; | |
18 | compatible = "fsl,imx51-babbage", "fsl,imx51"; | |
19 | ||
48f51963 SH |
20 | chosen { |
21 | stdout-path = &uart1; | |
22 | }; | |
23 | ||
9daaf31a SG |
24 | memory { |
25 | reg = <0x90000000 0x20000000>; | |
26 | }; | |
27 | ||
1c0daab7 AS |
28 | clocks { |
29 | ckih1 { | |
30 | clock-frequency = <22579200>; | |
31 | }; | |
32 | ||
33 | clk_26M: codec_clock { | |
34 | compatible = "fixed-clock"; | |
35 | reg=<0>; | |
36 | #clock-cells = <0>; | |
37 | clock-frequency = <26000000>; | |
38 | gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; | |
39 | }; | |
40 | }; | |
41 | ||
17b5001b | 42 | display0: display@di0 { |
be4ccfce | 43 | compatible = "fsl,imx-parallel-display"; |
be4ccfce SG |
44 | interface-pix-fmt = "rgb24"; |
45 | pinctrl-names = "default"; | |
5a2a7d57 | 46 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
493a8636 FE |
47 | display-timings { |
48 | native-mode = <&timing0>; | |
49 | timing0: dvi { | |
50 | clock-frequency = <65000000>; | |
51 | hactive = <1024>; | |
52 | vactive = <768>; | |
53 | hback-porch = <220>; | |
54 | hfront-porch = <40>; | |
55 | vback-porch = <21>; | |
56 | vfront-porch = <7>; | |
57 | hsync-len = <60>; | |
58 | vsync-len = <10>; | |
59 | }; | |
60 | }; | |
de10e04e PZ |
61 | |
62 | port { | |
63 | display0_in: endpoint { | |
64 | remote-endpoint = <&ipu_di0_disp0>; | |
65 | }; | |
66 | }; | |
be4ccfce | 67 | }; |
a15d9f89 | 68 | |
17b5001b | 69 | display1: display@di1 { |
be4ccfce | 70 | compatible = "fsl,imx-parallel-display"; |
be4ccfce SG |
71 | interface-pix-fmt = "rgb565"; |
72 | pinctrl-names = "default"; | |
5a2a7d57 | 73 | pinctrl-0 = <&pinctrl_ipu_disp2>; |
493a8636 FE |
74 | status = "disabled"; |
75 | display-timings { | |
76 | native-mode = <&timing1>; | |
77 | timing1: claawvga { | |
78 | clock-frequency = <27000000>; | |
79 | hactive = <800>; | |
80 | vactive = <480>; | |
81 | hback-porch = <40>; | |
82 | hfront-porch = <60>; | |
83 | vback-porch = <10>; | |
84 | vfront-porch = <10>; | |
85 | hsync-len = <20>; | |
86 | vsync-len = <10>; | |
87 | hsync-active = <0>; | |
88 | vsync-active = <0>; | |
89 | de-active = <1>; | |
90 | pixelclk-active = <0>; | |
91 | }; | |
92 | }; | |
de10e04e PZ |
93 | |
94 | port { | |
95 | display1_in: endpoint { | |
96 | remote-endpoint = <&ipu_di1_disp1>; | |
97 | }; | |
98 | }; | |
9daaf31a SG |
99 | }; |
100 | ||
101 | gpio-keys { | |
102 | compatible = "gpio-keys"; | |
2ccc447c AS |
103 | pinctrl-names = "default"; |
104 | pinctrl-0 = <&pinctrl_gpio_keys>; | |
9daaf31a SG |
105 | |
106 | power { | |
107 | label = "Power Button"; | |
bdb3eec7 | 108 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; |
02134e77 | 109 | linux,code = <KEY_POWER>; |
9daaf31a SG |
110 | gpio-key,wakeup; |
111 | }; | |
112 | }; | |
a15d9f89 | 113 | |
a198af23 LY |
114 | leds { |
115 | compatible = "gpio-leds"; | |
116 | pinctrl-names = "default"; | |
117 | pinctrl-0 = <&pinctrl_gpio_leds>; | |
118 | ||
119 | led-diagnostic { | |
120 | label = "diagnostic"; | |
121 | gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; | |
122 | }; | |
123 | }; | |
124 | ||
9bf206a9 FE |
125 | regulators { |
126 | compatible = "simple-bus"; | |
127 | #address-cells = <1>; | |
128 | #size-cells = <0>; | |
129 | ||
7a9f0604 | 130 | reg_hub_reset: regulator@0 { |
db8235ec AS |
131 | compatible = "regulator-fixed"; |
132 | pinctrl-names = "default"; | |
133 | pinctrl-0 = <&pinctrl_usbotgreg>; | |
7a9f0604 FE |
134 | reg = <0>; |
135 | regulator-name = "hub_reset"; | |
db8235ec AS |
136 | regulator-min-microvolt = <5000000>; |
137 | regulator-max-microvolt = <5000000>; | |
138 | gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
139 | enable-active-high; | |
140 | }; | |
9bf206a9 FE |
141 | }; |
142 | ||
1c0daab7 AS |
143 | sound { |
144 | compatible = "fsl,imx51-babbage-sgtl5000", | |
145 | "fsl,imx-audio-sgtl5000"; | |
146 | model = "imx51-babbage-sgtl5000"; | |
147 | ssi-controller = <&ssi2>; | |
148 | audio-codec = <&sgtl5000>; | |
149 | audio-routing = | |
150 | "MIC_IN", "Mic Jack", | |
151 | "Mic Jack", "Mic Bias", | |
152 | "Headphone Jack", "HP_OUT"; | |
153 | mux-int-port = <2>; | |
154 | mux-ext-port = <3>; | |
155 | }; | |
156 | ||
9bf206a9 FE |
157 | usbphy { |
158 | #address-cells = <1>; | |
159 | #size-cells = <0>; | |
160 | compatible = "simple-bus"; | |
161 | ||
162 | usbh1phy: usbh1phy@0 { | |
163 | compatible = "usb-nop-xceiv"; | |
164 | reg = <0>; | |
6b273284 | 165 | clocks = <&clks IMX5_CLK_DUMMY>; |
9bf206a9 | 166 | clock-names = "main_clk"; |
7a9f0604 | 167 | reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; |
9bf206a9 FE |
168 | }; |
169 | }; | |
9daaf31a | 170 | }; |
be4ccfce | 171 | |
1c0daab7 | 172 | &audmux { |
be4ccfce | 173 | pinctrl-names = "default"; |
1c0daab7 | 174 | pinctrl-0 = <&pinctrl_audmux>; |
be4ccfce SG |
175 | status = "okay"; |
176 | }; | |
177 | ||
178 | &ecspi1 { | |
179 | pinctrl-names = "default"; | |
5a2a7d57 | 180 | pinctrl-0 = <&pinctrl_ecspi1>; |
be4ccfce | 181 | fsl,spi-num-chipselects = <2>; |
bdb3eec7 | 182 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, |
d2176f29 | 183 | <&gpio4 25 GPIO_ACTIVE_LOW>; |
be4ccfce SG |
184 | status = "okay"; |
185 | ||
186 | pmic: mc13892@0 { | |
be4ccfce | 187 | compatible = "fsl,mc13892"; |
1ddcff4b AS |
188 | pinctrl-names = "default"; |
189 | pinctrl-0 = <&pinctrl_pmic>; | |
be4ccfce | 190 | spi-max-frequency = <6000000>; |
dc071436 | 191 | spi-cs-high; |
be4ccfce SG |
192 | reg = <0>; |
193 | interrupt-parent = <&gpio1>; | |
1cbb74fd | 194 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
f4511417 | 195 | fsl,mc13xxx-uses-rtc; |
be4ccfce SG |
196 | |
197 | regulators { | |
198 | sw1_reg: sw1 { | |
199 | regulator-min-microvolt = <600000>; | |
200 | regulator-max-microvolt = <1375000>; | |
201 | regulator-boot-on; | |
202 | regulator-always-on; | |
203 | }; | |
204 | ||
205 | sw2_reg: sw2 { | |
206 | regulator-min-microvolt = <900000>; | |
207 | regulator-max-microvolt = <1850000>; | |
208 | regulator-boot-on; | |
209 | regulator-always-on; | |
210 | }; | |
211 | ||
212 | sw3_reg: sw3 { | |
213 | regulator-min-microvolt = <1100000>; | |
214 | regulator-max-microvolt = <1850000>; | |
215 | regulator-boot-on; | |
216 | regulator-always-on; | |
217 | }; | |
218 | ||
219 | sw4_reg: sw4 { | |
220 | regulator-min-microvolt = <1100000>; | |
221 | regulator-max-microvolt = <1850000>; | |
222 | regulator-boot-on; | |
223 | regulator-always-on; | |
224 | }; | |
225 | ||
226 | vpll_reg: vpll { | |
227 | regulator-min-microvolt = <1050000>; | |
228 | regulator-max-microvolt = <1800000>; | |
229 | regulator-boot-on; | |
230 | regulator-always-on; | |
231 | }; | |
232 | ||
233 | vdig_reg: vdig { | |
234 | regulator-min-microvolt = <1650000>; | |
235 | regulator-max-microvolt = <1650000>; | |
236 | regulator-boot-on; | |
237 | }; | |
238 | ||
239 | vsd_reg: vsd { | |
240 | regulator-min-microvolt = <1800000>; | |
241 | regulator-max-microvolt = <3150000>; | |
242 | }; | |
243 | ||
244 | vusb2_reg: vusb2 { | |
245 | regulator-min-microvolt = <2400000>; | |
246 | regulator-max-microvolt = <2775000>; | |
247 | regulator-boot-on; | |
248 | regulator-always-on; | |
249 | }; | |
250 | ||
251 | vvideo_reg: vvideo { | |
252 | regulator-min-microvolt = <2775000>; | |
253 | regulator-max-microvolt = <2775000>; | |
254 | }; | |
255 | ||
256 | vaudio_reg: vaudio { | |
257 | regulator-min-microvolt = <2300000>; | |
258 | regulator-max-microvolt = <3000000>; | |
259 | }; | |
260 | ||
261 | vcam_reg: vcam { | |
262 | regulator-min-microvolt = <2500000>; | |
263 | regulator-max-microvolt = <3000000>; | |
264 | }; | |
265 | ||
266 | vgen1_reg: vgen1 { | |
267 | regulator-min-microvolt = <1200000>; | |
268 | regulator-max-microvolt = <1200000>; | |
269 | }; | |
270 | ||
271 | vgen2_reg: vgen2 { | |
272 | regulator-min-microvolt = <1200000>; | |
273 | regulator-max-microvolt = <3150000>; | |
274 | regulator-always-on; | |
275 | }; | |
276 | ||
277 | vgen3_reg: vgen3 { | |
278 | regulator-min-microvolt = <1800000>; | |
279 | regulator-max-microvolt = <2900000>; | |
280 | regulator-always-on; | |
281 | }; | |
282 | }; | |
283 | }; | |
284 | ||
285 | flash: at45db321d@1 { | |
286 | #address-cells = <1>; | |
287 | #size-cells = <1>; | |
288 | compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; | |
289 | spi-max-frequency = <25000000>; | |
290 | reg = <1>; | |
291 | ||
292 | partition@0 { | |
293 | label = "U-Boot"; | |
294 | reg = <0x0 0x40000>; | |
295 | read-only; | |
296 | }; | |
297 | ||
298 | partition@40000 { | |
299 | label = "Kernel"; | |
300 | reg = <0x40000 0x3c0000>; | |
301 | }; | |
302 | }; | |
303 | }; | |
304 | ||
1c0daab7 AS |
305 | &esdhc1 { |
306 | pinctrl-names = "default"; | |
307 | pinctrl-0 = <&pinctrl_esdhc1>; | |
dacf4922 SH |
308 | cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; |
309 | wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; | |
1c0daab7 AS |
310 | status = "okay"; |
311 | }; | |
312 | ||
313 | &esdhc2 { | |
314 | pinctrl-names = "default"; | |
315 | pinctrl-0 = <&pinctrl_esdhc2>; | |
dacf4922 | 316 | cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; |
1c0daab7 AS |
317 | wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
318 | status = "okay"; | |
319 | }; | |
320 | ||
321 | &fec { | |
322 | pinctrl-names = "default"; | |
323 | pinctrl-0 = <&pinctrl_fec>; | |
324 | phy-mode = "mii"; | |
325 | phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; | |
326 | phy-reset-duration = <1>; | |
327 | status = "okay"; | |
328 | }; | |
329 | ||
dd0c672a AS |
330 | &i2c1 { |
331 | pinctrl-names = "default"; | |
332 | pinctrl-0 = <&pinctrl_i2c1>; | |
333 | status = "okay"; | |
334 | }; | |
335 | ||
1c0daab7 AS |
336 | &i2c2 { |
337 | pinctrl-names = "default"; | |
338 | pinctrl-0 = <&pinctrl_i2c2>; | |
339 | status = "okay"; | |
340 | ||
341 | sgtl5000: codec@0a { | |
342 | compatible = "fsl,sgtl5000"; | |
343 | pinctrl-names = "default"; | |
344 | pinctrl-0 = <&pinctrl_clkcodec>; | |
345 | reg = <0x0a>; | |
346 | clocks = <&clk_26M>; | |
347 | VDDA-supply = <&vdig_reg>; | |
348 | VDDIO-supply = <&vvideo_reg>; | |
349 | }; | |
350 | }; | |
351 | ||
de10e04e PZ |
352 | &ipu_di0_disp0 { |
353 | remote-endpoint = <&display0_in>; | |
354 | }; | |
355 | ||
356 | &ipu_di1_disp1 { | |
357 | remote-endpoint = <&display1_in>; | |
358 | }; | |
359 | ||
1c0daab7 AS |
360 | &kpp { |
361 | pinctrl-names = "default"; | |
362 | pinctrl-0 = <&pinctrl_kpp>; | |
363 | linux,keymap = < | |
364 | MATRIX_KEY(0, 0, KEY_UP) | |
365 | MATRIX_KEY(0, 1, KEY_DOWN) | |
366 | MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) | |
367 | MATRIX_KEY(0, 3, KEY_HOME) | |
368 | MATRIX_KEY(1, 0, KEY_RIGHT) | |
369 | MATRIX_KEY(1, 1, KEY_LEFT) | |
370 | MATRIX_KEY(1, 2, KEY_ENTER) | |
371 | MATRIX_KEY(1, 3, KEY_VOLUMEUP) | |
372 | MATRIX_KEY(2, 0, KEY_F6) | |
373 | MATRIX_KEY(2, 1, KEY_F8) | |
374 | MATRIX_KEY(2, 2, KEY_F9) | |
375 | MATRIX_KEY(2, 3, KEY_F10) | |
376 | MATRIX_KEY(3, 0, KEY_F1) | |
377 | MATRIX_KEY(3, 1, KEY_F2) | |
378 | MATRIX_KEY(3, 2, KEY_F3) | |
379 | MATRIX_KEY(3, 3, KEY_POWER) | |
380 | >; | |
381 | status = "okay"; | |
382 | }; | |
383 | ||
be4ccfce | 384 | &ssi2 { |
be4ccfce SG |
385 | status = "okay"; |
386 | }; | |
387 | ||
1c0daab7 AS |
388 | &uart1 { |
389 | pinctrl-names = "default"; | |
390 | pinctrl-0 = <&pinctrl_uart1>; | |
391 | fsl,uart-has-rtscts; | |
392 | status = "okay"; | |
393 | }; | |
394 | ||
395 | &uart2 { | |
396 | pinctrl-names = "default"; | |
397 | pinctrl-0 = <&pinctrl_uart2>; | |
398 | status = "okay"; | |
399 | }; | |
400 | ||
401 | &uart3 { | |
402 | pinctrl-names = "default"; | |
403 | pinctrl-0 = <&pinctrl_uart3>; | |
404 | fsl,uart-has-rtscts; | |
405 | status = "okay"; | |
406 | }; | |
407 | ||
408 | &usbh1 { | |
409 | pinctrl-names = "default"; | |
410 | pinctrl-0 = <&pinctrl_usbh1>; | |
7a9f0604 | 411 | vbus-supply = <®_hub_reset>; |
1c0daab7 AS |
412 | fsl,usbphy = <&usbh1phy>; |
413 | phy_type = "ulpi"; | |
414 | status = "okay"; | |
415 | }; | |
416 | ||
417 | &usbotg { | |
418 | dr_mode = "otg"; | |
419 | disable-over-current; | |
420 | phy_type = "utmi_wide"; | |
1c0daab7 AS |
421 | status = "okay"; |
422 | }; | |
423 | ||
be4ccfce | 424 | &iomuxc { |
5a2a7d57 | 425 | imx51-babbage { |
5a2a7d57 SG |
426 | pinctrl_audmux: audmuxgrp { |
427 | fsl,pins = < | |
428 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | |
429 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | |
430 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | |
431 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | |
432 | >; | |
433 | }; | |
434 | ||
2ccc447c AS |
435 | pinctrl_clkcodec: clkcodecgrp { |
436 | fsl,pins = < | |
437 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 | |
438 | >; | |
439 | }; | |
440 | ||
5a2a7d57 SG |
441 | pinctrl_ecspi1: ecspi1grp { |
442 | fsl,pins = < | |
443 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | |
444 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | |
445 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | |
2ccc447c AS |
446 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ |
447 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ | |
5a2a7d57 SG |
448 | >; |
449 | }; | |
450 | ||
451 | pinctrl_esdhc1: esdhc1grp { | |
452 | fsl,pins = < | |
453 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | |
454 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | |
455 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | |
456 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | |
457 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | |
458 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | |
dacf4922 SH |
459 | MX51_PAD_GPIO1_0__GPIO1_0 0x100 |
460 | MX51_PAD_GPIO1_1__GPIO1_1 0x100 | |
5a2a7d57 SG |
461 | >; |
462 | }; | |
463 | ||
464 | pinctrl_esdhc2: esdhc2grp { | |
465 | fsl,pins = < | |
466 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | |
467 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | |
468 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | |
469 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | |
470 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | |
471 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | |
2ccc447c AS |
472 | MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ |
473 | MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ | |
5a2a7d57 SG |
474 | >; |
475 | }; | |
476 | ||
477 | pinctrl_fec: fecgrp { | |
478 | fsl,pins = < | |
c73dbd71 SH |
479 | MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 |
480 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 | |
481 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 | |
482 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 | |
483 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 | |
484 | MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 | |
485 | MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 | |
486 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 | |
487 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 | |
488 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 | |
489 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 | |
490 | MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 | |
491 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 | |
492 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 | |
493 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 | |
494 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 | |
495 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 | |
496 | MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 | |
497 | MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ | |
5a2a7d57 SG |
498 | >; |
499 | }; | |
500 | ||
2ccc447c AS |
501 | pinctrl_gpio_keys: gpiokeysgrp { |
502 | fsl,pins = < | |
503 | MX51_PAD_EIM_A27__GPIO2_21 0x5 | |
504 | >; | |
505 | }; | |
506 | ||
a198af23 LY |
507 | pinctrl_gpio_leds: gpioledsgrp { |
508 | fsl,pins = < | |
509 | MX51_PAD_EIM_D22__GPIO2_6 0x80000000 | |
510 | >; | |
511 | }; | |
512 | ||
dd0c672a AS |
513 | pinctrl_i2c1: i2c1grp { |
514 | fsl,pins = < | |
515 | MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed | |
516 | MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed | |
517 | >; | |
518 | }; | |
519 | ||
5a2a7d57 SG |
520 | pinctrl_i2c2: i2c2grp { |
521 | fsl,pins = < | |
522 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | |
523 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | |
524 | >; | |
525 | }; | |
526 | ||
527 | pinctrl_ipu_disp1: ipudisp1grp { | |
528 | fsl,pins = < | |
529 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | |
530 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | |
531 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | |
532 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | |
533 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | |
534 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | |
535 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | |
536 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | |
537 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | |
538 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | |
539 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | |
540 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | |
541 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | |
542 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | |
543 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | |
544 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | |
545 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | |
546 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | |
547 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | |
548 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | |
549 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | |
550 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | |
551 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | |
552 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | |
553 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 | |
554 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 | |
555 | >; | |
556 | }; | |
557 | ||
558 | pinctrl_ipu_disp2: ipudisp2grp { | |
559 | fsl,pins = < | |
560 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | |
561 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | |
562 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | |
563 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | |
564 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | |
565 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | |
566 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | |
567 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | |
568 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | |
569 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | |
570 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | |
571 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | |
572 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | |
573 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | |
574 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | |
575 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | |
576 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 | |
577 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 | |
578 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 | |
579 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 | |
580 | >; | |
581 | }; | |
582 | ||
583 | pinctrl_kpp: kppgrp { | |
584 | fsl,pins = < | |
585 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | |
586 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | |
587 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | |
588 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | |
589 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | |
590 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | |
591 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | |
592 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | |
593 | >; | |
594 | }; | |
595 | ||
1ddcff4b AS |
596 | pinctrl_pmic: pmicgrp { |
597 | fsl,pins = < | |
598 | MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ | |
599 | >; | |
600 | }; | |
601 | ||
5a2a7d57 SG |
602 | pinctrl_uart1: uart1grp { |
603 | fsl,pins = < | |
604 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | |
605 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | |
606 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | |
607 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | |
608 | >; | |
609 | }; | |
610 | ||
611 | pinctrl_uart2: uart2grp { | |
612 | fsl,pins = < | |
613 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | |
614 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | |
615 | >; | |
616 | }; | |
617 | ||
618 | pinctrl_uart3: uart3grp { | |
619 | fsl,pins = < | |
620 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | |
621 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | |
622 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | |
623 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | |
624 | >; | |
625 | }; | |
9bf206a9 FE |
626 | |
627 | pinctrl_usbh1: usbh1grp { | |
628 | fsl,pins = < | |
629 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 | |
630 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 | |
631 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 | |
632 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 | |
633 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 | |
634 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 | |
635 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 | |
636 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 | |
637 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 | |
638 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 | |
639 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 | |
2ccc447c AS |
640 | >; |
641 | }; | |
642 | ||
db8235ec | 643 | pinctrl_usbh1reg: usbh1reggrp { |
2ccc447c AS |
644 | fsl,pins = < |
645 | MX51_PAD_EIM_D21__GPIO2_5 0x85 | |
9bf206a9 FE |
646 | >; |
647 | }; | |
db8235ec AS |
648 | |
649 | pinctrl_usbotgreg: usbotgreggrp { | |
650 | fsl,pins = < | |
651 | MX51_PAD_GPIO1_7__GPIO1_7 0x85 | |
652 | >; | |
653 | }; | |
be4ccfce SG |
654 | }; |
655 | }; |