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ARM: dts: imx51: Add IPU ports and endpoints, move imx-drm node to dtsi
[deliverable/linux.git] / arch / arm / boot / dts / imx51.dtsi
CommitLineData
9daaf31a
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
e1641531 14#include "imx51-pinfunc.h"
9daaf31a
SG		 15
16/ {
17 aliases {
5230f8fe
SG		 18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
e3b73c68
SH		 22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &cspi;
9daaf31a
SG		 30 };
31
32 tzic: tz-interrupt-controller@e0000000 {
33 compatible = "fsl,imx51-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0xe0000000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
677e28b1 50 clock-frequency = <0>;
9daaf31a
SG		 51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
6f9d62d4
MP		 64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a8";
70 reg = <0>;
71 clock-latency = <61036>; /* two CLK32 periods */
72 clocks = <&clks 24>;
73 clock-names = "cpu";
74 operating-points = <
75 /* kHz uV (No regulator support) */
76 160000 0
77 800000 0
78 >;
79 };
80 };
81
de10e04e
PZ		 82 display-subsystem {
83 compatible = "fsl,imx-display-subsystem";
84 ports = <&ipu_di0>, <&ipu_di1>;
85 };
86
9daaf31a
SG		 87 soc {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "simple-bus";
91 interrupt-parent = <&tzic>;
92 ranges;
93
da38ea33
AS		 94 iram: iram@1ffe0000 {
95 compatible = "mmio-sram";
96 reg = <0x1ffe0000 0x20000>;
97 };
98
b5af6b10 99 ipu: ipu@40000000 {
de10e04e
PZ		 100 #address-cells = <1>;
101 #size-cells = <0>;
b5af6b10
SH		 102 compatible = "fsl,imx51-ipu";
103 reg = <0x40000000 0x20000000>;
104 interrupts = <11 10>;
4438a6a1
PZ		 105 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
106 clock-names = "bus", "di0", "di1";
8d84c374 107 resets = <&src 2>;
de10e04e
PZ		 108
109 ipu_di0: port@2 {
110 reg = <2>;
111
112 ipu_di0_disp0: endpoint {
113 };
114 };
115
116 ipu_di1: port@3 {
117 reg = <3>;
118
119 ipu_di1_disp1: endpoint {
120 };
121 };
b5af6b10
SH		 122 };
123
9daaf31a
SG		 124 aips@70000000 { /* AIPS1 */
125 compatible = "fsl,aips-bus", "simple-bus";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 reg = <0x70000000 0x10000000>;
129 ranges;
130
131 spba@70000000 {
132 compatible = "fsl,spba-bus", "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 reg = <0x70000000 0x40000>;
136 ranges;
137
7b7d6727 138 esdhc1: esdhc@70004000 {
9daaf31a
SG		 139 compatible = "fsl,imx51-esdhc";
140 reg = <0x70004000 0x4000>;
141 interrupts = <1>;
f40f38d1
FE		 142 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
143 clock-names = "ipg", "ahb", "per";
9daaf31a
SG		 144 status = "disabled";
145 };
146
7b7d6727 147 esdhc2: esdhc@70008000 {
9daaf31a
SG		 148 compatible = "fsl,imx51-esdhc";
149 reg = <0x70008000 0x4000>;
150 interrupts = <2>;
f40f38d1
FE		 151 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
152 clock-names = "ipg", "ahb", "per";
c104b6a2 153 bus-width = <4>;
9daaf31a
SG		 154 status = "disabled";
155 };
156
0c456cfa 157 uart3: serial@7000c000 {
9daaf31a
SG		 158 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
159 reg = <0x7000c000 0x4000>;
160 interrupts = <33>;
f40f38d1
FE		 161 clocks = <&clks 32>, <&clks 33>;
162 clock-names = "ipg", "per";
9daaf31a
SG		 163 status = "disabled";
164 };
165
7b7d6727 166 ecspi1: ecspi@70010000 {
9daaf31a
SG		 167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "fsl,imx51-ecspi";
170 reg = <0x70010000 0x4000>;
171 interrupts = <36>;
f40f38d1
FE		 172 clocks = <&clks 51>, <&clks 52>;
173 clock-names = "ipg", "per";
9daaf31a
SG		 174 status = "disabled";
175 };
176
a15d9f89
SG		 177 ssi2: ssi@70014000 {
178 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
179 reg = <0x70014000 0x4000>;
180 interrupts = <30>;
f40f38d1 181 clocks = <&clks 49>;
5da826ab
SG		 182 dmas = <&sdma 24 1 0>,
183 <&sdma 25 1 0>;
184 dma-names = "rx", "tx";
a15d9f89
SG		 185 fsl,fifo-depth = <15>;
186 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
187 status = "disabled";
188 };
189
7b7d6727 190 esdhc3: esdhc@70020000 {
9daaf31a
SG		 191 compatible = "fsl,imx51-esdhc";
192 reg = <0x70020000 0x4000>;
193 interrupts = <3>;
f40f38d1
FE		 194 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
195 clock-names = "ipg", "ahb", "per";
c104b6a2 196 bus-width = <4>;
9daaf31a
SG		 197 status = "disabled";
198 };
199
7b7d6727 200 esdhc4: esdhc@70024000 {
9daaf31a
SG		 201 compatible = "fsl,imx51-esdhc";
202 reg = <0x70024000 0x4000>;
203 interrupts = <4>;
f40f38d1
FE		 204 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
205 clock-names = "ipg", "ahb", "per";
c104b6a2 206 bus-width = <4>;
9daaf31a
SG		 207 status = "disabled";
208 };
209 };
210
a79025c4
MG		 211 usbphy0: usbphy@0 {
212 compatible = "usb-nop-xceiv";
036e2991 213 clocks = <&clks 75>;
a79025c4
MG		 214 clock-names = "main_clk";
215 status = "okay";
216 };
217
7b7d6727 218 usbotg: usb@73f80000 {
212d0b83
MG		 219 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
220 reg = <0x73f80000 0x0200>;
221 interrupts = <18>;
8e388908 222 clocks = <&clks 108>;
a5735021 223 fsl,usbmisc = <&usbmisc 0>;
a79025c4 224 fsl,usbphy = <&usbphy0>;
212d0b83
MG		 225 status = "disabled";
226 };
227
7b7d6727 228 usbh1: usb@73f80200 {
212d0b83
MG		 229 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
230 reg = <0x73f80200 0x0200>;
231 interrupts = <14>;
8e388908 232 clocks = <&clks 108>;
a5735021 233 fsl,usbmisc = <&usbmisc 1>;
212d0b83
MG		 234 status = "disabled";
235 };
236
7b7d6727 237 usbh2: usb@73f80400 {
212d0b83
MG		 238 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
239 reg = <0x73f80400 0x0200>;
240 interrupts = <16>;
8e388908 241 clocks = <&clks 108>;
a5735021 242 fsl,usbmisc = <&usbmisc 2>;
212d0b83
MG		 243 status = "disabled";
244 };
245
7b7d6727 246 usbh3: usb@73f80600 {
212d0b83
MG		 247 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
248 reg = <0x73f80600 0x0200>;
249 interrupts = <17>;
8e388908 250 clocks = <&clks 108>;
a5735021 251 fsl,usbmisc = <&usbmisc 3>;
212d0b83
MG		 252 status = "disabled";
253 };
254
a5735021
MG		 255 usbmisc: usbmisc@73f80800 {
256 #index-cells = <1>;
257 compatible = "fsl,imx51-usbmisc";
258 reg = <0x73f80800 0x200>;
8e388908 259 clocks = <&clks 108>;
a5735021
MG		 260 };
261
4d191868 262 gpio1: gpio@73f84000 {
aeb27748 263 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a
SG		 264 reg = <0x73f84000 0x4000>;
265 interrupts = <50 51>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
88cde8b7 269 #interrupt-cells = <2>;
9daaf31a
SG		 270 };
271
4d191868 272 gpio2: gpio@73f88000 {
aeb27748 273 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a
SG		 274 reg = <0x73f88000 0x4000>;
275 interrupts = <52 53>;
276 gpio-controller;
277 #gpio-cells = <2>;
278 interrupt-controller;
88cde8b7 279 #interrupt-cells = <2>;
9daaf31a
SG		 280 };
281
4d191868 282 gpio3: gpio@73f8c000 {
aeb27748 283 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a
SG		 284 reg = <0x73f8c000 0x4000>;
285 interrupts = <54 55>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
88cde8b7 289 #interrupt-cells = <2>;
9daaf31a
SG		 290 };
291
4d191868 292 gpio4: gpio@73f90000 {
aeb27748 293 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a
SG		 294 reg = <0x73f90000 0x4000>;
295 interrupts = <56 57>;
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
88cde8b7 299 #interrupt-cells = <2>;
9daaf31a
SG		 300 };
301
6012555c
LY		 302 kpp: kpp@73f94000 {
303 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
304 reg = <0x73f94000 0x4000>;
305 interrupts = <60>;
306 clocks = <&clks 0>;
307 status = "disabled";
308 };
309
7b7d6727 310 wdog1: wdog@73f98000 {
9daaf31a
SG		 311 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
312 reg = <0x73f98000 0x4000>;
313 interrupts = <58>;
f40f38d1 314 clocks = <&clks 0>;
9daaf31a
SG		 315 };
316
7b7d6727 317 wdog2: wdog@73f9c000 {
9daaf31a
SG		 318 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
319 reg = <0x73f9c000 0x4000>;
320 interrupts = <59>;
f40f38d1 321 clocks = <&clks 0>;
9daaf31a
SG		 322 status = "disabled";
323 };
324
ed73c63a
SH		 325 gpt: timer@73fa0000 {
326 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
327 reg = <0x73fa0000 0x4000>;
328 interrupts = <39>;
329 clocks = <&clks 36>, <&clks 41>;
330 clock-names = "ipg", "per";
331 };
332
7b7d6727 333 iomuxc: iomuxc@73fa8000 {
b72cf105
SG		 334 compatible = "fsl,imx51-iomuxc";
335 reg = <0x73fa8000 0x4000>;
b72cf105
SG		 336 };
337
82a618da
SH		 338 pwm1: pwm@73fb4000 {
339 #pwm-cells = <2>;
340 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
341 reg = <0x73fb4000 0x4000>;
342 clocks = <&clks 37>, <&clks 38>;
343 clock-names = "ipg", "per";
344 interrupts = <61>;
345 };
346
347 pwm2: pwm@73fb8000 {
348 #pwm-cells = <2>;
349 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
350 reg = <0x73fb8000 0x4000>;
351 clocks = <&clks 39>, <&clks 40>;
352 clock-names = "ipg", "per";
353 interrupts = <94>;
354 };
355
0c456cfa 356 uart1: serial@73fbc000 {
9daaf31a
SG		 357 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
358 reg = <0x73fbc000 0x4000>;
359 interrupts = <31>;
f40f38d1
FE		 360 clocks = <&clks 28>, <&clks 29>;
361 clock-names = "ipg", "per";
9daaf31a
SG		 362 status = "disabled";
363 };
364
0c456cfa 365 uart2: serial@73fc0000 {
9daaf31a
SG		 366 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
367 reg = <0x73fc0000 0x4000>;
368 interrupts = <32>;
f40f38d1
FE		 369 clocks = <&clks 30>, <&clks 31>;
370 clock-names = "ipg", "per";
9daaf31a
SG		 371 status = "disabled";
372 };
f40f38d1 373
8d84c374
PZ		 374 src: src@73fd0000 {
375 compatible = "fsl,imx51-src";
376 reg = <0x73fd0000 0x4000>;
377 #reset-cells = <1>;
378 };
379
f40f38d1
FE		 380 clks: ccm@73fd4000{
381 compatible = "fsl,imx51-ccm";
382 reg = <0x73fd4000 0x4000>;
383 interrupts = <0 71 0x04 0 72 0x04>;
384 #clock-cells = <1>;
385 };
9daaf31a
SG		 386 };
387
388 aips@80000000 { /* AIPS2 */
389 compatible = "fsl,aips-bus", "simple-bus";
390 #address-cells = <1>;
391 #size-cells = <1>;
392 reg = <0x80000000 0x10000000>;
393 ranges;
394
6510ea25
SH		 395 iim: iim@83f98000 {
396 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
397 reg = <0x83f98000 0x4000>;
398 interrupts = <69>;
399 clocks = <&clks 107>;
400 };
401
ad15f08c
AS		 402 owire: owire@83fa4000 {
403 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
404 reg = <0x83fa4000 0x4000>;
405 interrupts = <88>;
406 clocks = <&clks 159>;
407 status = "disabled";
408 };
409
7b7d6727 410 ecspi2: ecspi@83fac000 {
9daaf31a
SG		 411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "fsl,imx51-ecspi";
414 reg = <0x83fac000 0x4000>;
415 interrupts = <37>;
f40f38d1
FE		 416 clocks = <&clks 53>, <&clks 54>;
417 clock-names = "ipg", "per";
9daaf31a
SG		 418 status = "disabled";
419 };
420
7b7d6727 421 sdma: sdma@83fb0000 {
9daaf31a
SG		 422 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
423 reg = <0x83fb0000 0x4000>;
424 interrupts = <6>;
f40f38d1
FE		 425 clocks = <&clks 56>, <&clks 56>;
426 clock-names = "ipg", "ahb";
fb72bb21 427 #dma-cells = <3>;
7e4f0365 428 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
9daaf31a
SG		 429 };
430
7b7d6727 431 cspi: cspi@83fc0000 {
9daaf31a
SG		 432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
435 reg = <0x83fc0000 0x4000>;
436 interrupts = <38>;
37523dc5 437 clocks = <&clks 55>, <&clks 55>;
f40f38d1 438 clock-names = "ipg", "per";
9daaf31a
SG		 439 status = "disabled";
440 };
441
7b7d6727 442 i2c2: i2c@83fc4000 {
9daaf31a
SG		 443 #address-cells = <1>;
444 #size-cells = <0>;
5bdfba29 445 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
9daaf31a
SG		 446 reg = <0x83fc4000 0x4000>;
447 interrupts = <63>;
f40f38d1 448 clocks = <&clks 35>;
9daaf31a
SG		 449 status = "disabled";
450 };
451
7b7d6727 452 i2c1: i2c@83fc8000 {
9daaf31a
SG		 453 #address-cells = <1>;
454 #size-cells = <0>;
5bdfba29 455 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
9daaf31a
SG		 456 reg = <0x83fc8000 0x4000>;
457 interrupts = <62>;
f40f38d1 458 clocks = <&clks 34>;
9daaf31a
SG		 459 status = "disabled";
460 };
461
a15d9f89
SG		 462 ssi1: ssi@83fcc000 {
463 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
464 reg = <0x83fcc000 0x4000>;
465 interrupts = <29>;
f40f38d1 466 clocks = <&clks 48>;
5da826ab
SG		 467 dmas = <&sdma 28 0 0>,
468 <&sdma 29 0 0>;
469 dma-names = "rx", "tx";
a15d9f89
SG		 470 fsl,fifo-depth = <15>;
471 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
472 status = "disabled";
473 };
474
7b7d6727 475 audmux: audmux@83fd0000 {
a15d9f89
SG		 476 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
477 reg = <0x83fd0000 0x4000>;
478 status = "disabled";
479 };
480
edd05286
AS		 481 weim: weim@83fda000 {
482 #address-cells = <2>;
483 #size-cells = <1>;
484 compatible = "fsl,imx51-weim";
485 reg = <0x83fda000 0x1000>;
486 clocks = <&clks 57>;
487 ranges = <
488 0 0 0xb0000000 0x08000000
489 1 0 0xb8000000 0x08000000
490 2 0 0xc0000000 0x08000000
491 3 0 0xc8000000 0x04000000
492 4 0 0xcc000000 0x02000000
493 5 0 0xce000000 0x02000000
494 >;
495 status = "disabled";
496 };
497
7b7d6727 498 nfc: nand@83fdb000 {
75453a08
SH		 499 compatible = "fsl,imx51-nand";
500 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
501 interrupts = <8>;
f40f38d1 502 clocks = <&clks 60>;
75453a08
SH		 503 status = "disabled";
504 };
505
718a3500
SH		 506 pata: pata@83fe0000 {
507 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
508 reg = <0x83fe0000 0x4000>;
509 interrupts = <70>;
6a030ee3 510 clocks = <&clks 172>;
718a3500
SH		 511 status = "disabled";
512 };
513
a15d9f89
SG		 514 ssi3: ssi@83fe8000 {
515 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
516 reg = <0x83fe8000 0x4000>;
517 interrupts = <96>;
f40f38d1 518 clocks = <&clks 50>;
5da826ab
SG		 519 dmas = <&sdma 46 0 0>,
520 <&sdma 47 0 0>;
521 dma-names = "rx", "tx";
a15d9f89
SG		 522 fsl,fifo-depth = <15>;
523 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
524 status = "disabled";
525 };
526
7b7d6727 527 fec: ethernet@83fec000 {
9daaf31a
SG		 528 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
529 reg = <0x83fec000 0x4000>;
530 interrupts = <87>;
f40f38d1
FE		 531 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
532 clock-names = "ipg", "ahb", "ptp";
9daaf31a
SG		 533 status = "disabled";
534 };
535 };
536 };
537};
35878142
AS		 538
539&iomuxc {
540 audmux {
541 pinctrl_audmux_1: audmuxgrp-1 {
542 fsl,pins = <
543 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
544 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
545 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
546 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
547 >;
548 };
549 };
550
551 fec {
552 pinctrl_fec_1: fecgrp-1 {
553 fsl,pins = <
554 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
555 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
556 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
557 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
558 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
559 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
560 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
561 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
562 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
563 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
564 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
565 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
566 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
567 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
568 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
569 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
570 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
571 >;
572 };
573
574 pinctrl_fec_2: fecgrp-2 {
575 fsl,pins = <
576 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
577 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
578 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
579 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
580 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
581 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
582 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
583 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
584 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
585 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
586 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
587 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
588 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
589 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
590 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
591 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
592 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
593 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
594 >;
595 };
596 };
597
598 ecspi1 {
599 pinctrl_ecspi1_1: ecspi1grp-1 {
600 fsl,pins = <
601 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
602 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
603 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
604 >;
605 };
606 };
607
608 ecspi2 {
609 pinctrl_ecspi2_1: ecspi2grp-1 {
610 fsl,pins = <
611 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
612 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
613 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
614 >;
615 };
616 };
617
618 esdhc1 {
619 pinctrl_esdhc1_1: esdhc1grp-1 {
620 fsl,pins = <
621 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
622 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
623 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
624 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
625 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
626 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
627 >;
628 };
629 };
630
631 esdhc2 {
632 pinctrl_esdhc2_1: esdhc2grp-1 {
633 fsl,pins = <
634 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
635 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
636 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
637 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
638 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
639 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
640 >;
641 };
642 };
643
644 i2c2 {
645 pinctrl_i2c2_1: i2c2grp-1 {
646 fsl,pins = <
647 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
648 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
649 >;
650 };
651
652 pinctrl_i2c2_2: i2c2grp-2 {
653 fsl,pins = <
654 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
655 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
656 >;
657 };
10ed76d7
AS		 658
659 pinctrl_i2c2_3: i2c2grp-3 {
660 fsl,pins = <
661 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
662 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
663 >;
664 };
35878142
AS		 665 };
666
667 ipu_disp1 {
668 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
669 fsl,pins = <
670 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
671 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
672 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
673 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
674 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
675 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
676 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
677 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
678 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
679 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
680 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
681 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
682 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
683 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
684 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
685 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
686 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
687 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
688 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
689 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
690 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
691 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
692 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
693 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
694 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
695 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
696 >;
697 };
698 };
699
700 ipu_disp2 {
701 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
702 fsl,pins = <
703 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
704 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
705 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
706 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
707 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
708 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
709 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
710 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
711 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
712 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
713 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
714 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
715 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
716 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
717 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
718 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
719 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
720 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
721 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
722 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
723 >;
724 };
725 };
726
727 kpp {
728 pinctrl_kpp_1: kppgrp-1 {
729 fsl,pins = <
730 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
731 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
732 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
733 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
734 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
735 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
736 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
737 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
738 >;
739 };
740 };
741
742 pata {
743 pinctrl_pata_1: patagrp-1 {
744 fsl,pins = <
745 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
746 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
747 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
748 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
749 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
750 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
751 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
752 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
753 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
754 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
755 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
756 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
757 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
758 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
759 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
760 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
761 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
762 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
763 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
764 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
765 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
766 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
767 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
768 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
769 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
770 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
771 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
772 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
773 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
774 >;
775 };
776 };
777
778 uart1 {
779 pinctrl_uart1_1: uart1grp-1 {
780 fsl,pins = <
781 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
782 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
727b8124
AS		 783 >;
784 };
785
786 pinctrl_uart1_rtscts_1: uart1rtscts-1 {
787 fsl,pins = <
35878142
AS		 788 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
789 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
790 >;
791 };
792 };
793
794 uart2 {
795 pinctrl_uart2_1: uart2grp-1 {
796 fsl,pins = <
797 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
798 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
799 >;
800 };
801 };
802
803 uart3 {
804 pinctrl_uart3_1: uart3grp-1 {
805 fsl,pins = <
806 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
807 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
727b8124
AS		 808 >;
809 };
810
811 pinctrl_uart3_rtscts_1: uart3rtscts-1 {
812 fsl,pins = <
35878142
AS		 813 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
814 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
815 >;
816 };
817
818 pinctrl_uart3_2: uart3grp-2 {
819 fsl,pins = <
820 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
821 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
822 >;
823 };
824 };
825
826 usbh1 {
827 pinctrl_usbh1_1: usbh1grp-1 {
828 fsl,pins = <
829 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
830 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
831 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
832 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
833 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
834 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
835 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
836 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
837 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
838 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
839 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
840 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
841 >;
842 };
843 };
844
845 usbh2 {
846 pinctrl_usbh2_1: usbh2grp-1 {
847 fsl,pins = <
848 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
849 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
850 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
851 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
852 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
853 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
854 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
855 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
856 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
857 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
858 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
859 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
860 >;
861 };
862 };
863};
Linux kernel - Deliverables
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