[deliverable/linux.git] / arch / arm / boot / dts / imx53-mba53.dts

/*
 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx53-tqma53.dtsi"

/ {
	model = "TQ MBa53 starter kit";
	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";

	chosen {
		stdout-path = &uart2;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm2 0 50000>;
		brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
		default-brightness-level = <10>;
		enable-gpios = <&gpio7 7 0>;
		power-supply = <&reg_backlight>;
	};

	disp1: display@disp1 {
		compatible = "fsl,imx-parallel-display";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_disp1_1>;
		interface-pix-fmt = "rgb24";
		status = "disabled";

		port {
			display1_in: endpoint {
				remote-endpoint = <&ipu_di1_disp1>;
			};
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_backlight: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "lcd-supply";
			gpio = <&gpio2 5 0>;
			startup-delay-us = <5000>;
		};

		reg_3p2v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "3P2V";
			regulator-min-microvolt = <3200000>;
			regulator-max-microvolt = <3200000>;
			regulator-always-on;
		};
	};

	sound {
		compatible = "tq,imx53-mba53-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx53-mba53-sgtl5000";
		ssi-controller = <&ssi2>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <2>;
		mux-ext-port = <5>;
	};
};

&ldb {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds1_1>;
	status = "disabled";
};

&iomuxc {
	lvds1 {
		pinctrl_lvds1_1: lvds1-grp1 {
			fsl,pins = <
				MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
				MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
				MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
				MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
				MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
			>;
		};

		pinctrl_lvds1_2: lvds1-grp2 {
			fsl,pins = <
				MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
				MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
				MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
				MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
				MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
			>;
		};
	};

	disp1 {
		pinctrl_disp1_1: disp1-grp1 {
			fsl,pins = <
				MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
				MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
				MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
				MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
				MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
				MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
				MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
				MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
				MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
				MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
				MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
				MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
				MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
				MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
				MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
				MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
				MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
				MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
				MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
				MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
				MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
				MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
				MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
				MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
				MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
				MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
				MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
				MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
			>;
		};
	};

	tve {
		pinctrl_vga_sync_1: vgasync-grp1 {
			fsl,pins = <
				/* VGA_VSYNC, HSYNC with max drive strength */
				MX53_PAD_EIM_CS1__IPU_DI1_PIN6	   0xe6
				MX53_PAD_EIM_DA15__IPU_DI1_PIN4	   0xe6
			>;
		};
	};
};

&ipu_di1_disp1 {
	remote-endpoint = <&display1_in>;
};

&cspi {
	status = "okay";
};

&audmux {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
};

&i2c2 {
	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
		VDDA-supply = <&reg_3p2v>;
		VDDIO-supply = <&reg_3p2v>;
	};

	expander: pca9554@20 {
		compatible = "pca9554";
		reg = <0x20>;
		interrupts = <109>;
		#gpio-cells = <2>;
		gpio-controller;
	};

	sensor2: lm75@49 {
		compatible = "lm75";
		reg = <0x49>;
	};
};

&fec {
	phy-reset-gpios = <&gpio7 6 0>;
	status = "okay";
};

&esdhc2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&ecspi1 {
	status = "okay";
};

&usbotg {
	dr_mode = "host";
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&ssi2 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart2 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&can2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&tve {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_vga_sync_1>;
	ddc-i2c-bus = <&i2c3>;
	fsl,tve-mode = "vga";
	fsl,hsync-pin = <4>;
	fsl,vsync-pin = <6>;
	status = "okay";
};
Commit	Line	Data
be3a568d ST	1	/*
	2	* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
	3	* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/dts-v1/;
36dffd8f	14	#include "imx53-tqma53.dtsi"
be3a568d ST	15
	16	/ {
	17	model = "TQ MBa53 starter kit";
	18	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
4fa8cf79	19
48f51963 SH	20	chosen {
	21	stdout-path = &uart2;
	22	};
	23
4fa8cf79 SH	24	backlight {
4fa8cf79 SH	25	compatible = "pwm-backlight";
15968f1b	26	pwms = <&pwm2 0 50000>;
4fa8cf79 SH	27	brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
	28	default-brightness-level = <10>;
	29	enable-gpios = <&gpio7 7 0>;
	30	power-supply = <&reg_backlight>;
	31	};
	32
	33	disp1: display@disp1 {
	34	compatible = "fsl,imx-parallel-display";
	35	pinctrl-names = "default";
	36	pinctrl-0 = <&pinctrl_disp1_1>;
4fa8cf79 SH	37	interface-pix-fmt = "rgb24";
4fa8cf79 SH	38	status = "disabled";
eefb8008	39
e05c8c9a PZ	40	port {
	41	display1_in: endpoint {
	42	remote-endpoint = <&ipu_di1_disp1>;
	43	};
	44	};
17b5001b RK	45	};
17b5001b RK	46
a4a2aa9b SG	47	regulators {
a4a2aa9b SG	48	compatible = "simple-bus";
352d318c SG	49	#address-cells = <1>;
352d318c SG	50	#size-cells = <0>;
a4a2aa9b	51
352d318c	52	reg_backlight: regulator@0 {
a4a2aa9b	53	compatible = "regulator-fixed";
352d318c	54	reg = <0>;
a4a2aa9b SG	55	regulator-name = "lcd-supply";
	56	gpio = <&gpio2 5 0>;
	57	startup-delay-us = <5000>;
a4a2aa9b SG	58	};
a4a2aa9b SG	59
352d318c	60	reg_3p2v: regulator@1 {
a4a2aa9b	61	compatible = "regulator-fixed";
352d318c	62	reg = <1>;
a4a2aa9b SG	63	regulator-name = "3P2V";
	64	regulator-min-microvolt = <3200000>;
	65	regulator-max-microvolt = <3200000>;
	66	regulator-always-on;
	67	};
eefb8008 MN	68	};
	69
	70	sound {
	71	compatible = "tq,imx53-mba53-sgtl5000",
	72	"fsl,imx-audio-sgtl5000";
	73	model = "imx53-mba53-sgtl5000";
	74	ssi-controller = <&ssi2>;
	75	audio-codec = <&codec>;
	76	audio-routing =
	77	"MIC_IN", "Mic Jack",
	78	"Mic Jack", "Mic Bias",
	79	"Headphone Jack", "HP_OUT";
	80	mux-int-port = <2>;
	81	mux-ext-port = <5>;
	82	};
4fa8cf79 SH	83	};
	84
	85	&ldb {
	86	pinctrl-names = "default";
	87	pinctrl-0 = <&pinctrl_lvds1_1>;
	88	status = "disabled";
be3a568d ST	89	};
	90
	91	&iomuxc {
	92	lvds1 {
	93	pinctrl_lvds1_1: lvds1-grp1 {
e1641531	94	fsl,pins = <
188e97db ST	95	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
	96	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
	97	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
	98	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
	99	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
e1641531	100	>;
be3a568d ST	101	};
	102
	103	pinctrl_lvds1_2: lvds1-grp2 {
e1641531	104	fsl,pins = <
188e97db ST	105	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
	106	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
	107	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
	108	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
	109	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
e1641531	110	>;
be3a568d ST	111	};
	112	};
	113
	114	disp1 {
	115	pinctrl_disp1_1: disp1-grp1 {
e1641531	116	fsl,pins = <
81b8a3cd	117	MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
188e97db ST	118	MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
	119	MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
	120	MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
	121	MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
	122	MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
	123	MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
	124	MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
	125	MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
	126	MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
	127	MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
	128	MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
	129	MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
	130	MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
	131	MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
	132	MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
	133	MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
	134	MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
	135	MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
	136	MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
	137	MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
	138	MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
	139	MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
	140	MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
	141	MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
	142	MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
	143	MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
	144	MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
e1641531	145	>;
be3a568d ST	146	};
be3a568d ST	147	};
d7db5392 PZ	148
	149	tve {
	150	pinctrl_vga_sync_1: vgasync-grp1 {
	151	fsl,pins = <
	152	/* VGA_VSYNC, HSYNC with max drive strength */
	153	MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
	154	MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
	155	>;
	156	};
	157	};
be3a568d ST	158	};
be3a568d ST	159
e05c8c9a PZ	160	&ipu_di1_disp1 {
	161	remote-endpoint = <&display1_in>;
	162	};
	163
be3a568d ST	164	&cspi {
	165	status = "okay";
	166	};
	167
eefb8008 MN	168	&audmux {
	169	status = "okay";
	170	pinctrl-names = "default";
7ac0f700	171	pinctrl-0 = <&pinctrl_audmux>;
eefb8008 MN	172	};
eefb8008 MN	173
be3a568d ST	174	&i2c2 {
	175	codec: sgtl5000@a {
	176	compatible = "fsl,sgtl5000";
	177	reg = <0x0a>;
564695dd	178	clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
eefb8008 MN	179	VDDA-supply = <&reg_3p2v>;
eefb8008 MN	180	VDDIO-supply = <&reg_3p2v>;
be3a568d ST	181	};
	182
	183	expander: pca9554@20 {
	184	compatible = "pca9554";
	185	reg = <0x20>;
	186	interrupts = <109>;
74154be0 MN	187	#gpio-cells = <2>;
74154be0 MN	188	gpio-controller;
be3a568d ST	189	};
	190
	191	sensor2: lm75@49 {
	192	compatible = "lm75";
	193	reg = <0x49>;
	194	};
	195	};
	196
	197	&fec {
deb19eb7	198	phy-reset-gpios = <&gpio7 6 0>;
be3a568d ST	199	status = "okay";
	200	};
	201
	202	&esdhc2 {
	203	status = "okay";
	204	};
	205
	206	&uart3 {
	207	status = "okay";
	208	};
	209
	210	&ecspi1 {
	211	status = "okay";
	212	};
	213
3b1a0f23 MO	214	&usbotg {
	215	dr_mode = "host";
	216	status = "okay";
	217	};
	218
	219	&usbh1 {
	220	status = "okay";
	221	};
	222
be3a568d ST	223	&uart1 {
	224	status = "okay";
	225	};
	226
eefb8008 MN	227	&ssi2 {
	228	fsl,mode = "i2s-slave";
	229	status = "okay";
	230	};
	231
be3a568d ST	232	&uart2 {
	233	status = "okay";
	234	};
	235
	236	&can1 {
	237	status = "okay";
	238	};
	239
	240	&can2 {
	241	status = "okay";
	242	};
	243
	244	&i2c3 {
	245	status = "okay";
	246	};
d7db5392 PZ	247
	248	&tve {
	249	pinctrl-names = "default";
	250	pinctrl-0 = <&pinctrl_vga_sync_1>;
a3fe9641	251	ddc-i2c-bus = <&i2c3>;
d7db5392 PZ	252	fsl,tve-mode = "vga";
	253	fsl,hsync-pin = <4>;
	254	fsl,vsync-pin = <6>;
	255	status = "okay";
	256	};