[deliverable/linux.git] / arch / arm / boot / dts / imx53-mba53.dts

/*
 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx53-tqma53.dtsi"

/ {
	model = "TQ MBa53 starter kit";
	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";

	reg_backlight: fixed@0 {
		compatible = "regulator-fixed";
		regulator-name = "lcd-supply";
		gpio = <&gpio2 5 0>;
		startup-delay-us = <5000>;
		enable-active-low;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm2 0 50000 0 0>;
		brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
		default-brightness-level = <10>;
		enable-gpios = <&gpio7 7 0>;
		power-supply = <&reg_backlight>;
	};

	disp1: display@disp1 {
		compatible = "fsl,imx-parallel-display";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_disp1_1>;
		crtcs = <&ipu 1>;
		interface-pix-fmt = "rgb24";
		status = "disabled";
	};
};

&ldb {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds1_1>;
	status = "disabled";
};

&iomuxc {
	lvds1 {
		pinctrl_lvds1_1: lvds1-grp1 {
			fsl,pins = <
				MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
				MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
				MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
				MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
				MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
			>;
		};

		pinctrl_lvds1_2: lvds1-grp2 {
			fsl,pins = <
				MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
				MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
				MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
				MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
				MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
			>;
		};
	};

	disp1 {
		pinctrl_disp1_1: disp1-grp1 {
			fsl,pins = <
				MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x10000 /* DISP1_DRDY */
				MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x10000 /* DISP1_HSYNC */
				MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x10000 /* DISP1_VSYNC */
				MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
				MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
				MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
				MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
				MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
				MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
				MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
				MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
				MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
				MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
				MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
				MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
				MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
				MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
				MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x10000
				MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x10000
				MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x10000
				MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x10000
				MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x10000
				MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x10000
				MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x10000
				MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x10000
				MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x10000
				MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x10000
			>;
		};
	};

	tve {
		pinctrl_vga_sync_1: vgasync-grp1 {
			fsl,pins = <
				/* VGA_VSYNC, HSYNC with max drive strength */
				MX53_PAD_EIM_CS1__IPU_DI1_PIN6	   0xe6
				MX53_PAD_EIM_DA15__IPU_DI1_PIN4	   0xe6
			>;
		};
	};
};

&cspi {
	status = "okay";
};

&i2c2 {
	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
	};

	expander: pca9554@20 {
		compatible = "pca9554";
		reg = <0x20>;
		interrupts = <109>;
	};

	sensor2: lm75@49 {
		compatible = "lm75";
		reg = <0x49>;
	};
};

&fec {
	status = "okay";
};

&esdhc2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&ecspi1 {
	status = "okay";
};

&usbotg {
	dr_mode = "host";
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&can2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&tve {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_vga_sync_1>;
	ddc = <&i2c3>;
	fsl,tve-mode = "vga";
	fsl,hsync-pin = <4>;
	fsl,vsync-pin = <6>;
	status = "okay";
};
Commit	Line	Data
be3a568d ST	1	/*
	2	* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
	3	* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/dts-v1/;
36dffd8f	14	#include "imx53-tqma53.dtsi"
be3a568d ST	15
	16	/ {
	17	model = "TQ MBa53 starter kit";
	18	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
4fa8cf79 SH	19
	20	reg_backlight: fixed@0 {
	21	compatible = "regulator-fixed";
	22	regulator-name = "lcd-supply";
	23	gpio = <&gpio2 5 0>;
	24	startup-delay-us = <5000>;
	25	enable-active-low;
	26	};
	27
	28	backlight {
	29	compatible = "pwm-backlight";
	30	pwms = <&pwm2 0 50000 0 0>;
	31	brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
	32	default-brightness-level = <10>;
	33	enable-gpios = <&gpio7 7 0>;
	34	power-supply = <&reg_backlight>;
	35	};
	36
	37	disp1: display@disp1 {
	38	compatible = "fsl,imx-parallel-display";
	39	pinctrl-names = "default";
	40	pinctrl-0 = <&pinctrl_disp1_1>;
	41	crtcs = <&ipu 1>;
	42	interface-pix-fmt = "rgb24";
	43	status = "disabled";
	44	};
	45	};
	46
	47	&ldb {
	48	pinctrl-names = "default";
	49	pinctrl-0 = <&pinctrl_lvds1_1>;
	50	status = "disabled";
be3a568d ST	51	};
	52
	53	&iomuxc {
	54	lvds1 {
	55	pinctrl_lvds1_1: lvds1-grp1 {
e1641531 SG	56	fsl,pins = <
	57	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
	58	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
	59	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
	60	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
	61	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
	62	>;
be3a568d ST	63	};
	64
	65	pinctrl_lvds1_2: lvds1-grp2 {
e1641531 SG	66	fsl,pins = <
	67	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
	68	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
	69	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
	70	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
	71	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
	72	>;
be3a568d ST	73	};
	74	};
	75
	76	disp1 {
	77	pinctrl_disp1_1: disp1-grp1 {
e1641531 SG	78	fsl,pins = <
	79	MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */
	80	MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */
	81	MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */
	82	MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
	83	MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
	84	MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
	85	MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
	86	MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
	87	MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
	88	MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
	89	MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
	90	MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
	91	MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
	92	MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
	93	MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
	94	MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
	95	MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
	96	MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000
	97	MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000
	98	MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000
	99	MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000
	100	MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000
	101	MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000
	102	MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000
	103	MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000
	104	MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000
	105	MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000
	106	>;
be3a568d ST	107	};
be3a568d ST	108	};
d7db5392 PZ	109
	110	tve {
	111	pinctrl_vga_sync_1: vgasync-grp1 {
	112	fsl,pins = <
	113	/* VGA_VSYNC, HSYNC with max drive strength */
	114	MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
	115	MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
	116	>;
	117	};
	118	};
be3a568d ST	119	};
	120
	121	&cspi {
	122	status = "okay";
	123	};
	124
	125	&i2c2 {
	126	codec: sgtl5000@a {
	127	compatible = "fsl,sgtl5000";
	128	reg = <0x0a>;
	129	};
	130
	131	expander: pca9554@20 {
	132	compatible = "pca9554";
	133	reg = <0x20>;
	134	interrupts = <109>;
	135	};
	136
	137	sensor2: lm75@49 {
	138	compatible = "lm75";
	139	reg = <0x49>;
	140	};
	141	};
	142
	143	&fec {
	144	status = "okay";
	145	};
	146
	147	&esdhc2 {
	148	status = "okay";
	149	};
	150
	151	&uart3 {
	152	status = "okay";
	153	};
	154
	155	&ecspi1 {
	156	status = "okay";
	157	};
	158
3b1a0f23 MO	159	&usbotg {
	160	dr_mode = "host";
	161	status = "okay";
	162	};
	163
	164	&usbh1 {
	165	status = "okay";
	166	};
	167
be3a568d ST	168	&uart1 {
	169	status = "okay";
	170	};
	171
	172	&uart2 {
	173	status = "okay";
	174	};
	175
	176	&can1 {
	177	status = "okay";
	178	};
	179
	180	&can2 {
	181	status = "okay";
	182	};
	183
	184	&i2c3 {
	185	status = "okay";
	186	};
d7db5392 PZ	187
	188	&tve {
	189	pinctrl-names = "default";
	190	pinctrl-0 = <&pinctrl_vga_sync_1>;
	191	ddc = <&i2c3>;
	192	fsl,tve-mode = "vga";
	193	fsl,hsync-pin = <4>;
	194	fsl,vsync-pin = <6>;
	195	status = "okay";
	196	};