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ARM: ux500: enable AB8500 GPIO for HREF
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
CommitLineData
73d2b4cd
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
8f9ffecf
RZ		 17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
73d2b4cd
SG		 29 };
30
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
36 };
37
38 clocks {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 ckil {
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
45 };
46
47 ckih1 {
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
50 };
51
52 ckih2 {
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
55 };
56
57 osc {
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
68 ranges;
69
abed9a6b
SH		 70 ipu: ipu@18000000 {
71 #crtc-cells = <1>;
72 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>;
74 interrupts = <11 10>;
75 };
76
73d2b4cd
SG		 77 aips@50000000 { /* AIPS1 */
78 compatible = "fsl,aips-bus", "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0x50000000 0x10000000>;
82 ranges;
83
84 spba@50000000 {
85 compatible = "fsl,spba-bus", "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0x50000000 0x40000>;
89 ranges;
90
7b7d6727 91 esdhc1: esdhc@50004000 {
73d2b4cd
SG		 92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>;
94 interrupts = <1>;
f40f38d1
FE		 95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
c104b6a2 97 bus-width = <4>;
73d2b4cd
SG		 98 status = "disabled";
99 };
100
7b7d6727 101 esdhc2: esdhc@50008000 {
73d2b4cd
SG		 102 compatible = "fsl,imx53-esdhc";
103 reg = <0x50008000 0x4000>;
104 interrupts = <2>;
f40f38d1
FE		 105 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
106 clock-names = "ipg", "ahb", "per";
c104b6a2 107 bus-width = <4>;
73d2b4cd
SG		 108 status = "disabled";
109 };
110
0c456cfa 111 uart3: serial@5000c000 {
73d2b4cd
SG		 112 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
113 reg = <0x5000c000 0x4000>;
114 interrupts = <33>;
f40f38d1
FE		 115 clocks = <&clks 32>, <&clks 33>;
116 clock-names = "ipg", "per";
73d2b4cd
SG		 117 status = "disabled";
118 };
119
7b7d6727 120 ecspi1: ecspi@50010000 {
73d2b4cd
SG		 121 #address-cells = <1>;
122 #size-cells = <0>;
123 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
124 reg = <0x50010000 0x4000>;
125 interrupts = <36>;
f40f38d1
FE		 126 clocks = <&clks 51>, <&clks 52>;
127 clock-names = "ipg", "per";
73d2b4cd
SG		 128 status = "disabled";
129 };
130
ffc505c0
SG		 131 ssi2: ssi@50014000 {
132 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
133 reg = <0x50014000 0x4000>;
134 interrupts = <30>;
f40f38d1 135 clocks = <&clks 49>;
ffc505c0
SG		 136 fsl,fifo-depth = <15>;
137 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
138 status = "disabled";
139 };
140
7b7d6727 141 esdhc3: esdhc@50020000 {
73d2b4cd
SG		 142 compatible = "fsl,imx53-esdhc";
143 reg = <0x50020000 0x4000>;
144 interrupts = <3>;
f40f38d1
FE		 145 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
146 clock-names = "ipg", "ahb", "per";
c104b6a2 147 bus-width = <4>;
73d2b4cd
SG		 148 status = "disabled";
149 };
150
7b7d6727 151 esdhc4: esdhc@50024000 {
73d2b4cd
SG		 152 compatible = "fsl,imx53-esdhc";
153 reg = <0x50024000 0x4000>;
154 interrupts = <4>;
f40f38d1
FE		 155 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
156 clock-names = "ipg", "ahb", "per";
c104b6a2 157 bus-width = <4>;
73d2b4cd
SG		 158 status = "disabled";
159 };
160 };
161
7b7d6727 162 usbotg: usb@53f80000 {
212d0b83
MG		 163 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
164 reg = <0x53f80000 0x0200>;
165 interrupts = <18>;
166 status = "disabled";
167 };
168
7b7d6727 169 usbh1: usb@53f80200 {
212d0b83
MG		 170 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
171 reg = <0x53f80200 0x0200>;
172 interrupts = <14>;
173 status = "disabled";
174 };
175
7b7d6727 176 usbh2: usb@53f80400 {
212d0b83
MG		 177 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
178 reg = <0x53f80400 0x0200>;
179 interrupts = <16>;
180 status = "disabled";
181 };
182
7b7d6727 183 usbh3: usb@53f80600 {
212d0b83
MG		 184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
185 reg = <0x53f80600 0x0200>;
186 interrupts = <17>;
187 status = "disabled";
188 };
189
4d191868 190 gpio1: gpio@53f84000 {
aeb27748 191 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 192 reg = <0x53f84000 0x4000>;
193 interrupts = <50 51>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
88cde8b7 197 #interrupt-cells = <2>;
73d2b4cd
SG		 198 };
199
4d191868 200 gpio2: gpio@53f88000 {
aeb27748 201 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 202 reg = <0x53f88000 0x4000>;
203 interrupts = <52 53>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
88cde8b7 207 #interrupt-cells = <2>;
73d2b4cd
SG		 208 };
209
4d191868 210 gpio3: gpio@53f8c000 {
aeb27748 211 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 212 reg = <0x53f8c000 0x4000>;
213 interrupts = <54 55>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 interrupt-controller;
88cde8b7 217 #interrupt-cells = <2>;
73d2b4cd
SG		 218 };
219
4d191868 220 gpio4: gpio@53f90000 {
aeb27748 221 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 222 reg = <0x53f90000 0x4000>;
223 interrupts = <56 57>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
88cde8b7 227 #interrupt-cells = <2>;
73d2b4cd
SG		 228 };
229
7b7d6727 230 wdog1: wdog@53f98000 {
73d2b4cd
SG		 231 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
232 reg = <0x53f98000 0x4000>;
233 interrupts = <58>;
f40f38d1 234 clocks = <&clks 0>;
73d2b4cd
SG		 235 };
236
7b7d6727 237 wdog2: wdog@53f9c000 {
73d2b4cd
SG		 238 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
239 reg = <0x53f9c000 0x4000>;
240 interrupts = <59>;
f40f38d1 241 clocks = <&clks 0>;
73d2b4cd
SG		 242 status = "disabled";
243 };
244
7b7d6727 245 iomuxc: iomuxc@53fa8000 {
5be03a7b
SG		 246 compatible = "fsl,imx53-iomuxc";
247 reg = <0x53fa8000 0x4000>;
248
249 audmux {
250 pinctrl_audmux_1: audmuxgrp-1 {
251 fsl,pins = <
252 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
253 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
254 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
255 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
256 >;
257 };
258 };
259
260 fec {
261 pinctrl_fec_1: fecgrp-1 {
262 fsl,pins = <
263 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
264 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
265 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
266 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
267 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
268 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
269 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
270 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
271 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
272 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
273 >;
274 };
275 };
276
11ab21e9
ST		 277 csi {
278 pinctrl_csi_1: csigrp-1 {
279 fsl,pins = <
280 286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
281 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
282 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
283 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
284 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
285 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
286 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
287 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
288 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
289 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
290 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
291 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
292 352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
293 344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
294 336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
295 328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
296 320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
297 312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
298 304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
299 296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
300 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
301 >;
302 };
303 };
304
305 cspi {
306 pinctrl_cspi_1: cspigrp-1 {
307 fsl,pins = <
308 998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */
309 1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */
310 1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */
311 >;
312 };
313 };
314
327a79c0
SG		 315 ecspi1 {
316 pinctrl_ecspi1_1: ecspi1grp-1 {
317 fsl,pins = <
318 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
319 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
320 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
321 >;
322 };
323 };
324
5be03a7b
SG		 325 esdhc1 {
326 pinctrl_esdhc1_1: esdhc1grp-1 {
327 fsl,pins = <
328 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
329 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
330 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
331 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
332 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
333 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
334 >;
335 };
4bb6143c
SG		 336
337 pinctrl_esdhc1_2: esdhc1grp-2 {
338 fsl,pins = <
339 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
340 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
341 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
342 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
343 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
344 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
345 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
346 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
347 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
348 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
349 >;
350 };
5be03a7b
SG		 351 };
352
07248042
SG		 353 esdhc2 {
354 pinctrl_esdhc2_1: esdhc2grp-1 {
355 fsl,pins = <
356 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
357 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
358 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
359 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
360 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
361 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
362 >;
363 };
364 };
365
5be03a7b
SG		 366 esdhc3 {
367 pinctrl_esdhc3_1: esdhc3grp-1 {
368 fsl,pins = <
369 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
370 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
371 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
372 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
373 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
374 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
375 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
376 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
377 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
378 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
379 >;
380 };
381 };
382
a1fff236
RS		 383 can1 {
384 pinctrl_can1_1: can1grp-1 {
385 fsl,pins = <
386 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
387 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
388 >;
389 };
11ab21e9
ST		 390
391 pinctrl_can1_2: can1grp-2 {
392 fsl,pins = <
393 37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
394 44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
395 >;
396 };
a1fff236
RS		 397 };
398
399 can2 {
400 pinctrl_can2_1: can2grp-1 {
401 fsl,pins = <
402 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
403 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
404 >;
405 };
406 };
407
5be03a7b
SG		 408 i2c1 {
409 pinctrl_i2c1_1: i2c1grp-1 {
410 fsl,pins = <
411 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
412 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
413 >;
414 };
415 };
416
417 i2c2 {
418 pinctrl_i2c2_1: i2c2grp-1 {
419 fsl,pins = <
420 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
421 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
422 >;
423 };
424 };
425
a1fff236
RS		 426 i2c3 {
427 pinctrl_i2c3_1: i2c3grp-1 {
428 fsl,pins = <
429 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
430 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
431 >;
432 };
433 };
434
a82b7b9c
MF		 435 owire {
436 pinctrl_owire_1: owiregrp-1 {
437 fsl,pins = <
438 1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
439 >;
440 };
441 };
442
5be03a7b
SG		 443 uart1 {
444 pinctrl_uart1_1: uart1grp-1 {
445 fsl,pins = <
446 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
447 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
448 >;
449 };
4bb6143c
SG		 450
451 pinctrl_uart1_2: uart1grp-2 {
452 fsl,pins = <
453 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
454 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
455 >;
456 };
5be03a7b 457 };
07248042
SG		 458
459 uart2 {
460 pinctrl_uart2_1: uart2grp-1 {
461 fsl,pins = <
462 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
463 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
464 >;
465 };
466 };
467
468 uart3 {
469 pinctrl_uart3_1: uart3grp-1 {
470 fsl,pins = <
471 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
472 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
473 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
474 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
475 >;
476 };
11ab21e9
ST		 477
478 pinctrl_uart3_2: uart3grp-2 {
479 fsl,pins = <
480 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
481 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
482 >;
483 };
484
07248042 485 };
a1fff236
RS		 486
487 uart4 {
488 pinctrl_uart4_1: uart4grp-1 {
489 fsl,pins = <
490 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
491 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
492 >;
493 };
494 };
495
496 uart5 {
497 pinctrl_uart5_1: uart5grp-1 {
498 fsl,pins = <
499 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
500 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
501 >;
502 };
503 };
504
5be03a7b
SG		 505 };
506
9ae90afa
SH		 507 pwm1: pwm@53fb4000 {
508 #pwm-cells = <2>;
509 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
510 reg = <0x53fb4000 0x4000>;
511 clocks = <&clks 37>, <&clks 38>;
512 clock-names = "ipg", "per";
513 interrupts = <61>;
514 };
515
516 pwm2: pwm@53fb8000 {
517 #pwm-cells = <2>;
518 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
519 reg = <0x53fb8000 0x4000>;
520 clocks = <&clks 39>, <&clks 40>;
521 clock-names = "ipg", "per";
522 interrupts = <94>;
523 };
524
0c456cfa 525 uart1: serial@53fbc000 {
73d2b4cd
SG		 526 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
527 reg = <0x53fbc000 0x4000>;
528 interrupts = <31>;
f40f38d1
FE		 529 clocks = <&clks 28>, <&clks 29>;
530 clock-names = "ipg", "per";
73d2b4cd
SG		 531 status = "disabled";
532 };
533
0c456cfa 534 uart2: serial@53fc0000 {
73d2b4cd
SG		 535 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
536 reg = <0x53fc0000 0x4000>;
537 interrupts = <32>;
f40f38d1
FE		 538 clocks = <&clks 30>, <&clks 31>;
539 clock-names = "ipg", "per";
73d2b4cd
SG		 540 status = "disabled";
541 };
542
a9d1f924
ST		 543 can1: can@53fc8000 {
544 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
545 reg = <0x53fc8000 0x4000>;
546 interrupts = <82>;
f40f38d1
FE		 547 clocks = <&clks 158>, <&clks 157>;
548 clock-names = "ipg", "per";
a9d1f924
ST		 549 status = "disabled";
550 };
551
552 can2: can@53fcc000 {
553 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
554 reg = <0x53fcc000 0x4000>;
555 interrupts = <83>;
e37f0d5b 556 clocks = <&clks 87>, <&clks 86>;
f40f38d1 557 clock-names = "ipg", "per";
a9d1f924
ST		 558 status = "disabled";
559 };
560
f40f38d1
FE		 561 clks: ccm@53fd4000{
562 compatible = "fsl,imx53-ccm";
563 reg = <0x53fd4000 0x4000>;
564 interrupts = <0 71 0x04 0 72 0x04>;
565 #clock-cells = <1>;
566 };
567
4d191868 568 gpio5: gpio@53fdc000 {
aeb27748 569 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 570 reg = <0x53fdc000 0x4000>;
571 interrupts = <103 104>;
572 gpio-controller;
573 #gpio-cells = <2>;
574 interrupt-controller;
88cde8b7 575 #interrupt-cells = <2>;
73d2b4cd
SG		 576 };
577
4d191868 578 gpio6: gpio@53fe0000 {
aeb27748 579 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 580 reg = <0x53fe0000 0x4000>;
581 interrupts = <105 106>;
582 gpio-controller;
583 #gpio-cells = <2>;
584 interrupt-controller;
88cde8b7 585 #interrupt-cells = <2>;
73d2b4cd
SG		 586 };
587
4d191868 588 gpio7: gpio@53fe4000 {
aeb27748 589 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 590 reg = <0x53fe4000 0x4000>;
591 interrupts = <107 108>;
592 gpio-controller;
593 #gpio-cells = <2>;
594 interrupt-controller;
88cde8b7 595 #interrupt-cells = <2>;
73d2b4cd
SG		 596 };
597
7b7d6727 598 i2c3: i2c@53fec000 {
73d2b4cd
SG		 599 #address-cells = <1>;
600 #size-cells = <0>;
5bdfba29 601 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 602 reg = <0x53fec000 0x4000>;
603 interrupts = <64>;
f40f38d1 604 clocks = <&clks 88>;
73d2b4cd
SG		 605 status = "disabled";
606 };
607
0c456cfa 608 uart4: serial@53ff0000 {
73d2b4cd
SG		 609 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
610 reg = <0x53ff0000 0x4000>;
611 interrupts = <13>;
f40f38d1
FE		 612 clocks = <&clks 65>, <&clks 66>;
613 clock-names = "ipg", "per";
73d2b4cd
SG		 614 status = "disabled";
615 };
616 };
617
618 aips@60000000 { /* AIPS2 */
619 compatible = "fsl,aips-bus", "simple-bus";
620 #address-cells = <1>;
621 #size-cells = <1>;
622 reg = <0x60000000 0x10000000>;
623 ranges;
624
0c456cfa 625 uart5: serial@63f90000 {
73d2b4cd
SG		 626 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
627 reg = <0x63f90000 0x4000>;
628 interrupts = <86>;
f40f38d1
FE		 629 clocks = <&clks 67>, <&clks 68>;
630 clock-names = "ipg", "per";
73d2b4cd
SG		 631 status = "disabled";
632 };
633
a82b7b9c
MF		 634 owire: owire@63fa4000 {
635 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
636 reg = <0x63fa4000 0x4000>;
637 clocks = <&clks 159>;
638 status = "disabled";
639 };
640
7b7d6727 641 ecspi2: ecspi@63fac000 {
73d2b4cd
SG		 642 #address-cells = <1>;
643 #size-cells = <0>;
644 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
645 reg = <0x63fac000 0x4000>;
646 interrupts = <37>;
f40f38d1
FE		 647 clocks = <&clks 53>, <&clks 54>;
648 clock-names = "ipg", "per";
73d2b4cd
SG		 649 status = "disabled";
650 };
651
7b7d6727 652 sdma: sdma@63fb0000 {
73d2b4cd
SG		 653 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
654 reg = <0x63fb0000 0x4000>;
655 interrupts = <6>;
f40f38d1
FE		 656 clocks = <&clks 56>, <&clks 56>;
657 clock-names = "ipg", "ahb";
7e4f0365 658 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd
SG		 659 };
660
7b7d6727 661 cspi: cspi@63fc0000 {
73d2b4cd
SG		 662 #address-cells = <1>;
663 #size-cells = <0>;
664 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
665 reg = <0x63fc0000 0x4000>;
666 interrupts = <38>;
f40f38d1
FE		 667 clocks = <&clks 55>, <&clks 0>;
668 clock-names = "ipg", "per";
73d2b4cd
SG		 669 status = "disabled";
670 };
671
7b7d6727 672 i2c2: i2c@63fc4000 {
73d2b4cd
SG		 673 #address-cells = <1>;
674 #size-cells = <0>;
5bdfba29 675 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 676 reg = <0x63fc4000 0x4000>;
677 interrupts = <63>;
f40f38d1 678 clocks = <&clks 35>;
73d2b4cd
SG		 679 status = "disabled";
680 };
681
7b7d6727 682 i2c1: i2c@63fc8000 {
73d2b4cd
SG		 683 #address-cells = <1>;
684 #size-cells = <0>;
5bdfba29 685 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 686 reg = <0x63fc8000 0x4000>;
687 interrupts = <62>;
f40f38d1 688 clocks = <&clks 34>;
73d2b4cd
SG		 689 status = "disabled";
690 };
691
ffc505c0
SG		 692 ssi1: ssi@63fcc000 {
693 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
694 reg = <0x63fcc000 0x4000>;
695 interrupts = <29>;
f40f38d1 696 clocks = <&clks 48>;
ffc505c0
SG		 697 fsl,fifo-depth = <15>;
698 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
699 status = "disabled";
700 };
701
7b7d6727 702 audmux: audmux@63fd0000 {
ffc505c0
SG		 703 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
704 reg = <0x63fd0000 0x4000>;
705 status = "disabled";
706 };
707
7b7d6727 708 nfc: nand@63fdb000 {
75453a08
SH		 709 compatible = "fsl,imx53-nand";
710 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
711 interrupts = <8>;
f40f38d1 712 clocks = <&clks 60>;
75453a08
SH		 713 status = "disabled";
714 };
715
ffc505c0
SG		 716 ssi3: ssi@63fe8000 {
717 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
718 reg = <0x63fe8000 0x4000>;
719 interrupts = <96>;
f40f38d1 720 clocks = <&clks 50>;
ffc505c0
SG		 721 fsl,fifo-depth = <15>;
722 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
723 status = "disabled";
724 };
725
7b7d6727 726 fec: ethernet@63fec000 {
73d2b4cd
SG		 727 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
728 reg = <0x63fec000 0x4000>;
729 interrupts = <87>;
f40f38d1
FE		 730 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
731 clock-names = "ipg", "ahb", "ptp";
73d2b4cd
SG		 732 status = "disabled";
733 };
734 };
735 };
736};
Linux kernel - Deliverables
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