[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc@50004000 { /* ESDHC1 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					status = "disabled";
				};

				esdhc@50008000 { /* ESDHC2 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx53-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					status = "disabled";
				};

				ecspi@50010000 { /* ECSPI1 */
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc@50020000 { /* ESDHC3 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					status = "disabled";
				};

				esdhc@50024000 { /* ESDHC4 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					status = "disabled";
				};
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog@53f98000 { /* WDOG1 */
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
			};

			wdog@53f9c000 { /* WDOG2 */
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f9c000 0x4000>;
				interrupts = <59>;
				status = "disabled";
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				status = "disabled";
			};

			can1: can@53fc8000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fc8000 0x4000>;
				interrupts = <82>;
				status = "disabled";
			};

			can2: can@53fcc000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fcc000 0x4000>;
				interrupts = <83>;
				status = "disabled";
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio7: gpio@53fe4000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe4000 0x4000>;
				interrupts = <107 108>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c@53fec000 { /* I2C3 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				status = "disabled";
			};

			ecspi@63fac000 { /* ECSPI2 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				status = "disabled";
			};

			sdma@63fb0000 {
				compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
			};

			cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				status = "disabled";
			};

			i2c@63fc4000 { /* I2C2 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				status = "disabled";
			};

			i2c@63fc8000 { /* I2C1 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux@63fd0000 {
				compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			ssi3: ssi@63fe8000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fe8000 0x4000>;
				interrupts = <96>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
73d2b4cd SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/include/ "skeleton.dtsi"
	14
	15	/ {
	16	aliases {
8f9ffecf RZ	17	serial0 = &uart1;
	18	serial1 = &uart2;
	19	serial2 = &uart3;
	20	serial3 = &uart4;
	21	serial4 = &uart5;
5230f8fe SG	22	gpio0 = &gpio1;
	23	gpio1 = &gpio2;
	24	gpio2 = &gpio3;
	25	gpio3 = &gpio4;
	26	gpio4 = &gpio5;
	27	gpio5 = &gpio6;
	28	gpio6 = &gpio7;
73d2b4cd SG	29	};
	30
	31	tzic: tz-interrupt-controller@0fffc000 {
	32	compatible = "fsl,imx53-tzic", "fsl,tzic";
	33	interrupt-controller;
	34	#interrupt-cells = <1>;
	35	reg = <0x0fffc000 0x4000>;
	36	};
	37
	38	clocks {
	39	#address-cells = <1>;
	40	#size-cells = <0>;
	41
	42	ckil {
	43	compatible = "fsl,imx-ckil", "fixed-clock";
	44	clock-frequency = <32768>;
	45	};
	46
	47	ckih1 {
	48	compatible = "fsl,imx-ckih1", "fixed-clock";
	49	clock-frequency = <22579200>;
	50	};
	51
	52	ckih2 {
	53	compatible = "fsl,imx-ckih2", "fixed-clock";
	54	clock-frequency = <0>;
	55	};
	56
	57	osc {
	58	compatible = "fsl,imx-osc", "fixed-clock";
	59	clock-frequency = <24000000>;
	60	};
	61	};
	62
	63	soc {
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	compatible = "simple-bus";
	67	interrupt-parent = <&tzic>;
	68	ranges;
	69
	70	aips@50000000 { /* AIPS1 */
	71	compatible = "fsl,aips-bus", "simple-bus";
	72	#address-cells = <1>;
	73	#size-cells = <1>;
	74	reg = <0x50000000 0x10000000>;
	75	ranges;
	76
	77	spba@50000000 {
	78	compatible = "fsl,spba-bus", "simple-bus";
	79	#address-cells = <1>;
	80	#size-cells = <1>;
	81	reg = <0x50000000 0x40000>;
	82	ranges;
	83
	84	esdhc@50004000 { /* ESDHC1 */
	85	compatible = "fsl,imx53-esdhc";
	86	reg = <0x50004000 0x4000>;
	87	interrupts = <1>;
	88	status = "disabled";
	89	};
	90
	91	esdhc@50008000 { /* ESDHC2 */
	92	compatible = "fsl,imx53-esdhc";
93	reg = <0x50008000 0x4000>;
94	interrupts = <2>;
95	status = "disabled";
96	};
97
0c456cfa	98	uart3: serial@5000c000 {
73d2b4cd SG	99	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	100	reg = <0x5000c000 0x4000>;
	101	interrupts = <33>;
	102	status = "disabled";
	103	};
	104
	105	ecspi@50010000 { /* ECSPI1 */
	106	#address-cells = <1>;
	107	#size-cells = <0>;
	108	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	109	reg = <0x50010000 0x4000>;
	110	interrupts = <36>;
	111	status = "disabled";
	112	};
	113
ffc505c0 SG	114	ssi2: ssi@50014000 {
	115	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	116	reg = <0x50014000 0x4000>;
	117	interrupts = <30>;
	118	fsl,fifo-depth = <15>;
	119	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	120	status = "disabled";
	121	};
	122
73d2b4cd SG	123	esdhc@50020000 { /* ESDHC3 */
	124	compatible = "fsl,imx53-esdhc";
	125	reg = <0x50020000 0x4000>;
	126	interrupts = <3>;
	127	status = "disabled";
	128	};
	129
	130	esdhc@50024000 { /* ESDHC4 */
	131	compatible = "fsl,imx53-esdhc";
	132	reg = <0x50024000 0x4000>;
	133	interrupts = <4>;
	134	status = "disabled";
	135	};
	136	};
	137
4d191868	138	gpio1: gpio@53f84000 {
aeb27748	139	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	140	reg = <0x53f84000 0x4000>;
	141	interrupts = <50 51>;
	142	gpio-controller;
	143	#gpio-cells = <2>;
	144	interrupt-controller;
88cde8b7	145	#interrupt-cells = <2>;
73d2b4cd SG	146	};
73d2b4cd SG	147
4d191868	148	gpio2: gpio@53f88000 {
aeb27748	149	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	150	reg = <0x53f88000 0x4000>;
	151	interrupts = <52 53>;
	152	gpio-controller;
	153	#gpio-cells = <2>;
	154	interrupt-controller;
88cde8b7	155	#interrupt-cells = <2>;
73d2b4cd SG	156	};
73d2b4cd SG	157
4d191868	158	gpio3: gpio@53f8c000 {
aeb27748	159	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	160	reg = <0x53f8c000 0x4000>;
	161	interrupts = <54 55>;
	162	gpio-controller;
	163	#gpio-cells = <2>;
	164	interrupt-controller;
88cde8b7	165	#interrupt-cells = <2>;
73d2b4cd SG	166	};
73d2b4cd SG	167
4d191868	168	gpio4: gpio@53f90000 {
aeb27748	169	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	170	reg = <0x53f90000 0x4000>;
	171	interrupts = <56 57>;
	172	gpio-controller;
	173	#gpio-cells = <2>;
	174	interrupt-controller;
88cde8b7	175	#interrupt-cells = <2>;
73d2b4cd SG	176	};
	177
	178	wdog@53f98000 { /* WDOG1 */
	179	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	180	reg = <0x53f98000 0x4000>;
	181	interrupts = <58>;
73d2b4cd SG	182	};
	183
	184	wdog@53f9c000 { /* WDOG2 */
	185	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	186	reg = <0x53f9c000 0x4000>;
	187	interrupts = <59>;
	188	status = "disabled";
	189	};
	190
0c456cfa	191	uart1: serial@53fbc000 {
73d2b4cd SG	192	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	193	reg = <0x53fbc000 0x4000>;
	194	interrupts = <31>;
	195	status = "disabled";
	196	};
	197
0c456cfa	198	uart2: serial@53fc0000 {
73d2b4cd SG	199	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	200	reg = <0x53fc0000 0x4000>;
	201	interrupts = <32>;
	202	status = "disabled";
	203	};
	204
a9d1f924 ST	205	can1: can@53fc8000 {
	206	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	207	reg = <0x53fc8000 0x4000>;
	208	interrupts = <82>;
	209	status = "disabled";
	210	};
	211
	212	can2: can@53fcc000 {
	213	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	214	reg = <0x53fcc000 0x4000>;
	215	interrupts = <83>;
	216	status = "disabled";
	217	};
	218
4d191868	219	gpio5: gpio@53fdc000 {
aeb27748	220	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	221	reg = <0x53fdc000 0x4000>;
	222	interrupts = <103 104>;
	223	gpio-controller;
	224	#gpio-cells = <2>;
	225	interrupt-controller;
88cde8b7	226	#interrupt-cells = <2>;
73d2b4cd SG	227	};
73d2b4cd SG	228
4d191868	229	gpio6: gpio@53fe0000 {
aeb27748	230	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	231	reg = <0x53fe0000 0x4000>;
	232	interrupts = <105 106>;
	233	gpio-controller;
	234	#gpio-cells = <2>;
	235	interrupt-controller;
88cde8b7	236	#interrupt-cells = <2>;
73d2b4cd SG	237	};
73d2b4cd SG	238
4d191868	239	gpio7: gpio@53fe4000 {
aeb27748	240	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	241	reg = <0x53fe4000 0x4000>;
	242	interrupts = <107 108>;
	243	gpio-controller;
	244	#gpio-cells = <2>;
	245	interrupt-controller;
88cde8b7	246	#interrupt-cells = <2>;
73d2b4cd SG	247	};
	248
	249	i2c@53fec000 { /* I2C3 */
	250	#address-cells = <1>;
	251	#size-cells = <0>;
	252	compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
	253	reg = <0x53fec000 0x4000>;
	254	interrupts = <64>;
	255	status = "disabled";
	256	};
	257
0c456cfa	258	uart4: serial@53ff0000 {
73d2b4cd SG	259	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	260	reg = <0x53ff0000 0x4000>;
	261	interrupts = <13>;
	262	status = "disabled";
	263	};
	264	};
	265
	266	aips@60000000 { /* AIPS2 */
	267	compatible = "fsl,aips-bus", "simple-bus";
	268	#address-cells = <1>;
	269	#size-cells = <1>;
	270	reg = <0x60000000 0x10000000>;
	271	ranges;
	272
0c456cfa	273	uart5: serial@63f90000 {
73d2b4cd SG	274	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	275	reg = <0x63f90000 0x4000>;
	276	interrupts = <86>;
	277	status = "disabled";
	278	};
	279
	280	ecspi@63fac000 { /* ECSPI2 */
	281	#address-cells = <1>;
	282	#size-cells = <0>;
	283	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	284	reg = <0x63fac000 0x4000>;
	285	interrupts = <37>;
	286	status = "disabled";
	287	};
	288
	289	sdma@63fb0000 {
	290	compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
	291	reg = <0x63fb0000 0x4000>;
	292	interrupts = <6>;
	293	};
	294
	295	cspi@63fc0000 {
	296	#address-cells = <1>;
	297	#size-cells = <0>;
	298	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
	299	reg = <0x63fc0000 0x4000>;
	300	interrupts = <38>;
	301	status = "disabled";
	302	};
	303
	304	i2c@63fc4000 { /* I2C2 */
	305	#address-cells = <1>;
	306	#size-cells = <0>;
	307	compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
	308	reg = <0x63fc4000 0x4000>;
	309	interrupts = <63>;
	310	status = "disabled";
	311	};
	312
	313	i2c@63fc8000 { /* I2C1 */
	314	#address-cells = <1>;
	315	#size-cells = <0>;
	316	compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
	317	reg = <0x63fc8000 0x4000>;
	318	interrupts = <62>;
	319	status = "disabled";
	320	};
	321
ffc505c0 SG	322	ssi1: ssi@63fcc000 {
	323	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	324	reg = <0x63fcc000 0x4000>;
	325	interrupts = <29>;
	326	fsl,fifo-depth = <15>;
	327	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	328	status = "disabled";
	329	};
	330
	331	audmux@63fd0000 {
	332	compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
	333	reg = <0x63fd0000 0x4000>;
	334	status = "disabled";
	335	};
	336
	337	ssi3: ssi@63fe8000 {
	338	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	339	reg = <0x63fe8000 0x4000>;
	340	interrupts = <96>;
	341	fsl,fifo-depth = <15>;
	342	fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
	343	status = "disabled";
	344	};
	345
0c456cfa	346	ethernet@63fec000 {
73d2b4cd SG	347	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	348	reg = <0x63fec000 0x4000>;
	349	interrupts = <87>;
	350	status = "disabled";
	351	};
	352	};
	353	};
	354	};