[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc@50004000 { /* ESDHC1 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					status = "disabled";
				};

				esdhc@50008000 { /* ESDHC2 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx53-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					status = "disabled";
				};

				ecspi@50010000 { /* ECSPI1 */
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc@50020000 { /* ESDHC3 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					status = "disabled";
				};

				esdhc@50024000 { /* ESDHC4 */
					compatible = "fsl,imx53-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					status = "disabled";
				};
			};

			usb@53f80000 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				status = "disabled";
			};

			usb@53f80200 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				status = "disabled";
			};

			usb@53f80400 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				status = "disabled";
			};

			usb@53f80600 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				status = "disabled";
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog@53f98000 { /* WDOG1 */
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
			};

			wdog@53f9c000 { /* WDOG2 */
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f9c000 0x4000>;
				interrupts = <59>;
				status = "disabled";
			};

			iomuxc@53fa8000 {
				compatible = "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;

				audmux {
					pinctrl_audmux_1: audmuxgrp-1 {
						fsl,pins = <
							10 0x80000000	/* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
							17 0x80000000	/* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
							23 0x80000000	/* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
							30 0x80000000	/* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
						>;
					};
				};

				fec {
					pinctrl_fec_1: fecgrp-1 {
						fsl,pins = <
							820 0x80000000	/* MX53_PAD_FEC_MDC__FEC_MDC */
							779 0x80000000	/* MX53_PAD_FEC_MDIO__FEC_MDIO */
							786 0x80000000	/* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
							791 0x80000000	/* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
							796 0x80000000	/* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
							799 0x80000000	/* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
							804 0x80000000	/* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
							808 0x80000000	/* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
							811 0x80000000	/* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
							816 0x80000000	/* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
						>;
					};
				};

				esdhc1 {
					pinctrl_esdhc1_1: esdhc1grp-1 {
						fsl,pins = <
							995  0x1d5	/* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
							1000 0x1d5	/* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
							1010 0x1d5	/* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
							1024 0x1d5	/* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
							1005 0x1d5	/* MX53_PAD_SD1_CMD__ESDHC1_CMD */
							1018 0x1d5	/* MX53_PAD_SD1_CLK__ESDHC1_CLK */
						>;
					};
				};

				esdhc3 {
					pinctrl_esdhc3_1: esdhc3grp-1 {
						fsl,pins = <
							943 0x1d5	/* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
							950 0x1d5	/* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
							957 0x1d5	/* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
							964 0x1d5	/* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
							893 0x1d5	/* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
							900 0x1d5	/* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
							906 0x1d5	/* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
							912 0x1d5	/* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
							857 0x1d5	/* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
							863 0x1d5	/* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
						>;
					};
				};

				i2c1 {
					pinctrl_i2c1_1: i2c1grp-1 {
						fsl,pins = <
							333 0xc0000000	/* MX53_PAD_CSI0_DAT8__I2C1_SDA */
							341 0xc0000000	/* MX53_PAD_CSI0_DAT9__I2C1_SCL */
						>;
					};
				};

				i2c2 {
					pinctrl_i2c2_1: i2c2grp-1 {
						fsl,pins = <
							61 0xc0000000	/* MX53_PAD_KEY_ROW3__I2C2_SDA */
							53 0xc0000000	/* MX53_PAD_KEY_COL3__I2C2_SCL */
						>;
					};
				};

				uart1 {
					pinctrl_uart1_1: uart1grp-1 {
						fsl,pins = <
							346 0x1c5	/* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
							354 0x1c5	/* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
						>;
					};
				};
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				status = "disabled";
			};

			can1: can@53fc8000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fc8000 0x4000>;
				interrupts = <82>;
				status = "disabled";
			};

			can2: can@53fcc000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fcc000 0x4000>;
				interrupts = <83>;
				status = "disabled";
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio7: gpio@53fe4000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe4000 0x4000>;
				interrupts = <107 108>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c@53fec000 { /* I2C3 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				status = "disabled";
			};

			ecspi@63fac000 { /* ECSPI2 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				status = "disabled";
			};

			sdma@63fb0000 {
				compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
			};

			cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				status = "disabled";
			};

			i2c@63fc4000 { /* I2C2 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				status = "disabled";
			};

			i2c@63fc8000 { /* I2C1 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux@63fd0000 {
				compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			ssi3: ssi@63fe8000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fe8000 0x4000>;
				interrupts = <96>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
73d2b4cd SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/include/ "skeleton.dtsi"
	14
	15	/ {
	16	aliases {
8f9ffecf RZ	17	serial0 = &uart1;
	18	serial1 = &uart2;
	19	serial2 = &uart3;
	20	serial3 = &uart4;
	21	serial4 = &uart5;
5230f8fe SG	22	gpio0 = &gpio1;
	23	gpio1 = &gpio2;
	24	gpio2 = &gpio3;
	25	gpio3 = &gpio4;
	26	gpio4 = &gpio5;
	27	gpio5 = &gpio6;
	28	gpio6 = &gpio7;
73d2b4cd SG	29	};
	30
	31	tzic: tz-interrupt-controller@0fffc000 {
	32	compatible = "fsl,imx53-tzic", "fsl,tzic";
	33	interrupt-controller;
	34	#interrupt-cells = <1>;
	35	reg = <0x0fffc000 0x4000>;
	36	};
	37
	38	clocks {
	39	#address-cells = <1>;
	40	#size-cells = <0>;
	41
	42	ckil {
	43	compatible = "fsl,imx-ckil", "fixed-clock";
	44	clock-frequency = <32768>;
	45	};
	46
	47	ckih1 {
	48	compatible = "fsl,imx-ckih1", "fixed-clock";
	49	clock-frequency = <22579200>;
	50	};
	51
	52	ckih2 {
	53	compatible = "fsl,imx-ckih2", "fixed-clock";
	54	clock-frequency = <0>;
	55	};
	56
	57	osc {
	58	compatible = "fsl,imx-osc", "fixed-clock";
	59	clock-frequency = <24000000>;
	60	};
	61	};
	62
	63	soc {
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	compatible = "simple-bus";
	67	interrupt-parent = <&tzic>;
	68	ranges;
	69
	70	aips@50000000 { /* AIPS1 */
	71	compatible = "fsl,aips-bus", "simple-bus";
	72	#address-cells = <1>;
	73	#size-cells = <1>;
	74	reg = <0x50000000 0x10000000>;
	75	ranges;
	76
	77	spba@50000000 {
	78	compatible = "fsl,spba-bus", "simple-bus";
	79	#address-cells = <1>;
	80	#size-cells = <1>;
	81	reg = <0x50000000 0x40000>;
	82	ranges;
	83
	84	esdhc@50004000 { /* ESDHC1 */
	85	compatible = "fsl,imx53-esdhc";
	86	reg = <0x50004000 0x4000>;
	87	interrupts = <1>;
	88	status = "disabled";
	89	};
	90
	91	esdhc@50008000 { /* ESDHC2 */
	92	compatible = "fsl,imx53-esdhc";
93	reg = <0x50008000 0x4000>;
94	interrupts = <2>;
95	status = "disabled";
96	};
97
0c456cfa	98	uart3: serial@5000c000 {
73d2b4cd SG	99	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	100	reg = <0x5000c000 0x4000>;
	101	interrupts = <33>;
	102	status = "disabled";
	103	};
	104
	105	ecspi@50010000 { /* ECSPI1 */
	106	#address-cells = <1>;
	107	#size-cells = <0>;
	108	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	109	reg = <0x50010000 0x4000>;
	110	interrupts = <36>;
	111	status = "disabled";
	112	};
	113
ffc505c0 SG	114	ssi2: ssi@50014000 {
	115	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	116	reg = <0x50014000 0x4000>;
	117	interrupts = <30>;
	118	fsl,fifo-depth = <15>;
	119	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	120	status = "disabled";
	121	};
	122
73d2b4cd SG	123	esdhc@50020000 { /* ESDHC3 */
	124	compatible = "fsl,imx53-esdhc";
	125	reg = <0x50020000 0x4000>;
	126	interrupts = <3>;
	127	status = "disabled";
	128	};
	129
	130	esdhc@50024000 { /* ESDHC4 */
	131	compatible = "fsl,imx53-esdhc";
	132	reg = <0x50024000 0x4000>;
	133	interrupts = <4>;
	134	status = "disabled";
	135	};
	136	};
	137
212d0b83 MG	138	usb@53f80000 {
	139	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	140	reg = <0x53f80000 0x0200>;
	141	interrupts = <18>;
	142	status = "disabled";
	143	};
	144
	145	usb@53f80200 {
	146	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	147	reg = <0x53f80200 0x0200>;
	148	interrupts = <14>;
	149	status = "disabled";
	150	};
	151
	152	usb@53f80400 {
	153	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	154	reg = <0x53f80400 0x0200>;
	155	interrupts = <16>;
	156	status = "disabled";
	157	};
	158
	159	usb@53f80600 {
	160	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	161	reg = <0x53f80600 0x0200>;
	162	interrupts = <17>;
	163	status = "disabled";
	164	};
	165
4d191868	166	gpio1: gpio@53f84000 {
aeb27748	167	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	168	reg = <0x53f84000 0x4000>;
	169	interrupts = <50 51>;
	170	gpio-controller;
	171	#gpio-cells = <2>;
	172	interrupt-controller;
88cde8b7	173	#interrupt-cells = <2>;
73d2b4cd SG	174	};
73d2b4cd SG	175
4d191868	176	gpio2: gpio@53f88000 {
aeb27748	177	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	178	reg = <0x53f88000 0x4000>;
	179	interrupts = <52 53>;
	180	gpio-controller;
	181	#gpio-cells = <2>;
	182	interrupt-controller;
88cde8b7	183	#interrupt-cells = <2>;
73d2b4cd SG	184	};
73d2b4cd SG	185
4d191868	186	gpio3: gpio@53f8c000 {
aeb27748	187	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	188	reg = <0x53f8c000 0x4000>;
	189	interrupts = <54 55>;
	190	gpio-controller;
	191	#gpio-cells = <2>;
	192	interrupt-controller;
88cde8b7	193	#interrupt-cells = <2>;
73d2b4cd SG	194	};
73d2b4cd SG	195
4d191868	196	gpio4: gpio@53f90000 {
aeb27748	197	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	198	reg = <0x53f90000 0x4000>;
	199	interrupts = <56 57>;
	200	gpio-controller;
	201	#gpio-cells = <2>;
	202	interrupt-controller;
88cde8b7	203	#interrupt-cells = <2>;
73d2b4cd SG	204	};
	205
	206	wdog@53f98000 { /* WDOG1 */
	207	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	208	reg = <0x53f98000 0x4000>;
	209	interrupts = <58>;
73d2b4cd SG	210	};
	211
	212	wdog@53f9c000 { /* WDOG2 */
	213	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	214	reg = <0x53f9c000 0x4000>;
	215	interrupts = <59>;
	216	status = "disabled";
	217	};
	218
5be03a7b SG	219	iomuxc@53fa8000 {
	220	compatible = "fsl,imx53-iomuxc";
	221	reg = <0x53fa8000 0x4000>;
	222
	223	audmux {
	224	pinctrl_audmux_1: audmuxgrp-1 {
	225	fsl,pins = <
	226	10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
	227	17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
	228	23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
	229	30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
	230	>;
	231	};
	232	};
	233
	234	fec {
	235	pinctrl_fec_1: fecgrp-1 {
	236	fsl,pins = <
	237	820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
	238	779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
	239	786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
	240	791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
	241	796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
	242	799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
	243	804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
	244	808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
	245	811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
	246	816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
	247	>;
	248	};
	249	};
	250
	251	esdhc1 {
	252	pinctrl_esdhc1_1: esdhc1grp-1 {
	253	fsl,pins = <
	254	995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
	255	1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
	256	1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
	257	1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
	258	1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
	259	1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
	260	>;
	261	};
	262	};
	263
	264	esdhc3 {
	265	pinctrl_esdhc3_1: esdhc3grp-1 {
	266	fsl,pins = <
	267	943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
	268	950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
	269	957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
	270	964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
	271	893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
	272	900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
	273	906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
	274	912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
	275	857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
	276	863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
	277	>;
	278	};
	279	};
	280
	281	i2c1 {
	282	pinctrl_i2c1_1: i2c1grp-1 {
283	fsl,pins = <
284	333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
285	341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
286	>;
287	};
288	};
289
290	i2c2 {
291	pinctrl_i2c2_1: i2c2grp-1 {
292	fsl,pins = <
293	61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
294	53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
295	>;
296	};
297	};
298
299	uart1 {
300	pinctrl_uart1_1: uart1grp-1 {
301	fsl,pins = <
302	346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
303	354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
304	>;
305	};
306	};
307	};
308
0c456cfa	309	uart1: serial@53fbc000 {
73d2b4cd SG	310	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	311	reg = <0x53fbc000 0x4000>;
	312	interrupts = <31>;
	313	status = "disabled";
	314	};
	315
0c456cfa	316	uart2: serial@53fc0000 {
73d2b4cd SG	317	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	318	reg = <0x53fc0000 0x4000>;
	319	interrupts = <32>;
	320	status = "disabled";
	321	};
	322
a9d1f924 ST	323	can1: can@53fc8000 {
	324	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	325	reg = <0x53fc8000 0x4000>;
	326	interrupts = <82>;
	327	status = "disabled";
	328	};
	329
	330	can2: can@53fcc000 {
	331	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	332	reg = <0x53fcc000 0x4000>;
	333	interrupts = <83>;
	334	status = "disabled";
	335	};
	336
4d191868	337	gpio5: gpio@53fdc000 {
aeb27748	338	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	339	reg = <0x53fdc000 0x4000>;
	340	interrupts = <103 104>;
	341	gpio-controller;
	342	#gpio-cells = <2>;
	343	interrupt-controller;
88cde8b7	344	#interrupt-cells = <2>;
73d2b4cd SG	345	};
73d2b4cd SG	346
4d191868	347	gpio6: gpio@53fe0000 {
aeb27748	348	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	349	reg = <0x53fe0000 0x4000>;
	350	interrupts = <105 106>;
	351	gpio-controller;
	352	#gpio-cells = <2>;
	353	interrupt-controller;
88cde8b7	354	#interrupt-cells = <2>;
73d2b4cd SG	355	};
73d2b4cd SG	356
4d191868	357	gpio7: gpio@53fe4000 {
aeb27748	358	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	359	reg = <0x53fe4000 0x4000>;
	360	interrupts = <107 108>;
	361	gpio-controller;
	362	#gpio-cells = <2>;
	363	interrupt-controller;
88cde8b7	364	#interrupt-cells = <2>;
73d2b4cd SG	365	};
	366
	367	i2c@53fec000 { /* I2C3 */
	368	#address-cells = <1>;
	369	#size-cells = <0>;
	370	compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
	371	reg = <0x53fec000 0x4000>;
	372	interrupts = <64>;
	373	status = "disabled";
	374	};
	375
0c456cfa	376	uart4: serial@53ff0000 {
73d2b4cd SG	377	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	378	reg = <0x53ff0000 0x4000>;
	379	interrupts = <13>;
	380	status = "disabled";
	381	};
	382	};
	383
	384	aips@60000000 { /* AIPS2 */
	385	compatible = "fsl,aips-bus", "simple-bus";
	386	#address-cells = <1>;
	387	#size-cells = <1>;
	388	reg = <0x60000000 0x10000000>;
	389	ranges;
	390
0c456cfa	391	uart5: serial@63f90000 {
73d2b4cd SG	392	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	393	reg = <0x63f90000 0x4000>;
	394	interrupts = <86>;
	395	status = "disabled";
	396	};
	397
	398	ecspi@63fac000 { /* ECSPI2 */
	399	#address-cells = <1>;
	400	#size-cells = <0>;
	401	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	402	reg = <0x63fac000 0x4000>;
	403	interrupts = <37>;
	404	status = "disabled";
	405	};
	406
	407	sdma@63fb0000 {
	408	compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
	409	reg = <0x63fb0000 0x4000>;
	410	interrupts = <6>;
7e4f0365	411	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd SG	412	};
	413
	414	cspi@63fc0000 {
	415	#address-cells = <1>;
	416	#size-cells = <0>;
	417	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
	418	reg = <0x63fc0000 0x4000>;
	419	interrupts = <38>;
	420	status = "disabled";
	421	};
	422
	423	i2c@63fc4000 { /* I2C2 */
	424	#address-cells = <1>;
	425	#size-cells = <0>;
	426	compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
	427	reg = <0x63fc4000 0x4000>;
	428	interrupts = <63>;
	429	status = "disabled";
	430	};
	431
	432	i2c@63fc8000 { /* I2C1 */
	433	#address-cells = <1>;
	434	#size-cells = <0>;
	435	compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
	436	reg = <0x63fc8000 0x4000>;
	437	interrupts = <62>;
	438	status = "disabled";
	439	};
	440
ffc505c0 SG	441	ssi1: ssi@63fcc000 {
	442	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	443	reg = <0x63fcc000 0x4000>;
	444	interrupts = <29>;
	445	fsl,fifo-depth = <15>;
	446	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	447	status = "disabled";
	448	};
	449
	450	audmux@63fd0000 {
	451	compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
	452	reg = <0x63fd0000 0x4000>;
	453	status = "disabled";
	454	};
	455
	456	ssi3: ssi@63fe8000 {
	457	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	458	reg = <0x63fe8000 0x4000>;
	459	interrupts = <96>;
	460	fsl,fifo-depth = <15>;
	461	fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
	462	status = "disabled";
	463	};
	464
0c456cfa	465	ethernet@63fec000 {
73d2b4cd SG	466	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	467	reg = <0x63fec000 0x4000>;
	468	interrupts = <87>;
	469	status = "disabled";
	470	};
	471	};
	472	};
	473	};