Commit | Line | Data |
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73d2b4cd SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /include/ "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
8f9ffecf RZ |
17 | serial0 = &uart1; |
18 | serial1 = &uart2; | |
19 | serial2 = &uart3; | |
20 | serial3 = &uart4; | |
21 | serial4 = &uart5; | |
5230f8fe SG |
22 | gpio0 = &gpio1; |
23 | gpio1 = &gpio2; | |
24 | gpio2 = &gpio3; | |
25 | gpio3 = &gpio4; | |
26 | gpio4 = &gpio5; | |
27 | gpio5 = &gpio6; | |
28 | gpio6 = &gpio7; | |
73d2b4cd SG |
29 | }; |
30 | ||
31 | tzic: tz-interrupt-controller@0fffc000 { | |
32 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
33 | interrupt-controller; | |
34 | #interrupt-cells = <1>; | |
35 | reg = <0x0fffc000 0x4000>; | |
36 | }; | |
37 | ||
38 | clocks { | |
39 | #address-cells = <1>; | |
40 | #size-cells = <0>; | |
41 | ||
42 | ckil { | |
43 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
44 | clock-frequency = <32768>; | |
45 | }; | |
46 | ||
47 | ckih1 { | |
48 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
49 | clock-frequency = <22579200>; | |
50 | }; | |
51 | ||
52 | ckih2 { | |
53 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
54 | clock-frequency = <0>; | |
55 | }; | |
56 | ||
57 | osc { | |
58 | compatible = "fsl,imx-osc", "fixed-clock"; | |
59 | clock-frequency = <24000000>; | |
60 | }; | |
61 | }; | |
62 | ||
63 | soc { | |
64 | #address-cells = <1>; | |
65 | #size-cells = <1>; | |
66 | compatible = "simple-bus"; | |
67 | interrupt-parent = <&tzic>; | |
68 | ranges; | |
69 | ||
abed9a6b SH |
70 | ipu: ipu@18000000 { |
71 | #crtc-cells = <1>; | |
72 | compatible = "fsl,imx53-ipu"; | |
73 | reg = <0x18000000 0x080000000>; | |
74 | interrupts = <11 10>; | |
75 | }; | |
76 | ||
73d2b4cd SG |
77 | aips@50000000 { /* AIPS1 */ |
78 | compatible = "fsl,aips-bus", "simple-bus"; | |
79 | #address-cells = <1>; | |
80 | #size-cells = <1>; | |
81 | reg = <0x50000000 0x10000000>; | |
82 | ranges; | |
83 | ||
84 | spba@50000000 { | |
85 | compatible = "fsl,spba-bus", "simple-bus"; | |
86 | #address-cells = <1>; | |
87 | #size-cells = <1>; | |
88 | reg = <0x50000000 0x40000>; | |
89 | ranges; | |
90 | ||
91 | esdhc@50004000 { /* ESDHC1 */ | |
92 | compatible = "fsl,imx53-esdhc"; | |
93 | reg = <0x50004000 0x4000>; | |
94 | interrupts = <1>; | |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
98 | esdhc@50008000 { /* ESDHC2 */ | |
99 | compatible = "fsl,imx53-esdhc"; | |
100 | reg = <0x50008000 0x4000>; | |
101 | interrupts = <2>; | |
102 | status = "disabled"; | |
103 | }; | |
104 | ||
0c456cfa | 105 | uart3: serial@5000c000 { |
73d2b4cd SG |
106 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
107 | reg = <0x5000c000 0x4000>; | |
108 | interrupts = <33>; | |
109 | status = "disabled"; | |
110 | }; | |
111 | ||
112 | ecspi@50010000 { /* ECSPI1 */ | |
113 | #address-cells = <1>; | |
114 | #size-cells = <0>; | |
115 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
116 | reg = <0x50010000 0x4000>; | |
117 | interrupts = <36>; | |
118 | status = "disabled"; | |
119 | }; | |
120 | ||
ffc505c0 SG |
121 | ssi2: ssi@50014000 { |
122 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
123 | reg = <0x50014000 0x4000>; | |
124 | interrupts = <30>; | |
125 | fsl,fifo-depth = <15>; | |
126 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
127 | status = "disabled"; | |
128 | }; | |
129 | ||
73d2b4cd SG |
130 | esdhc@50020000 { /* ESDHC3 */ |
131 | compatible = "fsl,imx53-esdhc"; | |
132 | reg = <0x50020000 0x4000>; | |
133 | interrupts = <3>; | |
134 | status = "disabled"; | |
135 | }; | |
136 | ||
137 | esdhc@50024000 { /* ESDHC4 */ | |
138 | compatible = "fsl,imx53-esdhc"; | |
139 | reg = <0x50024000 0x4000>; | |
140 | interrupts = <4>; | |
141 | status = "disabled"; | |
142 | }; | |
143 | }; | |
144 | ||
212d0b83 MG |
145 | usb@53f80000 { |
146 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | |
147 | reg = <0x53f80000 0x0200>; | |
148 | interrupts = <18>; | |
149 | status = "disabled"; | |
150 | }; | |
151 | ||
152 | usb@53f80200 { | |
153 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | |
154 | reg = <0x53f80200 0x0200>; | |
155 | interrupts = <14>; | |
156 | status = "disabled"; | |
157 | }; | |
158 | ||
159 | usb@53f80400 { | |
160 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | |
161 | reg = <0x53f80400 0x0200>; | |
162 | interrupts = <16>; | |
163 | status = "disabled"; | |
164 | }; | |
165 | ||
166 | usb@53f80600 { | |
167 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | |
168 | reg = <0x53f80600 0x0200>; | |
169 | interrupts = <17>; | |
170 | status = "disabled"; | |
171 | }; | |
172 | ||
4d191868 | 173 | gpio1: gpio@53f84000 { |
aeb27748 | 174 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
175 | reg = <0x53f84000 0x4000>; |
176 | interrupts = <50 51>; | |
177 | gpio-controller; | |
178 | #gpio-cells = <2>; | |
179 | interrupt-controller; | |
88cde8b7 | 180 | #interrupt-cells = <2>; |
73d2b4cd SG |
181 | }; |
182 | ||
4d191868 | 183 | gpio2: gpio@53f88000 { |
aeb27748 | 184 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
185 | reg = <0x53f88000 0x4000>; |
186 | interrupts = <52 53>; | |
187 | gpio-controller; | |
188 | #gpio-cells = <2>; | |
189 | interrupt-controller; | |
88cde8b7 | 190 | #interrupt-cells = <2>; |
73d2b4cd SG |
191 | }; |
192 | ||
4d191868 | 193 | gpio3: gpio@53f8c000 { |
aeb27748 | 194 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
195 | reg = <0x53f8c000 0x4000>; |
196 | interrupts = <54 55>; | |
197 | gpio-controller; | |
198 | #gpio-cells = <2>; | |
199 | interrupt-controller; | |
88cde8b7 | 200 | #interrupt-cells = <2>; |
73d2b4cd SG |
201 | }; |
202 | ||
4d191868 | 203 | gpio4: gpio@53f90000 { |
aeb27748 | 204 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
205 | reg = <0x53f90000 0x4000>; |
206 | interrupts = <56 57>; | |
207 | gpio-controller; | |
208 | #gpio-cells = <2>; | |
209 | interrupt-controller; | |
88cde8b7 | 210 | #interrupt-cells = <2>; |
73d2b4cd SG |
211 | }; |
212 | ||
213 | wdog@53f98000 { /* WDOG1 */ | |
214 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | |
215 | reg = <0x53f98000 0x4000>; | |
216 | interrupts = <58>; | |
73d2b4cd SG |
217 | }; |
218 | ||
219 | wdog@53f9c000 { /* WDOG2 */ | |
220 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | |
221 | reg = <0x53f9c000 0x4000>; | |
222 | interrupts = <59>; | |
223 | status = "disabled"; | |
224 | }; | |
225 | ||
5be03a7b SG |
226 | iomuxc@53fa8000 { |
227 | compatible = "fsl,imx53-iomuxc"; | |
228 | reg = <0x53fa8000 0x4000>; | |
229 | ||
230 | audmux { | |
231 | pinctrl_audmux_1: audmuxgrp-1 { | |
232 | fsl,pins = < | |
233 | 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ | |
234 | 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ | |
235 | 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ | |
236 | 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ | |
237 | >; | |
238 | }; | |
239 | }; | |
240 | ||
241 | fec { | |
242 | pinctrl_fec_1: fecgrp-1 { | |
243 | fsl,pins = < | |
244 | 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ | |
245 | 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ | |
246 | 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ | |
247 | 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ | |
248 | 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ | |
249 | 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ | |
250 | 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ | |
251 | 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ | |
252 | 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ | |
253 | 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ | |
254 | >; | |
255 | }; | |
256 | }; | |
257 | ||
327a79c0 SG |
258 | ecspi1 { |
259 | pinctrl_ecspi1_1: ecspi1grp-1 { | |
260 | fsl,pins = < | |
261 | 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ | |
262 | 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ | |
263 | 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ | |
264 | >; | |
265 | }; | |
266 | }; | |
267 | ||
5be03a7b SG |
268 | esdhc1 { |
269 | pinctrl_esdhc1_1: esdhc1grp-1 { | |
270 | fsl,pins = < | |
271 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | |
272 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | |
273 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | |
274 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | |
275 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | |
276 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | |
277 | >; | |
278 | }; | |
4bb6143c SG |
279 | |
280 | pinctrl_esdhc1_2: esdhc1grp-2 { | |
281 | fsl,pins = < | |
282 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | |
283 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | |
284 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | |
285 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | |
286 | 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ | |
287 | 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ | |
288 | 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ | |
289 | 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ | |
290 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | |
291 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | |
292 | >; | |
293 | }; | |
5be03a7b SG |
294 | }; |
295 | ||
07248042 SG |
296 | esdhc2 { |
297 | pinctrl_esdhc2_1: esdhc2grp-1 { | |
298 | fsl,pins = < | |
299 | 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ | |
300 | 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ | |
301 | 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ | |
302 | 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ | |
303 | 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ | |
304 | 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ | |
305 | >; | |
306 | }; | |
307 | }; | |
308 | ||
5be03a7b SG |
309 | esdhc3 { |
310 | pinctrl_esdhc3_1: esdhc3grp-1 { | |
311 | fsl,pins = < | |
312 | 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ | |
313 | 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ | |
314 | 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ | |
315 | 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ | |
316 | 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ | |
317 | 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ | |
318 | 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ | |
319 | 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ | |
320 | 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ | |
321 | 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ | |
322 | >; | |
323 | }; | |
324 | }; | |
325 | ||
326 | i2c1 { | |
327 | pinctrl_i2c1_1: i2c1grp-1 { | |
328 | fsl,pins = < | |
329 | 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ | |
330 | 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ | |
331 | >; | |
332 | }; | |
333 | }; | |
334 | ||
335 | i2c2 { | |
336 | pinctrl_i2c2_1: i2c2grp-1 { | |
337 | fsl,pins = < | |
338 | 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ | |
339 | 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ | |
340 | >; | |
341 | }; | |
342 | }; | |
343 | ||
344 | uart1 { | |
345 | pinctrl_uart1_1: uart1grp-1 { | |
346 | fsl,pins = < | |
347 | 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ | |
348 | 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ | |
349 | >; | |
350 | }; | |
4bb6143c SG |
351 | |
352 | pinctrl_uart1_2: uart1grp-2 { | |
353 | fsl,pins = < | |
354 | 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ | |
355 | 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ | |
356 | >; | |
357 | }; | |
5be03a7b | 358 | }; |
07248042 SG |
359 | |
360 | uart2 { | |
361 | pinctrl_uart2_1: uart2grp-1 { | |
362 | fsl,pins = < | |
363 | 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ | |
364 | 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ | |
365 | >; | |
366 | }; | |
367 | }; | |
368 | ||
369 | uart3 { | |
370 | pinctrl_uart3_1: uart3grp-1 { | |
371 | fsl,pins = < | |
372 | 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ | |
373 | 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ | |
374 | 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ | |
375 | 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ | |
376 | >; | |
377 | }; | |
378 | }; | |
5be03a7b SG |
379 | }; |
380 | ||
0c456cfa | 381 | uart1: serial@53fbc000 { |
73d2b4cd SG |
382 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
383 | reg = <0x53fbc000 0x4000>; | |
384 | interrupts = <31>; | |
385 | status = "disabled"; | |
386 | }; | |
387 | ||
0c456cfa | 388 | uart2: serial@53fc0000 { |
73d2b4cd SG |
389 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
390 | reg = <0x53fc0000 0x4000>; | |
391 | interrupts = <32>; | |
392 | status = "disabled"; | |
393 | }; | |
394 | ||
a9d1f924 ST |
395 | can1: can@53fc8000 { |
396 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
397 | reg = <0x53fc8000 0x4000>; | |
398 | interrupts = <82>; | |
399 | status = "disabled"; | |
400 | }; | |
401 | ||
402 | can2: can@53fcc000 { | |
403 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
404 | reg = <0x53fcc000 0x4000>; | |
405 | interrupts = <83>; | |
406 | status = "disabled"; | |
407 | }; | |
408 | ||
4d191868 | 409 | gpio5: gpio@53fdc000 { |
aeb27748 | 410 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
411 | reg = <0x53fdc000 0x4000>; |
412 | interrupts = <103 104>; | |
413 | gpio-controller; | |
414 | #gpio-cells = <2>; | |
415 | interrupt-controller; | |
88cde8b7 | 416 | #interrupt-cells = <2>; |
73d2b4cd SG |
417 | }; |
418 | ||
4d191868 | 419 | gpio6: gpio@53fe0000 { |
aeb27748 | 420 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
421 | reg = <0x53fe0000 0x4000>; |
422 | interrupts = <105 106>; | |
423 | gpio-controller; | |
424 | #gpio-cells = <2>; | |
425 | interrupt-controller; | |
88cde8b7 | 426 | #interrupt-cells = <2>; |
73d2b4cd SG |
427 | }; |
428 | ||
4d191868 | 429 | gpio7: gpio@53fe4000 { |
aeb27748 | 430 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
431 | reg = <0x53fe4000 0x4000>; |
432 | interrupts = <107 108>; | |
433 | gpio-controller; | |
434 | #gpio-cells = <2>; | |
435 | interrupt-controller; | |
88cde8b7 | 436 | #interrupt-cells = <2>; |
73d2b4cd SG |
437 | }; |
438 | ||
439 | i2c@53fec000 { /* I2C3 */ | |
440 | #address-cells = <1>; | |
441 | #size-cells = <0>; | |
5bdfba29 | 442 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
443 | reg = <0x53fec000 0x4000>; |
444 | interrupts = <64>; | |
445 | status = "disabled"; | |
446 | }; | |
447 | ||
0c456cfa | 448 | uart4: serial@53ff0000 { |
73d2b4cd SG |
449 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
450 | reg = <0x53ff0000 0x4000>; | |
451 | interrupts = <13>; | |
452 | status = "disabled"; | |
453 | }; | |
454 | }; | |
455 | ||
456 | aips@60000000 { /* AIPS2 */ | |
457 | compatible = "fsl,aips-bus", "simple-bus"; | |
458 | #address-cells = <1>; | |
459 | #size-cells = <1>; | |
460 | reg = <0x60000000 0x10000000>; | |
461 | ranges; | |
462 | ||
0c456cfa | 463 | uart5: serial@63f90000 { |
73d2b4cd SG |
464 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
465 | reg = <0x63f90000 0x4000>; | |
466 | interrupts = <86>; | |
467 | status = "disabled"; | |
468 | }; | |
469 | ||
470 | ecspi@63fac000 { /* ECSPI2 */ | |
471 | #address-cells = <1>; | |
472 | #size-cells = <0>; | |
473 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
474 | reg = <0x63fac000 0x4000>; | |
475 | interrupts = <37>; | |
476 | status = "disabled"; | |
477 | }; | |
478 | ||
479 | sdma@63fb0000 { | |
480 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; | |
481 | reg = <0x63fb0000 0x4000>; | |
482 | interrupts = <6>; | |
7e4f0365 | 483 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
73d2b4cd SG |
484 | }; |
485 | ||
486 | cspi@63fc0000 { | |
487 | #address-cells = <1>; | |
488 | #size-cells = <0>; | |
489 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
490 | reg = <0x63fc0000 0x4000>; | |
491 | interrupts = <38>; | |
492 | status = "disabled"; | |
493 | }; | |
494 | ||
495 | i2c@63fc4000 { /* I2C2 */ | |
496 | #address-cells = <1>; | |
497 | #size-cells = <0>; | |
5bdfba29 | 498 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
499 | reg = <0x63fc4000 0x4000>; |
500 | interrupts = <63>; | |
501 | status = "disabled"; | |
502 | }; | |
503 | ||
504 | i2c@63fc8000 { /* I2C1 */ | |
505 | #address-cells = <1>; | |
506 | #size-cells = <0>; | |
5bdfba29 | 507 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
508 | reg = <0x63fc8000 0x4000>; |
509 | interrupts = <62>; | |
510 | status = "disabled"; | |
511 | }; | |
512 | ||
ffc505c0 SG |
513 | ssi1: ssi@63fcc000 { |
514 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
515 | reg = <0x63fcc000 0x4000>; | |
516 | interrupts = <29>; | |
517 | fsl,fifo-depth = <15>; | |
518 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
519 | status = "disabled"; | |
520 | }; | |
521 | ||
522 | audmux@63fd0000 { | |
523 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; | |
524 | reg = <0x63fd0000 0x4000>; | |
525 | status = "disabled"; | |
526 | }; | |
527 | ||
75453a08 SH |
528 | nand@63fdb000 { |
529 | compatible = "fsl,imx53-nand"; | |
530 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
531 | interrupts = <8>; | |
532 | status = "disabled"; | |
533 | }; | |
534 | ||
ffc505c0 SG |
535 | ssi3: ssi@63fe8000 { |
536 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
537 | reg = <0x63fe8000 0x4000>; | |
538 | interrupts = <96>; | |
539 | fsl,fifo-depth = <15>; | |
540 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ | |
541 | status = "disabled"; | |
542 | }; | |
543 | ||
0c456cfa | 544 | ethernet@63fec000 { |
73d2b4cd SG |
545 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
546 | reg = <0x63fec000 0x4000>; | |
547 | interrupts = <87>; | |
548 | status = "disabled"; | |
549 | }; | |
550 | }; | |
551 | }; | |
552 | }; |