Commit | Line | Data |
---|---|---|
9a8d6d55 | 1 | |
7c1da585 SG |
2 | /* |
3 | * Copyright 2013 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | */ | |
10 | ||
f89f5b46 | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
9a8d6d55 | 12 | #include "imx6dl-pinfunc.h" |
c56009b2 | 13 | #include "imx6qdl.dtsi" |
7c1da585 SG |
14 | |
15 | / { | |
225fc6d2 VZ |
16 | aliases { |
17 | i2c3 = &i2c4; | |
18 | }; | |
19 | ||
7c1da585 SG |
20 | cpus { |
21 | #address-cells = <1>; | |
22 | #size-cells = <0>; | |
23 | ||
24 | cpu@0 { | |
25 | compatible = "arm,cortex-a9"; | |
7925e89f | 26 | device_type = "cpu"; |
7c1da585 SG |
27 | reg = <0>; |
28 | next-level-cache = <&L2>; | |
978ed904 AH |
29 | operating-points = < |
30 | /* kHz uV */ | |
4c61a1e7 | 31 | 996000 1250000 |
978ed904 AH |
32 | 792000 1175000 |
33 | 396000 1075000 | |
34 | >; | |
35 | fsl,soc-operating-points = < | |
36 | /* ARM kHz SOC-PU uV */ | |
37 | 996000 1175000 | |
38 | 792000 1175000 | |
39 | 396000 1175000 | |
40 | >; | |
41 | clock-latency = <61036>; /* two CLK32 periods */ | |
8888f651 SG |
42 | clocks = <&clks IMX6QDL_CLK_ARM>, |
43 | <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, | |
44 | <&clks IMX6QDL_CLK_STEP>, | |
45 | <&clks IMX6QDL_CLK_PLL1_SW>, | |
46 | <&clks IMX6QDL_CLK_PLL1_SYS>; | |
978ed904 AH |
47 | clock-names = "arm", "pll2_pfd2_396m", "step", |
48 | "pll1_sw", "pll1_sys"; | |
49 | arm-supply = <®_arm>; | |
50 | pu-supply = <®_pu>; | |
51 | soc-supply = <®_soc>; | |
7c1da585 SG |
52 | }; |
53 | ||
54 | cpu@1 { | |
55 | compatible = "arm,cortex-a9"; | |
7925e89f | 56 | device_type = "cpu"; |
7c1da585 SG |
57 | reg = <1>; |
58 | next-level-cache = <&L2>; | |
59 | }; | |
60 | }; | |
61 | ||
62 | soc { | |
951ebf58 SG |
63 | ocram: sram@00900000 { |
64 | compatible = "mmio-sram"; | |
65 | reg = <0x00900000 0x20000>; | |
8888f651 | 66 | clocks = <&clks IMX6QDL_CLK_OCRAM>; |
951ebf58 SG |
67 | }; |
68 | ||
7c1da585 | 69 | aips1: aips-bus@02000000 { |
9a8d6d55 SG |
70 | iomuxc: iomuxc@020e0000 { |
71 | compatible = "fsl,imx6dl-iomuxc"; | |
9a8d6d55 SG |
72 | }; |
73 | ||
7c1da585 SG |
74 | pxp: pxp@020f0000 { |
75 | reg = <0x020f0000 0x4000>; | |
f89f5b46 | 76 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
7c1da585 SG |
77 | }; |
78 | ||
79 | epdc: epdc@020f4000 { | |
80 | reg = <0x020f4000 0x4000>; | |
f89f5b46 | 81 | interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
7c1da585 SG |
82 | }; |
83 | ||
84 | lcdif: lcdif@020f8000 { | |
85 | reg = <0x020f8000 0x4000>; | |
f89f5b46 | 86 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
7c1da585 SG |
87 | }; |
88 | }; | |
89 | ||
90 | aips2: aips-bus@02100000 { | |
91 | i2c4: i2c@021f8000 { | |
92 | #address-cells = <1>; | |
93 | #size-cells = <0>; | |
b92d7763 | 94 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7c1da585 | 95 | reg = <0x021f8000 0x4000>; |
f89f5b46 | 96 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 97 | clocks = <&clks IMX6DL_CLK_I2C4>; |
7c1da585 SG |
98 | status = "disabled"; |
99 | }; | |
100 | }; | |
101 | }; | |
4520e692 PZ |
102 | |
103 | display-subsystem { | |
104 | compatible = "fsl,imx-display-subsystem"; | |
105 | ports = <&ipu1_di0>, <&ipu1_di1>; | |
106 | }; | |
419e202b LS |
107 | |
108 | gpu-subsystem { | |
109 | compatible = "fsl,imx-gpu-subsystem"; | |
110 | cores = <&gpu_2d>, <&gpu_3d>; | |
111 | }; | |
4520e692 PZ |
112 | }; |
113 | ||
4e415ed8 | 114 | &gpt { |
c1b99ded | 115 | compatible = "fsl,imx6dl-gpt"; |
4e415ed8 SG |
116 | }; |
117 | ||
4520e692 PZ |
118 | &hdmi { |
119 | compatible = "fsl,imx6dl-hdmi"; | |
7c1da585 | 120 | }; |
964c847a PZ |
121 | |
122 | &ldb { | |
8888f651 SG |
123 | clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, |
124 | <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, | |
125 | <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; | |
964c847a PZ |
126 | clock-names = "di0_pll", "di1_pll", |
127 | "di0_sel", "di1_sel", | |
128 | "di0", "di1"; | |
cf83eb24 | 129 | }; |
a04a0b6f PZ |
130 | |
131 | &vpu { | |
132 | compatible = "fsl,imx6dl-vpu", "cnm,coda960"; | |
133 | }; |