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ARM: imx6q: disable usb charger detector
[deliverable/linux.git] / arch / arm / boot / dts / imx6q.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
8f9ffecf
RZ		 17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
7d740f87
SG		 22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 compatible = "arm,cortex-a9";
30 reg = <0>;
31 next-level-cache = <&L2>;
32 };
33
34 cpu@1 {
35 compatible = "arm,cortex-a9";
36 reg = <1>;
37 next-level-cache = <&L2>;
38 };
39
40 cpu@2 {
41 compatible = "arm,cortex-a9";
42 reg = <2>;
43 next-level-cache = <&L2>;
44 };
45
46 cpu@3 {
47 compatible = "arm,cortex-a9";
48 reg = <3>;
49 next-level-cache = <&L2>;
50 };
51 };
52
53 intc: interrupt-controller@00a01000 {
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58 interrupt-controller;
59 reg = <0x00a01000 0x1000>,
60 <0x00a00100 0x100>;
61 };
62
63 clocks {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ckil {
68 compatible = "fsl,imx-ckil", "fixed-clock";
69 clock-frequency = <32768>;
70 };
71
72 ckih1 {
73 compatible = "fsl,imx-ckih1", "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 osc {
78 compatible = "fsl,imx-osc", "fixed-clock";
79 clock-frequency = <24000000>;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&intc>;
88 ranges;
89
e5d0f9f5
HS		 90 dma-apbh@00110000 {
91 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
92 reg = <0x00110000 0x2000>;
93 };
94
cf922fa8
HS		 95 gpmi-nand@00112000 {
96 compatible = "fsl,imx6q-gpmi-nand";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
100 reg-names = "gpmi-nand", "bch";
101 interrupts = <0 13 0x04>, <0 15 0x04>;
102 interrupt-names = "gpmi-dma", "bch";
103 fsl,gpmi-dma-channel = <0>;
104 status = "disabled";
105 };
106
7d740f87 107 timer@00a00600 {
58458e03
MZ		 108 compatible = "arm,cortex-a9-twd-timer";
109 reg = <0x00a00600 0x20>;
110 interrupts = <1 13 0xf01>;
7d740f87
SG		 111 };
112
113 L2: l2-cache@00a02000 {
114 compatible = "arm,pl310-cache";
115 reg = <0x00a02000 0x1000>;
116 interrupts = <0 92 0x04>;
117 cache-unified;
118 cache-level = <2>;
119 };
120
121 aips-bus@02000000 { /* AIPS1 */
122 compatible = "fsl,aips-bus", "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 reg = <0x02000000 0x100000>;
126 ranges;
127
128 spba-bus@02000000 {
129 compatible = "fsl,spba-bus", "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 reg = <0x02000000 0x40000>;
133 ranges;
134
135 spdif@02004000 {
136 reg = <0x02004000 0x4000>;
137 interrupts = <0 52 0x04>;
138 };
139
140 ecspi@02008000 { /* eCSPI1 */
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
144 reg = <0x02008000 0x4000>;
145 interrupts = <0 31 0x04>;
146 status = "disabled";
147 };
148
149 ecspi@0200c000 { /* eCSPI2 */
150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
153 reg = <0x0200c000 0x4000>;
154 interrupts = <0 32 0x04>;
155 status = "disabled";
156 };
157
158 ecspi@02010000 { /* eCSPI3 */
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02010000 0x4000>;
163 interrupts = <0 33 0x04>;
164 status = "disabled";
165 };
166
167 ecspi@02014000 { /* eCSPI4 */
168 #address-cells = <1>;
169 #size-cells = <0>;
170 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
171 reg = <0x02014000 0x4000>;
172 interrupts = <0 34 0x04>;
173 status = "disabled";
174 };
175
176 ecspi@02018000 { /* eCSPI5 */
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
180 reg = <0x02018000 0x4000>;
181 interrupts = <0 35 0x04>;
182 status = "disabled";
183 };
184
0c456cfa 185 uart1: serial@02020000 {
7d740f87
SG		 186 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
187 reg = <0x02020000 0x4000>;
188 interrupts = <0 26 0x04>;
189 status = "disabled";
190 };
191
192 esai@02024000 {
193 reg = <0x02024000 0x4000>;
194 interrupts = <0 51 0x04>;
195 };
196
b1a5da8e
RZ		 197 ssi1: ssi@02028000 {
198 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 199 reg = <0x02028000 0x4000>;
200 interrupts = <0 46 0x04>;
b1a5da8e
RZ		 201 fsl,fifo-depth = <15>;
202 fsl,ssi-dma-events = <38 37>;
203 status = "disabled";
7d740f87
SG		 204 };
205
b1a5da8e
RZ		 206 ssi2: ssi@0202c000 {
207 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 208 reg = <0x0202c000 0x4000>;
209 interrupts = <0 47 0x04>;
b1a5da8e
RZ		 210 fsl,fifo-depth = <15>;
211 fsl,ssi-dma-events = <42 41>;
212 status = "disabled";
7d740f87
SG		 213 };
214
b1a5da8e
RZ		 215 ssi3: ssi@02030000 {
216 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 217 reg = <0x02030000 0x4000>;
218 interrupts = <0 48 0x04>;
b1a5da8e
RZ		 219 fsl,fifo-depth = <15>;
220 fsl,ssi-dma-events = <46 45>;
221 status = "disabled";
7d740f87
SG		 222 };
223
224 asrc@02034000 {
225 reg = <0x02034000 0x4000>;
226 interrupts = <0 50 0x04>;
227 };
228
229 spba@0203c000 {
230 reg = <0x0203c000 0x4000>;
231 };
232 };
233
234 vpu@02040000 {
235 reg = <0x02040000 0x3c000>;
236 interrupts = <0 3 0x04 0 12 0x04>;
237 };
238
239 aipstz@0207c000 { /* AIPSTZ1 */
240 reg = <0x0207c000 0x4000>;
241 };
242
243 pwm@02080000 { /* PWM1 */
244 reg = <0x02080000 0x4000>;
245 interrupts = <0 83 0x04>;
246 };
247
248 pwm@02084000 { /* PWM2 */
249 reg = <0x02084000 0x4000>;
250 interrupts = <0 84 0x04>;
251 };
252
253 pwm@02088000 { /* PWM3 */
254 reg = <0x02088000 0x4000>;
255 interrupts = <0 85 0x04>;
256 };
257
258 pwm@0208c000 { /* PWM4 */
259 reg = <0x0208c000 0x4000>;
260 interrupts = <0 86 0x04>;
261 };
262
263 flexcan@02090000 { /* CAN1 */
264 reg = <0x02090000 0x4000>;
265 interrupts = <0 110 0x04>;
266 };
267
268 flexcan@02094000 { /* CAN2 */
269 reg = <0x02094000 0x4000>;
270 interrupts = <0 111 0x04>;
271 };
272
273 gpt@02098000 {
274 compatible = "fsl,imx6q-gpt";
275 reg = <0x02098000 0x4000>;
276 interrupts = <0 55 0x04>;
277 };
278
4d191868 279 gpio1: gpio@0209c000 {
7d740f87
SG		 280 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
281 reg = <0x0209c000 0x4000>;
282 interrupts = <0 66 0x04 0 67 0x04>;
283 gpio-controller;
284 #gpio-cells = <2>;
285 interrupt-controller;
88cde8b7 286 #interrupt-cells = <2>;
7d740f87
SG		 287 };
288
4d191868 289 gpio2: gpio@020a0000 {
7d740f87
SG		 290 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
291 reg = <0x020a0000 0x4000>;
292 interrupts = <0 68 0x04 0 69 0x04>;
293 gpio-controller;
294 #gpio-cells = <2>;
295 interrupt-controller;
88cde8b7 296 #interrupt-cells = <2>;
7d740f87
SG		 297 };
298
4d191868 299 gpio3: gpio@020a4000 {
7d740f87
SG		 300 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
301 reg = <0x020a4000 0x4000>;
302 interrupts = <0 70 0x04 0 71 0x04>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
88cde8b7 306 #interrupt-cells = <2>;
7d740f87
SG		 307 };
308
4d191868 309 gpio4: gpio@020a8000 {
7d740f87
SG		 310 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
311 reg = <0x020a8000 0x4000>;
312 interrupts = <0 72 0x04 0 73 0x04>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
88cde8b7 316 #interrupt-cells = <2>;
7d740f87
SG		 317 };
318
4d191868 319 gpio5: gpio@020ac000 {
7d740f87
SG		 320 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
321 reg = <0x020ac000 0x4000>;
322 interrupts = <0 74 0x04 0 75 0x04>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
88cde8b7 326 #interrupt-cells = <2>;
7d740f87
SG		 327 };
328
4d191868 329 gpio6: gpio@020b0000 {
7d740f87
SG		 330 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
331 reg = <0x020b0000 0x4000>;
332 interrupts = <0 76 0x04 0 77 0x04>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
88cde8b7 336 #interrupt-cells = <2>;
7d740f87
SG		 337 };
338
4d191868 339 gpio7: gpio@020b4000 {
7d740f87
SG		 340 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
341 reg = <0x020b4000 0x4000>;
342 interrupts = <0 78 0x04 0 79 0x04>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 interrupt-controller;
88cde8b7 346 #interrupt-cells = <2>;
7d740f87
SG		 347 };
348
349 kpp@020b8000 {
350 reg = <0x020b8000 0x4000>;
351 interrupts = <0 82 0x04>;
352 };
353
354 wdog@020bc000 { /* WDOG1 */
355 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
356 reg = <0x020bc000 0x4000>;
357 interrupts = <0 80 0x04>;
358 status = "disabled";
359 };
360
361 wdog@020c0000 { /* WDOG2 */
362 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
363 reg = <0x020c0000 0x4000>;
364 interrupts = <0 81 0x04>;
365 status = "disabled";
366 };
367
368 ccm@020c4000 {
369 compatible = "fsl,imx6q-ccm";
370 reg = <0x020c4000 0x4000>;
371 interrupts = <0 87 0x04 0 88 0x04>;
372 };
373
374 anatop@020c8000 {
375 compatible = "fsl,imx6q-anatop";
376 reg = <0x020c8000 0x1000>;
377 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
a1e327e6
YCLP		 378
379 regulator-1p1@110 {
380 compatible = "fsl,anatop-regulator";
381 regulator-name = "vdd1p1";
382 regulator-min-microvolt = <800000>;
383 regulator-max-microvolt = <1375000>;
384 regulator-always-on;
385 anatop-reg-offset = <0x110>;
386 anatop-vol-bit-shift = <8>;
387 anatop-vol-bit-width = <5>;
388 anatop-min-bit-val = <4>;
389 anatop-min-voltage = <800000>;
390 anatop-max-voltage = <1375000>;
391 };
392
393 regulator-3p0@120 {
394 compatible = "fsl,anatop-regulator";
395 regulator-name = "vdd3p0";
396 regulator-min-microvolt = <2800000>;
397 regulator-max-microvolt = <3150000>;
398 regulator-always-on;
399 anatop-reg-offset = <0x120>;
400 anatop-vol-bit-shift = <8>;
401 anatop-vol-bit-width = <5>;
402 anatop-min-bit-val = <0>;
403 anatop-min-voltage = <2625000>;
404 anatop-max-voltage = <3400000>;
405 };
406
407 regulator-2p5@130 {
408 compatible = "fsl,anatop-regulator";
409 regulator-name = "vdd2p5";
410 regulator-min-microvolt = <2000000>;
411 regulator-max-microvolt = <2750000>;
412 regulator-always-on;
413 anatop-reg-offset = <0x130>;
414 anatop-vol-bit-shift = <8>;
415 anatop-vol-bit-width = <5>;
416 anatop-min-bit-val = <0>;
417 anatop-min-voltage = <2000000>;
418 anatop-max-voltage = <2750000>;
419 };
420
421 regulator-vddcore@140 {
422 compatible = "fsl,anatop-regulator";
423 regulator-name = "cpu";
424 regulator-min-microvolt = <725000>;
425 regulator-max-microvolt = <1450000>;
426 regulator-always-on;
427 anatop-reg-offset = <0x140>;
428 anatop-vol-bit-shift = <0>;
429 anatop-vol-bit-width = <5>;
430 anatop-min-bit-val = <1>;
431 anatop-min-voltage = <725000>;
432 anatop-max-voltage = <1450000>;
433 };
434
435 regulator-vddpu@140 {
436 compatible = "fsl,anatop-regulator";
437 regulator-name = "vddpu";
438 regulator-min-microvolt = <725000>;
439 regulator-max-microvolt = <1450000>;
440 regulator-always-on;
441 anatop-reg-offset = <0x140>;
442 anatop-vol-bit-shift = <9>;
443 anatop-vol-bit-width = <5>;
444 anatop-min-bit-val = <1>;
445 anatop-min-voltage = <725000>;
446 anatop-max-voltage = <1450000>;
447 };
448
449 regulator-vddsoc@140 {
450 compatible = "fsl,anatop-regulator";
451 regulator-name = "vddsoc";
452 regulator-min-microvolt = <725000>;
453 regulator-max-microvolt = <1450000>;
454 regulator-always-on;
455 anatop-reg-offset = <0x140>;
456 anatop-vol-bit-shift = <18>;
457 anatop-vol-bit-width = <5>;
458 anatop-min-bit-val = <1>;
459 anatop-min-voltage = <725000>;
460 anatop-max-voltage = <1450000>;
461 };
7d740f87
SG		 462 };
463
464 usbphy@020c9000 { /* USBPHY1 */
465 reg = <0x020c9000 0x1000>;
466 interrupts = <0 44 0x04>;
467 };
468
469 usbphy@020ca000 { /* USBPHY2 */
470 reg = <0x020ca000 0x1000>;
471 interrupts = <0 45 0x04>;
472 };
473
474 snvs@020cc000 {
475 reg = <0x020cc000 0x4000>;
476 interrupts = <0 19 0x04 0 20 0x04>;
477 };
478
479 epit@020d0000 { /* EPIT1 */
480 reg = <0x020d0000 0x4000>;
481 interrupts = <0 56 0x04>;
482 };
483
484 epit@020d4000 { /* EPIT2 */
485 reg = <0x020d4000 0x4000>;
486 interrupts = <0 57 0x04>;
487 };
488
489 src@020d8000 {
490 compatible = "fsl,imx6q-src";
491 reg = <0x020d8000 0x4000>;
492 interrupts = <0 91 0x04 0 96 0x04>;
493 };
494
495 gpc@020dc000 {
496 compatible = "fsl,imx6q-gpc";
497 reg = <0x020dc000 0x4000>;
498 interrupts = <0 89 0x04 0 90 0x04>;
499 };
500
501 iomuxc@020e0000 {
551fd208 502 compatible = "fsl,imx6q-iomuxc";
7d740f87 503 reg = <0x020e0000 0x4000>;
551fd208
DA		 504
505 /* shared pinctrl settings */
5ca65c18
RZ		 506 audmux {
507 pinctrl_audmux_1: audmux-1 {
508 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
509 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
510 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
511 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
512 };
513 };
514
cf922fa8
HS		 515 gpmi-nand {
516 pinctrl_gpmi_nand_1: gpmi-nand-1 {
517 fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
518 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
519 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
520 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
521 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
522 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
523 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
524 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
525 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
526 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
527 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
528 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
529 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
530 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
531 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
532 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
533 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
534 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
535 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
536 };
537 };
538
d99a79fc
RZ		 539 i2c1 {
540 pinctrl_i2c1_1: i2c1grp-1 {
541 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
542 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
543 };
544 };
545
c3001b2a
RZ		 546 serial2 {
547 pinctrl_serial2_1: serial2grp-1 {
548 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
549 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
550 };
551 };
552
551fd208
DA		 553 usdhc3 {
554 pinctrl_usdhc3_1: usdhc3grp-1 {
555 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
556 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
557 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
558 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
559 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
560 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
561 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
562 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
563 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
564 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
565 };
566 };
567
568 usdhc4 {
569 pinctrl_usdhc4_1: usdhc4grp-1 {
570 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
571 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
572 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
573 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
574 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
575 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
576 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
577 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
578 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
579 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
580 };
581 };
7d740f87
SG		 582 };
583
584 dcic@020e4000 { /* DCIC1 */
585 reg = <0x020e4000 0x4000>;
586 interrupts = <0 124 0x04>;
587 };
588
589 dcic@020e8000 { /* DCIC2 */
590 reg = <0x020e8000 0x4000>;
591 interrupts = <0 125 0x04>;
592 };
593
594 sdma@020ec000 {
595 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
596 reg = <0x020ec000 0x4000>;
597 interrupts = <0 2 0x04>;
598 };
599 };
600
601 aips-bus@02100000 { /* AIPS2 */
602 compatible = "fsl,aips-bus", "simple-bus";
603 #address-cells = <1>;
604 #size-cells = <1>;
605 reg = <0x02100000 0x100000>;
606 ranges;
607
608 caam@02100000 {
609 reg = <0x02100000 0x40000>;
610 interrupts = <0 105 0x04 0 106 0x04>;
611 };
612
613 aipstz@0217c000 { /* AIPSTZ2 */
614 reg = <0x0217c000 0x4000>;
615 };
616
0c456cfa 617 ethernet@02188000 {
7d740f87
SG		 618 compatible = "fsl,imx6q-fec";
619 reg = <0x02188000 0x4000>;
620 interrupts = <0 118 0x04 0 119 0x04>;
621 status = "disabled";
622 };
623
624 mlb@0218c000 {
625 reg = <0x0218c000 0x4000>;
626 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
627 };
628
629 usdhc@02190000 { /* uSDHC1 */
630 compatible = "fsl,imx6q-usdhc";
631 reg = <0x02190000 0x4000>;
632 interrupts = <0 22 0x04>;
633 status = "disabled";
634 };
635
636 usdhc@02194000 { /* uSDHC2 */
637 compatible = "fsl,imx6q-usdhc";
638 reg = <0x02194000 0x4000>;
639 interrupts = <0 23 0x04>;
640 status = "disabled";
641 };
642
643 usdhc@02198000 { /* uSDHC3 */
644 compatible = "fsl,imx6q-usdhc";
645 reg = <0x02198000 0x4000>;
646 interrupts = <0 24 0x04>;
647 status = "disabled";
648 };
649
650 usdhc@0219c000 { /* uSDHC4 */
651 compatible = "fsl,imx6q-usdhc";
652 reg = <0x0219c000 0x4000>;
653 interrupts = <0 25 0x04>;
654 status = "disabled";
655 };
656
657 i2c@021a0000 { /* I2C1 */
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
661 reg = <0x021a0000 0x4000>;
662 interrupts = <0 36 0x04>;
663 status = "disabled";
664 };
665
666 i2c@021a4000 { /* I2C2 */
667 #address-cells = <1>;
668 #size-cells = <0>;
669 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
670 reg = <0x021a4000 0x4000>;
671 interrupts = <0 37 0x04>;
672 status = "disabled";
673 };
674
675 i2c@021a8000 { /* I2C3 */
676 #address-cells = <1>;
677 #size-cells = <0>;
678 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
679 reg = <0x021a8000 0x4000>;
680 interrupts = <0 38 0x04>;
681 status = "disabled";
682 };
683
684 romcp@021ac000 {
685 reg = <0x021ac000 0x4000>;
686 };
687
688 mmdc@021b0000 { /* MMDC0 */
689 compatible = "fsl,imx6q-mmdc";
690 reg = <0x021b0000 0x4000>;
691 };
692
693 mmdc@021b4000 { /* MMDC1 */
694 reg = <0x021b4000 0x4000>;
695 };
696
697 weim@021b8000 {
698 reg = <0x021b8000 0x4000>;
699 interrupts = <0 14 0x04>;
700 };
701
702 ocotp@021bc000 {
703 reg = <0x021bc000 0x4000>;
704 };
705
706 ocotp@021c0000 {
707 reg = <0x021c0000 0x4000>;
708 interrupts = <0 21 0x04>;
709 };
710
711 tzasc@021d0000 { /* TZASC1 */
712 reg = <0x021d0000 0x4000>;
713 interrupts = <0 108 0x04>;
714 };
715
716 tzasc@021d4000 { /* TZASC2 */
717 reg = <0x021d4000 0x4000>;
718 interrupts = <0 109 0x04>;
719 };
720
721 audmux@021d8000 {
f965cd55 722 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 723 reg = <0x021d8000 0x4000>;
f965cd55 724 status = "disabled";
7d740f87
SG		 725 };
726
727 mipi@021dc000 { /* MIPI-CSI */
728 reg = <0x021dc000 0x4000>;
729 };
730
731 mipi@021e0000 { /* MIPI-DSI */
732 reg = <0x021e0000 0x4000>;
733 };
734
735 vdoa@021e4000 {
736 reg = <0x021e4000 0x4000>;
737 interrupts = <0 18 0x04>;
738 };
739
0c456cfa 740 uart2: serial@021e8000 {
7d740f87
SG		 741 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
742 reg = <0x021e8000 0x4000>;
743 interrupts = <0 27 0x04>;
744 status = "disabled";
745 };
746
0c456cfa 747 uart3: serial@021ec000 {
7d740f87
SG		 748 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
749 reg = <0x021ec000 0x4000>;
750 interrupts = <0 28 0x04>;
751 status = "disabled";
752 };
753
0c456cfa 754 uart4: serial@021f0000 {
7d740f87
SG		 755 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
756 reg = <0x021f0000 0x4000>;
757 interrupts = <0 29 0x04>;
758 status = "disabled";
759 };
760
0c456cfa 761 uart5: serial@021f4000 {
7d740f87
SG		 762 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
763 reg = <0x021f4000 0x4000>;
764 interrupts = <0 30 0x04>;
765 status = "disabled";
766 };
767 };
768 };
769};
Linux kernel - Deliverables
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