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ARM i.MX6q: Add LDB device to device tree
[deliverable/linux.git] / arch / arm / boot / dts / imx6q.dtsi
CommitLineData
7c1da585
SG		 1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
36dffd8f 11#include "imx6qdl.dtsi"
e1641531 12#include "imx6q-pinfunc.h"
7c1da585
SG		 13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 operating-points = <
24 /* kHz uV */
25 1200000 1275000
26 996000 1250000
27 792000 1150000
28 396000 950000
29 >;
30 clock-latency = <61036>; /* two CLK32 periods */
31 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
32 <&clks 17>, <&clks 170>;
33 clock-names = "arm", "pll2_pfd2_396m", "step",
34 "pll1_sw", "pll1_sys";
35 arm-supply = <&reg_arm>;
36 pu-supply = <&reg_pu>;
37 soc-supply = <&reg_soc>;
38 };
39
40 cpu@1 {
41 compatible = "arm,cortex-a9";
42 reg = <1>;
43 next-level-cache = <&L2>;
44 };
45
46 cpu@2 {
47 compatible = "arm,cortex-a9";
48 reg = <2>;
49 next-level-cache = <&L2>;
50 };
51
52 cpu@3 {
53 compatible = "arm,cortex-a9";
54 reg = <3>;
55 next-level-cache = <&L2>;
56 };
57 };
58
59 soc {
60 aips-bus@02000000 { /* AIPS1 */
61 spba-bus@02000000 {
62 ecspi5: ecspi@02018000 {
63 #address-cells = <1>;
64 #size-cells = <0>;
65 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
66 reg = <0x02018000 0x4000>;
67 interrupts = <0 35 0x04>;
68 clocks = <&clks 116>, <&clks 116>;
69 clock-names = "ipg", "per";
70 status = "disabled";
71 };
72 };
73
74 iomuxc: iomuxc@020e0000 {
75 compatible = "fsl,imx6q-iomuxc";
76 reg = <0x020e0000 0x4000>;
77
78 /* shared pinctrl settings */
79 audmux {
80 pinctrl_audmux_1: audmux-1 {
81 fsl,pins = <
e1641531
SG		 82 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
83 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
84 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
85 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
7c1da585
SG		 86 >;
87 };
624dbaca
SC		 88
89 pinctrl_audmux_2: audmux-2 {
90 fsl,pins = <
91 MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
92 MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
93 MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
94 MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
95 >;
96 };
7c1da585
SG		 97 };
98
99 ecspi1 {
100 pinctrl_ecspi1_1: ecspi1grp-1 {
101 fsl,pins = <
e1641531
SG		 102 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
103 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
104 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
7c1da585
SG		 105 >;
106 };
107 };
108
4820a9ac
SC		 109 ecspi3 {
110 pinctrl_ecspi3_1: ecspi3grp-1 {
111 fsl,pins = <
112 MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
113 MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
114 MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
115 >;
116 };
117 };
118
7c1da585
SG		 119 enet {
120 pinctrl_enet_1: enetgrp-1 {
121 fsl,pins = <
e1641531
SG		 122 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
123 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
124 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
125 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
126 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
127 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
128 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
129 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
130 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
131 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
132 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
133 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
134 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
135 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
136 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
137 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
7c1da585
SG		 138 >;
139 };
140
141 pinctrl_enet_2: enetgrp-2 {
142 fsl,pins = <
e1641531
SG		 143 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
144 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
145 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
146 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
147 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
148 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
149 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
150 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
151 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
152 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
153 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
154 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
155 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
156 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
157 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
7c1da585
SG		 158 >;
159 };
160 };
161
162 gpmi-nand {
163 pinctrl_gpmi_nand_1: gpmi-nand-1 {
164 fsl,pins = <
e1641531
SG		 165 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
166 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
167 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
168 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
169 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
170 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
171 MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
172 MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
173 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
174 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
175 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
176 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
177 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
178 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
179 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
180 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
181 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
182 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
183 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
7c1da585
SG		 184 >;
185 };
186 };
187
188 i2c1 {
189 pinctrl_i2c1_1: i2c1grp-1 {
190 fsl,pins = <
e1641531
SG		 191 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
192 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
7c1da585
SG		 193 >;
194 };
195 };
196
d27f512a
SC		 197 i2c2 {
198 pinctrl_i2c2_1: i2c2grp-1 {
199 fsl,pins = <
200 MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
201 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
202 >;
203 };
204 };
205
206 i2c3 {
207 pinctrl_i2c3_1: i2c3grp-1 {
208 fsl,pins = <
209 MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
210 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
211 >;
212 };
213 };
214
7c1da585
SG		 215 uart1 {
216 pinctrl_uart1_1: uart1grp-1 {
217 fsl,pins = <
e1641531
SG		 218 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
219 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
7c1da585
SG		 220 >;
221 };
222 };
223
224 uart2 {
225 pinctrl_uart2_1: uart2grp-1 {
226 fsl,pins = <
e1641531
SG		 227 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
228 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
7c1da585
SG		 229 >;
230 };
231 };
232
233 uart4 {
234 pinctrl_uart4_1: uart4grp-1 {
235 fsl,pins = <
e1641531
SG		 236 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
237 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
7c1da585
SG		 238 >;
239 };
240 };
241
242 usbotg {
243 pinctrl_usbotg_1: usbotggrp-1 {
244 fsl,pins = <
e1641531 245 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
7c1da585
SG		 246 >;
247 };
a10c22e4
PC		 248
249 pinctrl_usbotg_2: usbotggrp-2 {
e1641531
SG		 250 fsl,pins = <
251 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
a10c22e4
PC		 252 >;
253 };
7c1da585
SG		 254 };
255
256 usdhc2 {
257 pinctrl_usdhc2_1: usdhc2grp-1 {
258 fsl,pins = <
e1641531
SG		 259 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
260 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
261 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
262 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
263 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
264 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
265 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
266 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
267 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
268 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
7c1da585
SG		 269 >;
270 };
271 };
272
273 usdhc3 {
274 pinctrl_usdhc3_1: usdhc3grp-1 {
275 fsl,pins = <
e1641531
SG		 276 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
277 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
278 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
279 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
280 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
281 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
282 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
283 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
284 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
285 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
7c1da585
SG		 286 >;
287 };
288
289 pinctrl_usdhc3_2: usdhc3grp-2 {
290 fsl,pins = <
e1641531
SG		 291 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
292 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
293 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
294 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
295 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
296 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
7c1da585
SG		 297 >;
298 };
299 };
300
301 usdhc4 {
302 pinctrl_usdhc4_1: usdhc4grp-1 {
303 fsl,pins = <
e1641531
SG		 304 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
305 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
306 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
307 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
308 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
309 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
310 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
311 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
312 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
313 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
7c1da585
SG		 314 >;
315 };
316
317 pinctrl_usdhc4_2: usdhc4grp-2 {
318 fsl,pins = <
e1641531
SG		 319 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
320 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
321 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
322 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
323 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
324 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
7c1da585
SG		 325 >;
326 };
327 };
328 };
329 };
330
331 ipu2: ipu@02800000 {
332 #crtc-cells = <1>;
333 compatible = "fsl,imx6q-ipu";
334 reg = <0x02800000 0x400000>;
335 interrupts = <0 8 0x4 0 7 0x4>;
336 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
337 clock-names = "bus", "di0", "di1";
338 };
339 };
340};
41c04342
ST		 341
342&ldb {
343 clocks = <&clks 33>, <&clks 34>,
344 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
345 <&clks 135>, <&clks 136>;
346 clock-names = "di0_pll", "di1_pll",
347 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
348 "di0", "di1";
349
350 lvds-channel@0 {
351 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
352 };
353
354 lvds-channel@1 {
355 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
356 };
357};
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