Commit | Line | Data |
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7d740f87 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /include/ "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
8f9ffecf RZ |
17 | serial0 = &uart1; |
18 | serial1 = &uart2; | |
19 | serial2 = &uart3; | |
20 | serial3 = &uart4; | |
21 | serial4 = &uart5; | |
7d740f87 SG |
22 | }; |
23 | ||
24 | cpus { | |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
27 | ||
28 | cpu@0 { | |
29 | compatible = "arm,cortex-a9"; | |
30 | reg = <0>; | |
31 | next-level-cache = <&L2>; | |
32 | }; | |
33 | ||
34 | cpu@1 { | |
35 | compatible = "arm,cortex-a9"; | |
36 | reg = <1>; | |
37 | next-level-cache = <&L2>; | |
38 | }; | |
39 | ||
40 | cpu@2 { | |
41 | compatible = "arm,cortex-a9"; | |
42 | reg = <2>; | |
43 | next-level-cache = <&L2>; | |
44 | }; | |
45 | ||
46 | cpu@3 { | |
47 | compatible = "arm,cortex-a9"; | |
48 | reg = <3>; | |
49 | next-level-cache = <&L2>; | |
50 | }; | |
51 | }; | |
52 | ||
53 | intc: interrupt-controller@00a01000 { | |
54 | compatible = "arm,cortex-a9-gic"; | |
55 | #interrupt-cells = <3>; | |
56 | #address-cells = <1>; | |
57 | #size-cells = <1>; | |
58 | interrupt-controller; | |
59 | reg = <0x00a01000 0x1000>, | |
60 | <0x00a00100 0x100>; | |
61 | }; | |
62 | ||
63 | clocks { | |
64 | #address-cells = <1>; | |
65 | #size-cells = <0>; | |
66 | ||
67 | ckil { | |
68 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
69 | clock-frequency = <32768>; | |
70 | }; | |
71 | ||
72 | ckih1 { | |
73 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
74 | clock-frequency = <0>; | |
75 | }; | |
76 | ||
77 | osc { | |
78 | compatible = "fsl,imx-osc", "fixed-clock"; | |
79 | clock-frequency = <24000000>; | |
80 | }; | |
81 | }; | |
82 | ||
83 | soc { | |
84 | #address-cells = <1>; | |
85 | #size-cells = <1>; | |
86 | compatible = "simple-bus"; | |
87 | interrupt-parent = <&intc>; | |
88 | ranges; | |
89 | ||
90 | timer@00a00600 { | |
58458e03 MZ |
91 | compatible = "arm,cortex-a9-twd-timer"; |
92 | reg = <0x00a00600 0x20>; | |
93 | interrupts = <1 13 0xf01>; | |
7d740f87 SG |
94 | }; |
95 | ||
96 | L2: l2-cache@00a02000 { | |
97 | compatible = "arm,pl310-cache"; | |
98 | reg = <0x00a02000 0x1000>; | |
99 | interrupts = <0 92 0x04>; | |
100 | cache-unified; | |
101 | cache-level = <2>; | |
102 | }; | |
103 | ||
104 | aips-bus@02000000 { /* AIPS1 */ | |
105 | compatible = "fsl,aips-bus", "simple-bus"; | |
106 | #address-cells = <1>; | |
107 | #size-cells = <1>; | |
108 | reg = <0x02000000 0x100000>; | |
109 | ranges; | |
110 | ||
111 | spba-bus@02000000 { | |
112 | compatible = "fsl,spba-bus", "simple-bus"; | |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | reg = <0x02000000 0x40000>; | |
116 | ranges; | |
117 | ||
118 | spdif@02004000 { | |
119 | reg = <0x02004000 0x4000>; | |
120 | interrupts = <0 52 0x04>; | |
121 | }; | |
122 | ||
123 | ecspi@02008000 { /* eCSPI1 */ | |
124 | #address-cells = <1>; | |
125 | #size-cells = <0>; | |
126 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
127 | reg = <0x02008000 0x4000>; | |
128 | interrupts = <0 31 0x04>; | |
129 | status = "disabled"; | |
130 | }; | |
131 | ||
132 | ecspi@0200c000 { /* eCSPI2 */ | |
133 | #address-cells = <1>; | |
134 | #size-cells = <0>; | |
135 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
136 | reg = <0x0200c000 0x4000>; | |
137 | interrupts = <0 32 0x04>; | |
138 | status = "disabled"; | |
139 | }; | |
140 | ||
141 | ecspi@02010000 { /* eCSPI3 */ | |
142 | #address-cells = <1>; | |
143 | #size-cells = <0>; | |
144 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
145 | reg = <0x02010000 0x4000>; | |
146 | interrupts = <0 33 0x04>; | |
147 | status = "disabled"; | |
148 | }; | |
149 | ||
150 | ecspi@02014000 { /* eCSPI4 */ | |
151 | #address-cells = <1>; | |
152 | #size-cells = <0>; | |
153 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
154 | reg = <0x02014000 0x4000>; | |
155 | interrupts = <0 34 0x04>; | |
156 | status = "disabled"; | |
157 | }; | |
158 | ||
159 | ecspi@02018000 { /* eCSPI5 */ | |
160 | #address-cells = <1>; | |
161 | #size-cells = <0>; | |
162 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
163 | reg = <0x02018000 0x4000>; | |
164 | interrupts = <0 35 0x04>; | |
165 | status = "disabled"; | |
166 | }; | |
167 | ||
0c456cfa | 168 | uart1: serial@02020000 { |
7d740f87 SG |
169 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
170 | reg = <0x02020000 0x4000>; | |
171 | interrupts = <0 26 0x04>; | |
172 | status = "disabled"; | |
173 | }; | |
174 | ||
175 | esai@02024000 { | |
176 | reg = <0x02024000 0x4000>; | |
177 | interrupts = <0 51 0x04>; | |
178 | }; | |
179 | ||
b1a5da8e RZ |
180 | ssi1: ssi@02028000 { |
181 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
182 | reg = <0x02028000 0x4000>; |
183 | interrupts = <0 46 0x04>; | |
b1a5da8e RZ |
184 | fsl,fifo-depth = <15>; |
185 | fsl,ssi-dma-events = <38 37>; | |
186 | status = "disabled"; | |
7d740f87 SG |
187 | }; |
188 | ||
b1a5da8e RZ |
189 | ssi2: ssi@0202c000 { |
190 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
191 | reg = <0x0202c000 0x4000>; |
192 | interrupts = <0 47 0x04>; | |
b1a5da8e RZ |
193 | fsl,fifo-depth = <15>; |
194 | fsl,ssi-dma-events = <42 41>; | |
195 | status = "disabled"; | |
7d740f87 SG |
196 | }; |
197 | ||
b1a5da8e RZ |
198 | ssi3: ssi@02030000 { |
199 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
200 | reg = <0x02030000 0x4000>; |
201 | interrupts = <0 48 0x04>; | |
b1a5da8e RZ |
202 | fsl,fifo-depth = <15>; |
203 | fsl,ssi-dma-events = <46 45>; | |
204 | status = "disabled"; | |
7d740f87 SG |
205 | }; |
206 | ||
207 | asrc@02034000 { | |
208 | reg = <0x02034000 0x4000>; | |
209 | interrupts = <0 50 0x04>; | |
210 | }; | |
211 | ||
212 | spba@0203c000 { | |
213 | reg = <0x0203c000 0x4000>; | |
214 | }; | |
215 | }; | |
216 | ||
217 | vpu@02040000 { | |
218 | reg = <0x02040000 0x3c000>; | |
219 | interrupts = <0 3 0x04 0 12 0x04>; | |
220 | }; | |
221 | ||
222 | aipstz@0207c000 { /* AIPSTZ1 */ | |
223 | reg = <0x0207c000 0x4000>; | |
224 | }; | |
225 | ||
226 | pwm@02080000 { /* PWM1 */ | |
227 | reg = <0x02080000 0x4000>; | |
228 | interrupts = <0 83 0x04>; | |
229 | }; | |
230 | ||
231 | pwm@02084000 { /* PWM2 */ | |
232 | reg = <0x02084000 0x4000>; | |
233 | interrupts = <0 84 0x04>; | |
234 | }; | |
235 | ||
236 | pwm@02088000 { /* PWM3 */ | |
237 | reg = <0x02088000 0x4000>; | |
238 | interrupts = <0 85 0x04>; | |
239 | }; | |
240 | ||
241 | pwm@0208c000 { /* PWM4 */ | |
242 | reg = <0x0208c000 0x4000>; | |
243 | interrupts = <0 86 0x04>; | |
244 | }; | |
245 | ||
246 | flexcan@02090000 { /* CAN1 */ | |
247 | reg = <0x02090000 0x4000>; | |
248 | interrupts = <0 110 0x04>; | |
249 | }; | |
250 | ||
251 | flexcan@02094000 { /* CAN2 */ | |
252 | reg = <0x02094000 0x4000>; | |
253 | interrupts = <0 111 0x04>; | |
254 | }; | |
255 | ||
256 | gpt@02098000 { | |
257 | compatible = "fsl,imx6q-gpt"; | |
258 | reg = <0x02098000 0x4000>; | |
259 | interrupts = <0 55 0x04>; | |
260 | }; | |
261 | ||
4d191868 | 262 | gpio1: gpio@0209c000 { |
7d740f87 SG |
263 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
264 | reg = <0x0209c000 0x4000>; | |
265 | interrupts = <0 66 0x04 0 67 0x04>; | |
266 | gpio-controller; | |
267 | #gpio-cells = <2>; | |
268 | interrupt-controller; | |
269 | #interrupt-cells = <1>; | |
270 | }; | |
271 | ||
4d191868 | 272 | gpio2: gpio@020a0000 { |
7d740f87 SG |
273 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
274 | reg = <0x020a0000 0x4000>; | |
275 | interrupts = <0 68 0x04 0 69 0x04>; | |
276 | gpio-controller; | |
277 | #gpio-cells = <2>; | |
278 | interrupt-controller; | |
279 | #interrupt-cells = <1>; | |
280 | }; | |
281 | ||
4d191868 | 282 | gpio3: gpio@020a4000 { |
7d740f87 SG |
283 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
284 | reg = <0x020a4000 0x4000>; | |
285 | interrupts = <0 70 0x04 0 71 0x04>; | |
286 | gpio-controller; | |
287 | #gpio-cells = <2>; | |
288 | interrupt-controller; | |
289 | #interrupt-cells = <1>; | |
290 | }; | |
291 | ||
4d191868 | 292 | gpio4: gpio@020a8000 { |
7d740f87 SG |
293 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
294 | reg = <0x020a8000 0x4000>; | |
295 | interrupts = <0 72 0x04 0 73 0x04>; | |
296 | gpio-controller; | |
297 | #gpio-cells = <2>; | |
298 | interrupt-controller; | |
299 | #interrupt-cells = <1>; | |
300 | }; | |
301 | ||
4d191868 | 302 | gpio5: gpio@020ac000 { |
7d740f87 SG |
303 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
304 | reg = <0x020ac000 0x4000>; | |
305 | interrupts = <0 74 0x04 0 75 0x04>; | |
306 | gpio-controller; | |
307 | #gpio-cells = <2>; | |
308 | interrupt-controller; | |
309 | #interrupt-cells = <1>; | |
310 | }; | |
311 | ||
4d191868 | 312 | gpio6: gpio@020b0000 { |
7d740f87 SG |
313 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
314 | reg = <0x020b0000 0x4000>; | |
315 | interrupts = <0 76 0x04 0 77 0x04>; | |
316 | gpio-controller; | |
317 | #gpio-cells = <2>; | |
318 | interrupt-controller; | |
319 | #interrupt-cells = <1>; | |
320 | }; | |
321 | ||
4d191868 | 322 | gpio7: gpio@020b4000 { |
7d740f87 SG |
323 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
324 | reg = <0x020b4000 0x4000>; | |
325 | interrupts = <0 78 0x04 0 79 0x04>; | |
326 | gpio-controller; | |
327 | #gpio-cells = <2>; | |
328 | interrupt-controller; | |
329 | #interrupt-cells = <1>; | |
330 | }; | |
331 | ||
332 | kpp@020b8000 { | |
333 | reg = <0x020b8000 0x4000>; | |
334 | interrupts = <0 82 0x04>; | |
335 | }; | |
336 | ||
337 | wdog@020bc000 { /* WDOG1 */ | |
338 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | |
339 | reg = <0x020bc000 0x4000>; | |
340 | interrupts = <0 80 0x04>; | |
341 | status = "disabled"; | |
342 | }; | |
343 | ||
344 | wdog@020c0000 { /* WDOG2 */ | |
345 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | |
346 | reg = <0x020c0000 0x4000>; | |
347 | interrupts = <0 81 0x04>; | |
348 | status = "disabled"; | |
349 | }; | |
350 | ||
351 | ccm@020c4000 { | |
352 | compatible = "fsl,imx6q-ccm"; | |
353 | reg = <0x020c4000 0x4000>; | |
354 | interrupts = <0 87 0x04 0 88 0x04>; | |
355 | }; | |
356 | ||
357 | anatop@020c8000 { | |
358 | compatible = "fsl,imx6q-anatop"; | |
359 | reg = <0x020c8000 0x1000>; | |
360 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | |
a1e327e6 YCLP |
361 | |
362 | regulator-1p1@110 { | |
363 | compatible = "fsl,anatop-regulator"; | |
364 | regulator-name = "vdd1p1"; | |
365 | regulator-min-microvolt = <800000>; | |
366 | regulator-max-microvolt = <1375000>; | |
367 | regulator-always-on; | |
368 | anatop-reg-offset = <0x110>; | |
369 | anatop-vol-bit-shift = <8>; | |
370 | anatop-vol-bit-width = <5>; | |
371 | anatop-min-bit-val = <4>; | |
372 | anatop-min-voltage = <800000>; | |
373 | anatop-max-voltage = <1375000>; | |
374 | }; | |
375 | ||
376 | regulator-3p0@120 { | |
377 | compatible = "fsl,anatop-regulator"; | |
378 | regulator-name = "vdd3p0"; | |
379 | regulator-min-microvolt = <2800000>; | |
380 | regulator-max-microvolt = <3150000>; | |
381 | regulator-always-on; | |
382 | anatop-reg-offset = <0x120>; | |
383 | anatop-vol-bit-shift = <8>; | |
384 | anatop-vol-bit-width = <5>; | |
385 | anatop-min-bit-val = <0>; | |
386 | anatop-min-voltage = <2625000>; | |
387 | anatop-max-voltage = <3400000>; | |
388 | }; | |
389 | ||
390 | regulator-2p5@130 { | |
391 | compatible = "fsl,anatop-regulator"; | |
392 | regulator-name = "vdd2p5"; | |
393 | regulator-min-microvolt = <2000000>; | |
394 | regulator-max-microvolt = <2750000>; | |
395 | regulator-always-on; | |
396 | anatop-reg-offset = <0x130>; | |
397 | anatop-vol-bit-shift = <8>; | |
398 | anatop-vol-bit-width = <5>; | |
399 | anatop-min-bit-val = <0>; | |
400 | anatop-min-voltage = <2000000>; | |
401 | anatop-max-voltage = <2750000>; | |
402 | }; | |
403 | ||
404 | regulator-vddcore@140 { | |
405 | compatible = "fsl,anatop-regulator"; | |
406 | regulator-name = "cpu"; | |
407 | regulator-min-microvolt = <725000>; | |
408 | regulator-max-microvolt = <1450000>; | |
409 | regulator-always-on; | |
410 | anatop-reg-offset = <0x140>; | |
411 | anatop-vol-bit-shift = <0>; | |
412 | anatop-vol-bit-width = <5>; | |
413 | anatop-min-bit-val = <1>; | |
414 | anatop-min-voltage = <725000>; | |
415 | anatop-max-voltage = <1450000>; | |
416 | }; | |
417 | ||
418 | regulator-vddpu@140 { | |
419 | compatible = "fsl,anatop-regulator"; | |
420 | regulator-name = "vddpu"; | |
421 | regulator-min-microvolt = <725000>; | |
422 | regulator-max-microvolt = <1450000>; | |
423 | regulator-always-on; | |
424 | anatop-reg-offset = <0x140>; | |
425 | anatop-vol-bit-shift = <9>; | |
426 | anatop-vol-bit-width = <5>; | |
427 | anatop-min-bit-val = <1>; | |
428 | anatop-min-voltage = <725000>; | |
429 | anatop-max-voltage = <1450000>; | |
430 | }; | |
431 | ||
432 | regulator-vddsoc@140 { | |
433 | compatible = "fsl,anatop-regulator"; | |
434 | regulator-name = "vddsoc"; | |
435 | regulator-min-microvolt = <725000>; | |
436 | regulator-max-microvolt = <1450000>; | |
437 | regulator-always-on; | |
438 | anatop-reg-offset = <0x140>; | |
439 | anatop-vol-bit-shift = <18>; | |
440 | anatop-vol-bit-width = <5>; | |
441 | anatop-min-bit-val = <1>; | |
442 | anatop-min-voltage = <725000>; | |
443 | anatop-max-voltage = <1450000>; | |
444 | }; | |
7d740f87 SG |
445 | }; |
446 | ||
447 | usbphy@020c9000 { /* USBPHY1 */ | |
448 | reg = <0x020c9000 0x1000>; | |
449 | interrupts = <0 44 0x04>; | |
450 | }; | |
451 | ||
452 | usbphy@020ca000 { /* USBPHY2 */ | |
453 | reg = <0x020ca000 0x1000>; | |
454 | interrupts = <0 45 0x04>; | |
455 | }; | |
456 | ||
457 | snvs@020cc000 { | |
458 | reg = <0x020cc000 0x4000>; | |
459 | interrupts = <0 19 0x04 0 20 0x04>; | |
460 | }; | |
461 | ||
462 | epit@020d0000 { /* EPIT1 */ | |
463 | reg = <0x020d0000 0x4000>; | |
464 | interrupts = <0 56 0x04>; | |
465 | }; | |
466 | ||
467 | epit@020d4000 { /* EPIT2 */ | |
468 | reg = <0x020d4000 0x4000>; | |
469 | interrupts = <0 57 0x04>; | |
470 | }; | |
471 | ||
472 | src@020d8000 { | |
473 | compatible = "fsl,imx6q-src"; | |
474 | reg = <0x020d8000 0x4000>; | |
475 | interrupts = <0 91 0x04 0 96 0x04>; | |
476 | }; | |
477 | ||
478 | gpc@020dc000 { | |
479 | compatible = "fsl,imx6q-gpc"; | |
480 | reg = <0x020dc000 0x4000>; | |
481 | interrupts = <0 89 0x04 0 90 0x04>; | |
482 | }; | |
483 | ||
484 | iomuxc@020e0000 { | |
551fd208 | 485 | compatible = "fsl,imx6q-iomuxc"; |
7d740f87 | 486 | reg = <0x020e0000 0x4000>; |
551fd208 DA |
487 | |
488 | /* shared pinctrl settings */ | |
489 | usdhc3 { | |
490 | pinctrl_usdhc3_1: usdhc3grp-1 { | |
491 | fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | |
492 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | |
493 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | |
494 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | |
495 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | |
496 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | |
497 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ | |
498 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ | |
499 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ | |
500 | 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ | |
501 | }; | |
502 | }; | |
503 | ||
504 | usdhc4 { | |
505 | pinctrl_usdhc4_1: usdhc4grp-1 { | |
506 | fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | |
507 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | |
508 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | |
509 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | |
510 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | |
511 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | |
512 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ | |
513 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ | |
514 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ | |
515 | 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | |
516 | }; | |
517 | }; | |
7d740f87 SG |
518 | }; |
519 | ||
520 | dcic@020e4000 { /* DCIC1 */ | |
521 | reg = <0x020e4000 0x4000>; | |
522 | interrupts = <0 124 0x04>; | |
523 | }; | |
524 | ||
525 | dcic@020e8000 { /* DCIC2 */ | |
526 | reg = <0x020e8000 0x4000>; | |
527 | interrupts = <0 125 0x04>; | |
528 | }; | |
529 | ||
530 | sdma@020ec000 { | |
531 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; | |
532 | reg = <0x020ec000 0x4000>; | |
533 | interrupts = <0 2 0x04>; | |
534 | }; | |
535 | }; | |
536 | ||
537 | aips-bus@02100000 { /* AIPS2 */ | |
538 | compatible = "fsl,aips-bus", "simple-bus"; | |
539 | #address-cells = <1>; | |
540 | #size-cells = <1>; | |
541 | reg = <0x02100000 0x100000>; | |
542 | ranges; | |
543 | ||
544 | caam@02100000 { | |
545 | reg = <0x02100000 0x40000>; | |
546 | interrupts = <0 105 0x04 0 106 0x04>; | |
547 | }; | |
548 | ||
549 | aipstz@0217c000 { /* AIPSTZ2 */ | |
550 | reg = <0x0217c000 0x4000>; | |
551 | }; | |
552 | ||
0c456cfa | 553 | ethernet@02188000 { |
7d740f87 SG |
554 | compatible = "fsl,imx6q-fec"; |
555 | reg = <0x02188000 0x4000>; | |
556 | interrupts = <0 118 0x04 0 119 0x04>; | |
557 | status = "disabled"; | |
558 | }; | |
559 | ||
560 | mlb@0218c000 { | |
561 | reg = <0x0218c000 0x4000>; | |
562 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; | |
563 | }; | |
564 | ||
565 | usdhc@02190000 { /* uSDHC1 */ | |
566 | compatible = "fsl,imx6q-usdhc"; | |
567 | reg = <0x02190000 0x4000>; | |
568 | interrupts = <0 22 0x04>; | |
569 | status = "disabled"; | |
570 | }; | |
571 | ||
572 | usdhc@02194000 { /* uSDHC2 */ | |
573 | compatible = "fsl,imx6q-usdhc"; | |
574 | reg = <0x02194000 0x4000>; | |
575 | interrupts = <0 23 0x04>; | |
576 | status = "disabled"; | |
577 | }; | |
578 | ||
579 | usdhc@02198000 { /* uSDHC3 */ | |
580 | compatible = "fsl,imx6q-usdhc"; | |
581 | reg = <0x02198000 0x4000>; | |
582 | interrupts = <0 24 0x04>; | |
583 | status = "disabled"; | |
584 | }; | |
585 | ||
586 | usdhc@0219c000 { /* uSDHC4 */ | |
587 | compatible = "fsl,imx6q-usdhc"; | |
588 | reg = <0x0219c000 0x4000>; | |
589 | interrupts = <0 25 0x04>; | |
590 | status = "disabled"; | |
591 | }; | |
592 | ||
593 | i2c@021a0000 { /* I2C1 */ | |
594 | #address-cells = <1>; | |
595 | #size-cells = <0>; | |
596 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | |
597 | reg = <0x021a0000 0x4000>; | |
598 | interrupts = <0 36 0x04>; | |
599 | status = "disabled"; | |
600 | }; | |
601 | ||
602 | i2c@021a4000 { /* I2C2 */ | |
603 | #address-cells = <1>; | |
604 | #size-cells = <0>; | |
605 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | |
606 | reg = <0x021a4000 0x4000>; | |
607 | interrupts = <0 37 0x04>; | |
608 | status = "disabled"; | |
609 | }; | |
610 | ||
611 | i2c@021a8000 { /* I2C3 */ | |
612 | #address-cells = <1>; | |
613 | #size-cells = <0>; | |
614 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | |
615 | reg = <0x021a8000 0x4000>; | |
616 | interrupts = <0 38 0x04>; | |
617 | status = "disabled"; | |
618 | }; | |
619 | ||
620 | romcp@021ac000 { | |
621 | reg = <0x021ac000 0x4000>; | |
622 | }; | |
623 | ||
624 | mmdc@021b0000 { /* MMDC0 */ | |
625 | compatible = "fsl,imx6q-mmdc"; | |
626 | reg = <0x021b0000 0x4000>; | |
627 | }; | |
628 | ||
629 | mmdc@021b4000 { /* MMDC1 */ | |
630 | reg = <0x021b4000 0x4000>; | |
631 | }; | |
632 | ||
633 | weim@021b8000 { | |
634 | reg = <0x021b8000 0x4000>; | |
635 | interrupts = <0 14 0x04>; | |
636 | }; | |
637 | ||
638 | ocotp@021bc000 { | |
639 | reg = <0x021bc000 0x4000>; | |
640 | }; | |
641 | ||
642 | ocotp@021c0000 { | |
643 | reg = <0x021c0000 0x4000>; | |
644 | interrupts = <0 21 0x04>; | |
645 | }; | |
646 | ||
647 | tzasc@021d0000 { /* TZASC1 */ | |
648 | reg = <0x021d0000 0x4000>; | |
649 | interrupts = <0 108 0x04>; | |
650 | }; | |
651 | ||
652 | tzasc@021d4000 { /* TZASC2 */ | |
653 | reg = <0x021d4000 0x4000>; | |
654 | interrupts = <0 109 0x04>; | |
655 | }; | |
656 | ||
657 | audmux@021d8000 { | |
f965cd55 | 658 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 659 | reg = <0x021d8000 0x4000>; |
f965cd55 | 660 | status = "disabled"; |
7d740f87 SG |
661 | }; |
662 | ||
663 | mipi@021dc000 { /* MIPI-CSI */ | |
664 | reg = <0x021dc000 0x4000>; | |
665 | }; | |
666 | ||
667 | mipi@021e0000 { /* MIPI-DSI */ | |
668 | reg = <0x021e0000 0x4000>; | |
669 | }; | |
670 | ||
671 | vdoa@021e4000 { | |
672 | reg = <0x021e4000 0x4000>; | |
673 | interrupts = <0 18 0x04>; | |
674 | }; | |
675 | ||
0c456cfa | 676 | uart2: serial@021e8000 { |
7d740f87 SG |
677 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
678 | reg = <0x021e8000 0x4000>; | |
679 | interrupts = <0 27 0x04>; | |
680 | status = "disabled"; | |
681 | }; | |
682 | ||
0c456cfa | 683 | uart3: serial@021ec000 { |
7d740f87 SG |
684 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
685 | reg = <0x021ec000 0x4000>; | |
686 | interrupts = <0 28 0x04>; | |
687 | status = "disabled"; | |
688 | }; | |
689 | ||
0c456cfa | 690 | uart4: serial@021f0000 { |
7d740f87 SG |
691 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
692 | reg = <0x021f0000 0x4000>; | |
693 | interrupts = <0 29 0x04>; | |
694 | status = "disabled"; | |
695 | }; | |
696 | ||
0c456cfa | 697 | uart5: serial@021f4000 { |
7d740f87 SG |
698 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
699 | reg = <0x021f4000 0x4000>; | |
700 | interrupts = <0 30 0x04>; | |
701 | status = "disabled"; | |
702 | }; | |
703 | }; | |
704 | }; | |
705 | }; |