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ARM: dts: imx: ventana: add PWM nodes for Ventana boards
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl-gw52xx.dtsi
CommitLineData
e3946fe8
TH		 1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
326cdb16
TH		 12#include <dt-bindings/gpio/gpio.h>
13
e3946fe8
TH		 14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
e3946fe8
TH		 17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 ssi0 = &ssi1;
22 usb0 = &usbh1;
23 usb1 = &usbotg;
e3946fe8
TH		 24 };
25
26 chosen {
27 bootargs = "console=ttymxc1,115200";
28 };
29
b3253241
TH		 30 backlight {
31 compatible = "pwm-backlight";
32 pwms = <&pwm4 0 5000000>;
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <7>;
35 };
36
e3946fe8
TH		 37 leds {
38 compatible = "gpio-leds";
b5f37b76
TH		 39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
e3946fe8
TH		 41
42 led0: user1 {
43 label = "user1";
326cdb16 44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
e3946fe8
TH		 45 default-state = "on";
46 linux,default-trigger = "heartbeat";
47 };
48
49 led1: user2 {
50 label = "user2";
326cdb16 51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
e3946fe8
TH		 52 default-state = "off";
53 };
54
55 led2: user3 {
56 label = "user3";
326cdb16 57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
e3946fe8
TH		 58 default-state = "off";
59 };
60 };
61
62 memory {
63 reg = <0x10000000 0x20000000>;
64 };
65
66 pps {
67 compatible = "pps-gpio";
b5f37b76
TH		 68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
326cdb16 70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
e3946fe8
TH		 71 status = "okay";
72 };
73
74 regulators {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 reg_1p0v: regulator@0 {
80 compatible = "regulator-fixed";
81 reg = <0>;
82 regulator-name = "1P0V";
83 regulator-min-microvolt = <1000000>;
84 regulator-max-microvolt = <1000000>;
85 regulator-always-on;
86 };
87
88 /* remove this fixed regulator once ltc3676__sw2 driver available */
89 reg_1p8v: regulator@1 {
90 compatible = "regulator-fixed";
91 reg = <1>;
92 regulator-name = "1P8V";
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
95 regulator-always-on;
96 };
97
98 reg_3p3v: regulator@2 {
99 compatible = "regulator-fixed";
100 reg = <2>;
101 regulator-name = "3P3V";
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 regulator-always-on;
105 };
106
107 reg_5p0v: regulator@3 {
108 compatible = "regulator-fixed";
109 reg = <3>;
110 regulator-name = "5P0V";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 regulator-always-on;
114 };
115
116 reg_usb_otg_vbus: regulator@4 {
117 compatible = "regulator-fixed";
118 reg = <4>;
119 regulator-name = "usb_otg_vbus";
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5000000>;
326cdb16 122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
e3946fe8
TH		 123 enable-active-high;
124 };
125 };
126
127 sound {
b12d1e94 128 compatible = "fsl,imx6q-ventana-sgtl5000",
e3946fe8 129 "fsl,imx-audio-sgtl5000";
b12d1e94 130 model = "sgtl5000-audio";
e3946fe8
TH		 131 ssi-controller = <&ssi1>;
132 audio-codec = <&codec>;
133 audio-routing =
134 "MIC_IN", "Mic Jack",
135 "Mic Jack", "Mic Bias",
136 "Headphone Jack", "HP_OUT";
137 mux-int-port = <1>;
138 mux-ext-port = <4>;
139 };
140};
141
142&audmux {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_audmux>;
145 status = "okay";
146};
147
7cab35c3
TH		 148&can1 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_flexcan1>;
151 status = "okay";
152};
153
e726a9fd
TH		 154&clks {
155 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
156 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
157 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
158 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
159};
160
e3946fe8
TH		 161&fec {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_enet>;
3a35e470 164 phy-mode = "rgmii-id";
326cdb16 165 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
e3946fe8
TH		 166 status = "okay";
167};
168
169&gpmi {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_gpmi_nand>;
172 status = "okay";
173};
174
aef15dba
TH		 175&hdmi {
176 ddc-i2c-bus = <&i2c3>;
177 status = "okay";
178};
179
e3946fe8
TH		 180&i2c1 {
181 clock-frequency = <100000>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_i2c1>;
184 status = "okay";
185
186 eeprom1: eeprom@50 {
187 compatible = "atmel,24c02";
188 reg = <0x50>;
189 pagesize = <16>;
190 };
191
192 eeprom2: eeprom@51 {
193 compatible = "atmel,24c02";
194 reg = <0x51>;
195 pagesize = <16>;
196 };
197
198 eeprom3: eeprom@52 {
199 compatible = "atmel,24c02";
200 reg = <0x52>;
201 pagesize = <16>;
202 };
203
204 eeprom4: eeprom@53 {
205 compatible = "atmel,24c02";
206 reg = <0x53>;
207 pagesize = <16>;
208 };
209
210 gpio: pca9555@23 {
211 compatible = "nxp,pca9555";
212 reg = <0x23>;
213 gpio-controller;
214 #gpio-cells = <2>;
215 };
216
e3946fe8
TH		 217 rtc: ds1672@68 {
218 compatible = "dallas,ds1672";
219 reg = <0x68>;
220 };
221};
222
223&i2c2 {
224 clock-frequency = <100000>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_i2c2>;
227 status = "okay";
e3946fe8
TH		 228};
229
230&i2c3 {
231 clock-frequency = <100000>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_i2c3>;
234 status = "okay";
235
e3946fe8
TH		 236 codec: sgtl5000@0a {
237 compatible = "fsl,sgtl5000";
238 reg = <0x0a>;
5b4c180a 239 clocks = <&clks 201>;
e3946fe8
TH		 240 VDDA-supply = <&reg_1p8v>;
241 VDDIO-supply = <&reg_3p3v>;
242 };
243
244 touchscreen: egalax_ts@04 {
245 compatible = "eeti,egalax_ts";
246 reg = <0x04>;
247 interrupt-parent = <&gpio7>;
326cdb16
TH		 248 interrupts = <12 2>;
249 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
e3946fe8 250 };
e3946fe8
TH		 251};
252
b5f37b76
TH		 253&ldb {
254 status = "okay";
e3946fe8 255
b5f37b76
TH		 256 lvds-channel@0 {
257 fsl,data-mapping = "spwg";
258 fsl,data-width = <18>;
259 status = "okay";
260
261 display-timings {
262 native-mode = <&timing0>;
263 timing0: hsd100pxn1 {
264 clock-frequency = <65000000>;
265 hactive = <1024>;
266 vactive = <768>;
267 hback-porch = <220>;
268 hfront-porch = <40>;
269 vback-porch = <21>;
270 vfront-porch = <7>;
271 hsync-len = <60>;
272 vsync-len = <10>;
273 };
e3946fe8 274 };
b5f37b76
TH		 275 };
276};
277
278&pcie {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_pcie>;
281 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
282 status = "okay";
283};
284
aa2b2178
TH		 285&pwm2 {
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
288 status = "disabled";
289};
290
291&pwm3 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
294 status = "disabled";
295};
296
b5f37b76
TH		 297&pwm4 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_pwm4>;
300 status = "okay";
301};
302
303&ssi1 {
b5f37b76
TH		 304 status = "okay";
305};
306
307&uart1 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_uart1>;
310 status = "okay";
311};
312
313&uart2 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_uart2>;
316 status = "okay";
317};
e3946fe8 318
b5f37b76
TH		 319&uart5 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_uart5>;
322 status = "okay";
323};
324
325&usbotg {
326 vbus-supply = <&reg_usb_otg_vbus>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_usbotg>;
329 disable-over-current;
330 status = "okay";
331};
332
333&usbh1 {
334 status = "okay";
335};
336
337&usdhc3 {
3ee12d80 338 pinctrl-names = "default", "state_100mhz", "state_200mhz";
b5f37b76 339 pinctrl-0 = <&pinctrl_usdhc3>;
3ee12d80
TH		 340 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
341 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
89c1a8cf 342 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
b5f37b76 343 vmmc-supply = <&reg_3p3v>;
3ee12d80 344 no-1-8-v; /* firmware will remove if board revision supports */
b5f37b76
TH		 345 status = "okay";
346};
347
348&iomuxc {
349 imx6qdl-gw52xx {
e3946fe8
TH		 350 pinctrl_audmux: audmuxgrp {
351 fsl,pins = <
352 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
353 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
354 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
355 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
b5f37b76 356 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
e3946fe8
TH		 357 >;
358 };
359
360 pinctrl_enet: enetgrp {
361 fsl,pins = <
362 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
363 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
364 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
365 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
366 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
367 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
368 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
369 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
370 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
371 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
372 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
373 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
374 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
375 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
376 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
377 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
b5f37b76
TH		 378 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
379 >;
380 };
381
7cab35c3
TH		 382 pinctrl_flexcan1: flexcan1grp {
383 fsl,pins = <
384 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
385 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
386 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
387 >;
388 };
389
b5f37b76
TH		 390 pinctrl_gpio_leds: gpioledsgrp {
391 fsl,pins = <
392 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
393 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
394 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
e3946fe8
TH		 395 >;
396 };
397
398 pinctrl_gpmi_nand: gpminandgrp {
399 fsl,pins = <
400 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
401 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
402 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
403 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
404 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
e3946fe8
TH		 405 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
406 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
407 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
408 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
409 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
410 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
411 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
412 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
413 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
414 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
415 >;
416 };
417
418 pinctrl_i2c1: i2c1grp {
419 fsl,pins = <
420 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
421 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
422 >;
423 };
424
425 pinctrl_i2c2: i2c2grp {
426 fsl,pins = <
427 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
428 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
429 >;
430 };
431
432 pinctrl_i2c3: i2c3grp {
433 fsl,pins = <
434 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
435 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
436 >;
437 };
438
b5f37b76
TH		 439 pinctrl_pcie: pciegrp {
440 fsl,pins = <
441 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
442 >;
443 };
444
445 pinctrl_pps: ppsgrp {
446 fsl,pins = <
447 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
448 >;
449 };
450
aa2b2178
TH		 451 pinctrl_pwm2: pwm2grp {
452 fsl,pins = <
453 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
454 >;
455 };
456
457 pinctrl_pwm3: pwm3grp {
458 fsl,pins = <
459 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
460 >;
461 };
462
b3253241
TH		 463 pinctrl_pwm4: pwm4grp {
464 fsl,pins = <
465 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
466 >;
467 };
468
e3946fe8
TH		 469 pinctrl_uart1: uart1grp {
470 fsl,pins = <
471 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
472 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
473 >;
474 };
475
476 pinctrl_uart2: uart2grp {
477 fsl,pins = <
478 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
479 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
480 >;
481 };
482
483 pinctrl_uart5: uart5grp {
484 fsl,pins = <
485 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
486 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
487 >;
488 };
489
490 pinctrl_usbotg: usbotggrp {
491 fsl,pins = <
492 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
b5f37b76 493 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
e3946fe8
TH		 494 >;
495 };
496
497 pinctrl_usdhc3: usdhc3grp {
498 fsl,pins = <
499 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
500 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
501 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
502 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
503 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
504 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
3ee12d80
TH		 505 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
506 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
507 >;
508 };
509
510 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
511 fsl,pins = <
512 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
513 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
514 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
515 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
516 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
517 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
518 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
519 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
520 >;
521 };
522
523 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
524 fsl,pins = <
525 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
526 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
527 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
528 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
529 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
530 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
531 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
532 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
e3946fe8
TH		 533 >;
534 };
535 };
536};
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