[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl-sabreauto.dtsi

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	memory {
		reg = <0x10000000 0x80000000>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		user {
			label = "debug";
			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
		};
	};

	clocks {
		codec_osc: anaclk2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24576000>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_audio: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "cs42888_supply";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		reg_usb_h1_vbus: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "usb_h1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg_vbus: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "usb_otg_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};

	sound-cs42888 {
		compatible = "fsl,imx6-sabreauto-cs42888",
			"fsl,imx-audio-cs42888";
		model = "imx-cs42888";
		audio-cpu = <&esai>;
		audio-asrc = <&asrc>;
		audio-codec = <&codec>;
		audio-routing =
			"Line Out Jack", "AOUT1L",
			"Line Out Jack", "AOUT1R",
			"Line Out Jack", "AOUT2L",
			"Line Out Jack", "AOUT2R",
			"Line Out Jack", "AOUT3L",
			"Line Out Jack", "AOUT3R",
			"Line Out Jack", "AOUT4L",
			"Line Out Jack", "AOUT4R",
			"AIN1L", "Line In Jack",
			"AIN1R", "Line In Jack",
			"AIN2L", "Line In Jack",
			"AIN2R", "Line In Jack";
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif",
			   "fsl,imx-sabreauto-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-in;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
		status = "okay";
	};
};

&clks {
	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
			  <&clks IMX6QDL_PLL4_BYPASS>,
			  <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
};

&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio3 19 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
	status = "disabled"; /* pin conflict with WEIM NOR */

	flash: m25p80@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p32", "jedec,spi-nor";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&esai {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esai>;
	assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
			  <&clks IMX6QDL_CLK_ESAI_EXTAL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <24576000>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
	fsl,err006687-workaround-present;
	status = "okay";
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
};

&hdmi {
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic: pfuze100@08 {
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3b_reg: sw3b {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};

	codec: cs42888@48 {
		compatible = "cirrus,cs42888";
		reg = <0x48>;
		clocks = <&codec_osc>;
		clock-names = "mclk";
		VA-supply = <&reg_audio>;
		VD-supply = <&reg_audio>;
		VLS-supply = <&reg_audio>;
		VLC-supply = <&reg_audio>;
        };

};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	max7310_a: gpio@30 {
		compatible = "maxim,max7310";
		reg = <0x30>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	max7310_b: gpio@32 {
		compatible = "maxim,max7310";
		reg = <0x32>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	max7310_c: gpio@34 {
		compatible = "maxim,max7310";
		reg = <0x34>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx6qdl-sabreauto {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
			>;
		};

		pinctrl_ecspi1_cs: ecspi1cs {
			fsl,pins = <
				MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
			>;
		};

		pinctrl_esai: esaigrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
				MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
				MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
				MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
				MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
				MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
				MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
				MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
				MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
				MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
			>;
		};

		pinctrl_gpio_leds: gpioledsgrp {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x80000000
			>;
		};

		pinctrl_gpmi_nand: gpminandgrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
				MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
			>;
		};

		pinctrl_pwm3: pwm1grp {
			fsl,pins = <
				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
			>;
		};

		pinctrl_spdif: spdifgrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
			>;
		};

		pinctrl_uart4: uart4grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
			>;
		};

		pinctrl_weim_cs0: weimcs0grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
			>;
		};

		pinctrl_weim_nor: weimnorgrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
				MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
				MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B		0xb060
				MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
				MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
				MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
				MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
				MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
				MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
				MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
				MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
				MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
				MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
				MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
				MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
				MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
				MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
				MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
				MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
				MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
				MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
				MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
				MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
				MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
				MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
				MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
				MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
				MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
				MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
				MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
				MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
				MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
				MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
				MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
				MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
				MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
				MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
				MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
				MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
				MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
				MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
				MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
				MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
			>;
		};
	};
};

&ldb {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "okay";

		display-timings {
			native-mode = <&timing0>;
			timing0: hsd100pxn1 {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_usb_h1_vbus>;
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x08000000 0x08000000>;
	status = "disabled"; /* pin conflict with SPI NOR */

	nor@0,0 {
		compatible = "cfi-flash";
		reg = <0 0 0x02000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		bank-width = <2>;
		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
				0x0000c000 0x1404a38e 0x00000000>;
	};
};
Commit	Line	Data
082d33d0 SG	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
35346b22 LY	13	#include <dt-bindings/gpio/gpio.h>
35346b22 LY	14
082d33d0 SG	15	/ {
	16	memory {
	17	reg = <0x10000000 0x80000000>;
	18	};
1169cf1f	19
35346b22 LY	20	leds {
	21	compatible = "gpio-leds";
	22	pinctrl-names = "default";
	23	pinctrl-0 = <&pinctrl_gpio_leds>;
	24
	25	user {
	26	label = "debug";
	27	gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
	28	};
	29	};
	30
97dae859 SW	31	clocks {
	32	codec_osc: anaclk2 {
	33	compatible = "fixed-clock";
	34	#clock-cells = <0>;
	35	clock-frequency = <24576000>;
	36	};
	37	};
	38
	39	regulators {
	40	compatible = "simple-bus";
	41	#address-cells = <1>;
	42	#size-cells = <0>;
	43
	44	reg_audio: regulator@0 {
	45	compatible = "regulator-fixed";
	46	reg = <0>;
	47	regulator-name = "cs42888_supply";
	48	regulator-min-microvolt = <3300000>;
	49	regulator-max-microvolt = <3300000>;
	50	regulator-always-on;
	51	};
0f92fd49 PC	52
	53	reg_usb_h1_vbus: regulator@1 {
	54	compatible = "regulator-fixed";
	55	reg = <1>;
	56	regulator-name = "usb_h1_vbus";
	57	regulator-min-microvolt = <5000000>;
	58	regulator-max-microvolt = <5000000>;
	59	gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
	60	enable-active-high;
	61	};
	62
	63	reg_usb_otg_vbus: regulator@2 {
	64	compatible = "regulator-fixed";
	65	reg = <2>;
	66	regulator-name = "usb_otg_vbus";
	67	regulator-min-microvolt = <5000000>;
	68	regulator-max-microvolt = <5000000>;
	69	gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
	70	enable-active-high;
	71	};
97dae859 SW	72	};
	73
	74	sound-cs42888 {
	75	compatible = "fsl,imx6-sabreauto-cs42888",
	76	"fsl,imx-audio-cs42888";
	77	model = "imx-cs42888";
	78	audio-cpu = <&esai>;
	79	audio-asrc = <&asrc>;
	80	audio-codec = <&codec>;
	81	audio-routing =
	82	"Line Out Jack", "AOUT1L",
	83	"Line Out Jack", "AOUT1R",
	84	"Line Out Jack", "AOUT2L",
	85	"Line Out Jack", "AOUT2R",
	86	"Line Out Jack", "AOUT3L",
	87	"Line Out Jack", "AOUT3R",
	88	"Line Out Jack", "AOUT4L",
	89	"Line Out Jack", "AOUT4R",
	90	"AIN1L", "Line In Jack",
	91	"AIN1R", "Line In Jack",
	92	"AIN2L", "Line In Jack",
	93	"AIN2R", "Line In Jack";
	94	};
	95
1169cf1f NC	96	sound-spdif {
	97	compatible = "fsl,imx-audio-spdif",
	98	"fsl,imx-sabreauto-spdif";
	99	model = "imx-spdif";
	100	spdif-controller = <&spdif>;
	101	spdif-in;
	102	};
c0f16624 FE	103
	104	backlight {
	105	compatible = "pwm-backlight";
	106	pwms = <&pwm3 0 5000000>;
	107	brightness-levels = <0 4 8 16 32 64 128 255>;
	108	default-brightness-level = <7>;
	109	status = "okay";
	110	};
082d33d0 SG	111	};
082d33d0 SG	112
97dae859 SW	113	&clks {
	114	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
	115	<&clks IMX6QDL_PLL4_BYPASS>,
ed339363	116	<&clks IMX6QDL_CLK_LDB_DI0_SEL>,
13fdae1a BP	117	<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
13fdae1a BP	118	<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
97dae859	119	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
ed339363 FE	120	<&clks IMX6QDL_PLL4_BYPASS_SRC>,
	121	<&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	122	<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
13fdae1a	123	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
97dae859 SW	124	};
97dae859 SW	125
faacc290 HS	126	&ecspi1 {
	127	fsl,spi-num-chipselects = <1>;
	128	cs-gpios = <&gpio3 19 0>;
	129	pinctrl-names = "default";
817c27a1	130	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
faacc290 HS	131	status = "disabled"; /* pin conflict with WEIM NOR */
	132
	133	flash: m25p80@0 {
	134	#address-cells = <1>;
	135	#size-cells = <1>;
79826ac6	136	compatible = "st,m25p32", "jedec,spi-nor";
faacc290 HS	137	spi-max-frequency = <20000000>;
	138	reg = <0>;
	139	};
	140	};
	141
97dae859 SW	142	&esai {
	143	pinctrl-names = "default";
	144	pinctrl-0 = <&pinctrl_esai>;
	145	assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
	146	<&clks IMX6QDL_CLK_ESAI_EXTAL>;
	147	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
	148	assigned-clock-rates = <0>, <24576000>;
	149	status = "okay";
	150	};
	151
082d33d0 SG	152	&fec {
082d33d0 SG	153	pinctrl-names = "default";
817c27a1	154	pinctrl-0 = <&pinctrl_enet>;
082d33d0	155	phy-mode = "rgmii";
bc20a5d6 TK	156	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
bc20a5d6 TK	157	<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
a28eeb43	158	fsl,err006687-workaround-present;
082d33d0 SG	159	status = "okay";
	160	};
	161
82726931 HS	162	&gpmi {
82726931 HS	163	pinctrl-names = "default";
817c27a1	164	pinctrl-0 = <&pinctrl_gpmi_nand>;
82726931 HS	165	status = "okay";
	166	};
	167
1906c21a FE	168	&hdmi {
	169	status = "okay";
	170	};
	171
44659021 FE	172	&i2c2 {
	173	clock-frequency = <100000>;
	174	pinctrl-names = "default";
	175	pinctrl-0 = <&pinctrl_i2c2>;
	176	status = "okay";
	177
	178	pmic: pfuze100@08 {
	179	compatible = "fsl,pfuze100";
	180	reg = <0x08>;
	181
	182	regulators {
	183	sw1a_reg: sw1ab {
	184	regulator-min-microvolt = <300000>;
	185	regulator-max-microvolt = <1875000>;
	186	regulator-boot-on;
	187	regulator-always-on;
	188	regulator-ramp-delay = <6250>;
	189	};
	190
	191	sw1c_reg: sw1c {
	192	regulator-min-microvolt = <300000>;
	193	regulator-max-microvolt = <1875000>;
	194	regulator-boot-on;
	195	regulator-always-on;
	196	regulator-ramp-delay = <6250>;
	197	};
	198
	199	sw2_reg: sw2 {
	200	regulator-min-microvolt = <800000>;
	201	regulator-max-microvolt = <3300000>;
	202	regulator-boot-on;
	203	regulator-always-on;
	204	};
	205
	206	sw3a_reg: sw3a {
	207	regulator-min-microvolt = <400000>;
	208	regulator-max-microvolt = <1975000>;
	209	regulator-boot-on;
	210	regulator-always-on;
	211	};
	212
	213	sw3b_reg: sw3b {
	214	regulator-min-microvolt = <400000>;
	215	regulator-max-microvolt = <1975000>;
	216	regulator-boot-on;
	217	regulator-always-on;
	218	};
	219
	220	sw4_reg: sw4 {
	221	regulator-min-microvolt = <800000>;
	222	regulator-max-microvolt = <3300000>;
	223	};
	224
	225	swbst_reg: swbst {
	226	regulator-min-microvolt = <5000000>;
	227	regulator-max-microvolt = <5150000>;
	228	};
	229
	230	snvs_reg: vsnvs {
	231	regulator-min-microvolt = <1000000>;
	232	regulator-max-microvolt = <3000000>;
	233	regulator-boot-on;
	234	regulator-always-on;
	235	};
236
237	vref_reg: vrefddr {
238	regulator-boot-on;
239	regulator-always-on;
240	};
241
242	vgen1_reg: vgen1 {
243	regulator-min-microvolt = <800000>;
244	regulator-max-microvolt = <1550000>;
245	};
246
247	vgen2_reg: vgen2 {
248	regulator-min-microvolt = <800000>;
249	regulator-max-microvolt = <1550000>;
250	};
251
252	vgen3_reg: vgen3 {
253	regulator-min-microvolt = <1800000>;
254	regulator-max-microvolt = <3300000>;
255	};
256
257	vgen4_reg: vgen4 {
258	regulator-min-microvolt = <1800000>;
259	regulator-max-microvolt = <3300000>;
260	regulator-always-on;
261	};
262
263	vgen5_reg: vgen5 {
264	regulator-min-microvolt = <1800000>;
265	regulator-max-microvolt = <3300000>;
266	regulator-always-on;
267	};
268
269	vgen6_reg: vgen6 {
270	regulator-min-microvolt = <1800000>;
271	regulator-max-microvolt = <3300000>;
272	regulator-always-on;
273	};
274	};
275	};
97dae859 SW	276
	277	codec: cs42888@48 {
	278	compatible = "cirrus,cs42888";
	279	reg = <0x48>;
	280	clocks = <&codec_osc>;
	281	clock-names = "mclk";
	282	VA-supply = <&reg_audio>;
	283	VD-supply = <&reg_audio>;
	284	VLS-supply = <&reg_audio>;
	285	VLC-supply = <&reg_audio>;
	286	};
	287
44659021 FE	288	};
44659021 FE	289
4e18a224 PC	290	&i2c3 {
	291	pinctrl-names = "default";
	292	pinctrl-0 = <&pinctrl_i2c3>;
4e18a224 PC	293	status = "okay";
	294
	295	max7310_a: gpio@30 {
	296	compatible = "maxim,max7310";
	297	reg = <0x30>;
	298	gpio-controller;
	299	#gpio-cells = <2>;
	300	};
	301
	302	max7310_b: gpio@32 {
	303	compatible = "maxim,max7310";
	304	reg = <0x32>;
	305	gpio-controller;
	306	#gpio-cells = <2>;
	307	};
	308
	309	max7310_c: gpio@34 {
	310	compatible = "maxim,max7310";
	311	reg = <0x34>;
	312	gpio-controller;
	313	#gpio-cells = <2>;
	314	};
	315	};
	316
c56009b2 SG	317	&iomuxc {
	318	pinctrl-names = "default";
	319	pinctrl-0 = <&pinctrl_hog>;
	320
817c27a1	321	imx6qdl-sabreauto {
c56009b2 SG	322	pinctrl_hog: hoggrp {
	323	fsl,pins = <
	324	MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
	325	MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
93e2ca02	326	MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
c56009b2 SG	327	>;
c56009b2 SG	328	};
c56009b2	329
817c27a1 SG	330	pinctrl_ecspi1: ecspi1grp {
	331	fsl,pins = <
	332	MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	333	MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	334	MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
	335	>;
	336	};
	337
	338	pinctrl_ecspi1_cs: ecspi1cs {
c56009b2 SG	339	fsl,pins = <
	340	MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
	341	>;
	342	};
817c27a1 SG	343
	344	pinctrl_enet: enetgrp {
	345	fsl,pins = <
	346	MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
	347	MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
	348	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
	349	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
	350	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
	351	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
	352	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
	353	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
	354	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	355	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
	356	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
	357	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
	358	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
	359	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
	360	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
bc20a5d6	361	MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
817c27a1 SG	362	>;
	363	};
	364
97dae859 SW	365	pinctrl_esai: esaigrp {
	366	fsl,pins = <
	367	MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
	368	MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
	369	MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
	370	MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
	371	MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
	372	MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
	373	MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
	374	MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
	375	MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
	376	MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
	377	>;
	378	};
	379
35346b22 LY	380	pinctrl_gpio_leds: gpioledsgrp {
	381	fsl,pins = <
	382	MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
	383	>;
	384	};
	385
817c27a1 SG	386	pinctrl_gpmi_nand: gpminandgrp {
	387	fsl,pins = <
	388	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	389	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	390	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	391	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	392	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	393	MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
	394	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	395	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	396	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	397	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	398	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	399	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	400	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	401	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	402	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	403	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	404	MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
	405	>;
	406	};
	407
44659021 FE	408	pinctrl_i2c2: i2c2grp {
	409	fsl,pins = <
	410	MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
	411	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	412	>;
	413	};
	414
4e18a224 PC	415	pinctrl_i2c3: i2c3grp {
	416	fsl,pins = <
	417	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	418	MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	419	>;
	420	};
	421
c0f16624 FE	422	pinctrl_pwm3: pwm1grp {
	423	fsl,pins = <
	424	MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	425	>;
	426	};
	427
1169cf1f NC	428	pinctrl_spdif: spdifgrp {
	429	fsl,pins = <
	430	MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
	431	>;
	432	};
	433
817c27a1 SG	434	pinctrl_uart4: uart4grp {
	435	fsl,pins = <
	436	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	437	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	438	>;
	439	};
	440
0f92fd49 PC	441	pinctrl_usbotg: usbotggrp {
	442	fsl,pins = <
	443	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	444	>;
	445	};
	446
817c27a1 SG	447	pinctrl_usdhc3: usdhc3grp {
	448	fsl,pins = <
	449	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	450	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	451	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	452	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	453	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	454	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	455	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
	456	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
	457	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
	458	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
	459	>;
	460	};
	461
	462	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	463	fsl,pins = <
	464	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	465	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
	466	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	467	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	468	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	469	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	470	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
	471	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
	472	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
	473	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
	474	>;
	475	};
	476
	477	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	478	fsl,pins = <
	479	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	480	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	481	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	482	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	483	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	484	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	485	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
	486	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
	487	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
	488	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
	489	>;
	490	};
	491
	492	pinctrl_weim_cs0: weimcs0grp {
	493	fsl,pins = <
	494	MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
	495	>;
	496	};
	497
	498	pinctrl_weim_nor: weimnorgrp {
	499	fsl,pins = <
	500	MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
	501	MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
	502	MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
	503	MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
	504	MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
	505	MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
	506	MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
	507	MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
	508	MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
	509	MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
	510	MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
511	MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
512	MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
513	MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
514	MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
515	MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
516	MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
517	MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
518	MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
519	MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
520	MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
521	MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
522	MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
523	MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
524	MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
525	MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
526	MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
527	MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
528	MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
529	MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
530	MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
531	MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
532	MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
533	MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
534	MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
535	MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
536	MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
537	MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
538	MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
539	MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
540	MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
541	MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
542	MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
543	>;
544	};
c56009b2 SG	545	};
	546	};
	547
c0f16624 FE	548	&ldb {
	549	status = "okay";
	550
	551	lvds-channel@0 {
	552	fsl,data-mapping = "spwg";
	553	fsl,data-width = <18>;
	554	status = "okay";
	555
	556	display-timings {
	557	native-mode = <&timing0>;
	558	timing0: hsd100pxn1 {
	559	clock-frequency = <65000000>;
	560	hactive = <1024>;
	561	vactive = <768>;
	562	hback-porch = <220>;
	563	hfront-porch = <40>;
	564	vback-porch = <21>;
	565	vfront-porch = <7>;
	566	hsync-len = <60>;
	567	vsync-len = <10>;
	568	};
	569	};
	570	};
	571	};
	572
	573	&pwm3 {
	574	pinctrl-names = "default";
	575	pinctrl-0 = <&pinctrl_pwm3>;
	576	status = "okay";
	577	};
	578
1169cf1f NC	579	&spdif {
	580	pinctrl-names = "default";
	581	pinctrl-0 = <&pinctrl_spdif>;
	582	status = "okay";
	583	};
	584
082d33d0 SG	585	&uart4 {
082d33d0 SG	586	pinctrl-names = "default";
817c27a1	587	pinctrl-0 = <&pinctrl_uart4>;
082d33d0 SG	588	status = "okay";
	589	};
	590
0f92fd49 PC	591	&usbh1 {
	592	vbus-supply = <&reg_usb_h1_vbus>;
	593	status = "okay";
	594	};
	595
	596	&usbotg {
	597	vbus-supply = <&reg_usb_otg_vbus>;
	598	pinctrl-names = "default";
	599	pinctrl-0 = <&pinctrl_usbotg>;
	600	status = "okay";
	601	};
	602
082d33d0	603	&usdhc3 {
93e2ca02	604	pinctrl-names = "default", "state_100mhz", "state_200mhz";
817c27a1 SG	605	pinctrl-0 = <&pinctrl_usdhc3>;
	606	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	607	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
89c1a8cf DA	608	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
89c1a8cf DA	609	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
082d33d0 SG	610	status = "okay";
082d33d0 SG	611	};
50fe0e90 HS	612
	613	&weim {
	614	pinctrl-names = "default";
817c27a1	615	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
50fe0e90 HS	616	#address-cells = <2>;
	617	#size-cells = <1>;
	618	ranges = <0 0 0x08000000 0x08000000>;
	619	status = "disabled"; /* pin conflict with SPI NOR */
	620
	621	nor@0,0 {
	622	compatible = "cfi-flash";
	623	reg = <0 0 0x02000000>;
	624	#address-cells = <1>;
	625	#size-cells = <1>;
	626	bank-width = <2>;
	627	fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
	628	0x0000c000 0x1404a38e 0x00000000>;
	629	};
	630	};