Commit | Line | Data |
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7d740f87 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
36dffd8f | 13 | #include "skeleton.dtsi" |
7d740f87 SG |
14 | |
15 | / { | |
16 | aliases { | |
5230f8fe SG |
17 | gpio0 = &gpio1; |
18 | gpio1 = &gpio2; | |
19 | gpio2 = &gpio3; | |
20 | gpio3 = &gpio4; | |
21 | gpio4 = &gpio5; | |
22 | gpio5 = &gpio6; | |
23 | gpio6 = &gpio7; | |
80fa0584 SH |
24 | i2c0 = &i2c1; |
25 | i2c1 = &i2c2; | |
26 | i2c2 = &i2c3; | |
27 | serial0 = &uart1; | |
28 | serial1 = &uart2; | |
29 | serial2 = &uart3; | |
30 | serial3 = &uart4; | |
31 | serial4 = &uart5; | |
32 | spi0 = &ecspi1; | |
33 | spi1 = &ecspi2; | |
34 | spi2 = &ecspi3; | |
35 | spi3 = &ecspi4; | |
7d740f87 SG |
36 | }; |
37 | ||
7d740f87 SG |
38 | intc: interrupt-controller@00a01000 { |
39 | compatible = "arm,cortex-a9-gic"; | |
40 | #interrupt-cells = <3>; | |
41 | #address-cells = <1>; | |
42 | #size-cells = <1>; | |
43 | interrupt-controller; | |
44 | reg = <0x00a01000 0x1000>, | |
45 | <0x00a00100 0x100>; | |
46 | }; | |
47 | ||
48 | clocks { | |
49 | #address-cells = <1>; | |
50 | #size-cells = <0>; | |
51 | ||
52 | ckil { | |
53 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
54 | clock-frequency = <32768>; | |
55 | }; | |
56 | ||
57 | ckih1 { | |
58 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
59 | clock-frequency = <0>; | |
60 | }; | |
61 | ||
62 | osc { | |
63 | compatible = "fsl,imx-osc", "fixed-clock"; | |
64 | clock-frequency = <24000000>; | |
65 | }; | |
66 | }; | |
67 | ||
68 | soc { | |
69 | #address-cells = <1>; | |
70 | #size-cells = <1>; | |
71 | compatible = "simple-bus"; | |
72 | interrupt-parent = <&intc>; | |
73 | ranges; | |
74 | ||
f30fb03d | 75 | dma_apbh: dma-apbh@00110000 { |
e5d0f9f5 HS |
76 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
77 | reg = <0x00110000 0x2000>; | |
f30fb03d SG |
78 | interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; |
79 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; | |
80 | #dma-cells = <1>; | |
81 | dma-channels = <4>; | |
0e87e043 | 82 | clocks = <&clks 106>; |
e5d0f9f5 HS |
83 | }; |
84 | ||
be4ccfce | 85 | gpmi: gpmi-nand@00112000 { |
0e87e043 SG |
86 | compatible = "fsl,imx6q-gpmi-nand"; |
87 | #address-cells = <1>; | |
88 | #size-cells = <1>; | |
89 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
90 | reg-names = "gpmi-nand", "bch"; | |
c7aa12a6 SG |
91 | interrupts = <0 15 0x04>; |
92 | interrupt-names = "bch"; | |
0e87e043 SG |
93 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
94 | <&clks 150>, <&clks 149>; | |
95 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
96 | "gpmi_bch_apb", "per1_bch"; | |
f30fb03d SG |
97 | dmas = <&dma_apbh 0>; |
98 | dma-names = "rx-tx"; | |
0e87e043 | 99 | status = "disabled"; |
cf922fa8 HS |
100 | }; |
101 | ||
7d740f87 | 102 | timer@00a00600 { |
58458e03 MZ |
103 | compatible = "arm,cortex-a9-twd-timer"; |
104 | reg = <0x00a00600 0x20>; | |
105 | interrupts = <1 13 0xf01>; | |
2bb4b70b | 106 | clocks = <&clks 15>; |
7d740f87 SG |
107 | }; |
108 | ||
109 | L2: l2-cache@00a02000 { | |
110 | compatible = "arm,pl310-cache"; | |
111 | reg = <0x00a02000 0x1000>; | |
112 | interrupts = <0 92 0x04>; | |
113 | cache-unified; | |
114 | cache-level = <2>; | |
5a5ca56e DB |
115 | arm,tag-latency = <4 2 3>; |
116 | arm,data-latency = <4 2 3>; | |
7d740f87 SG |
117 | }; |
118 | ||
3a57291f SC |
119 | pcie: pcie@0x01000000 { |
120 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
121 | reg = <0x01ffc000 0x4000>; /* DBI */ | |
122 | #address-cells = <3>; | |
123 | #size-cells = <2>; | |
124 | device_type = "pci"; | |
125 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ | |
126 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | |
127 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | |
128 | num-lanes = <1>; | |
129 | interrupts = <0 123 0x04>; | |
130 | clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; | |
131 | clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; | |
132 | status = "disabled"; | |
133 | }; | |
134 | ||
218abe6f DB |
135 | pmu { |
136 | compatible = "arm,cortex-a9-pmu"; | |
137 | interrupts = <0 94 0x04>; | |
138 | }; | |
139 | ||
7d740f87 SG |
140 | aips-bus@02000000 { /* AIPS1 */ |
141 | compatible = "fsl,aips-bus", "simple-bus"; | |
142 | #address-cells = <1>; | |
143 | #size-cells = <1>; | |
144 | reg = <0x02000000 0x100000>; | |
145 | ranges; | |
146 | ||
147 | spba-bus@02000000 { | |
148 | compatible = "fsl,spba-bus", "simple-bus"; | |
149 | #address-cells = <1>; | |
150 | #size-cells = <1>; | |
151 | reg = <0x02000000 0x40000>; | |
152 | ranges; | |
153 | ||
7b7d6727 | 154 | spdif: spdif@02004000 { |
c9d96df2 | 155 | compatible = "fsl,imx35-spdif"; |
7d740f87 SG |
156 | reg = <0x02004000 0x4000>; |
157 | interrupts = <0 52 0x04>; | |
c9d96df2 FE |
158 | dmas = <&sdma 14 18 0>, |
159 | <&sdma 15 18 0>; | |
160 | dma-names = "rx", "tx"; | |
161 | clocks = <&clks 197>, <&clks 3>, | |
162 | <&clks 197>, <&clks 107>, | |
163 | <&clks 0>, <&clks 118>, | |
164 | <&clks 62>, <&clks 139>, | |
165 | <&clks 0>; | |
166 | clock-names = "core", "rxtx0", | |
167 | "rxtx1", "rxtx2", | |
168 | "rxtx3", "rxtx4", | |
169 | "rxtx5", "rxtx6", | |
170 | "rxtx7"; | |
171 | status = "disabled"; | |
7d740f87 SG |
172 | }; |
173 | ||
7b7d6727 | 174 | ecspi1: ecspi@02008000 { |
7d740f87 SG |
175 | #address-cells = <1>; |
176 | #size-cells = <0>; | |
177 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
178 | reg = <0x02008000 0x4000>; | |
179 | interrupts = <0 31 0x04>; | |
0e87e043 SG |
180 | clocks = <&clks 112>, <&clks 112>; |
181 | clock-names = "ipg", "per"; | |
7d740f87 SG |
182 | status = "disabled"; |
183 | }; | |
184 | ||
7b7d6727 | 185 | ecspi2: ecspi@0200c000 { |
7d740f87 SG |
186 | #address-cells = <1>; |
187 | #size-cells = <0>; | |
188 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
189 | reg = <0x0200c000 0x4000>; | |
190 | interrupts = <0 32 0x04>; | |
0e87e043 SG |
191 | clocks = <&clks 113>, <&clks 113>; |
192 | clock-names = "ipg", "per"; | |
7d740f87 SG |
193 | status = "disabled"; |
194 | }; | |
195 | ||
7b7d6727 | 196 | ecspi3: ecspi@02010000 { |
7d740f87 SG |
197 | #address-cells = <1>; |
198 | #size-cells = <0>; | |
199 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
200 | reg = <0x02010000 0x4000>; | |
201 | interrupts = <0 33 0x04>; | |
0e87e043 SG |
202 | clocks = <&clks 114>, <&clks 114>; |
203 | clock-names = "ipg", "per"; | |
7d740f87 SG |
204 | status = "disabled"; |
205 | }; | |
206 | ||
7b7d6727 | 207 | ecspi4: ecspi@02014000 { |
7d740f87 SG |
208 | #address-cells = <1>; |
209 | #size-cells = <0>; | |
210 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
211 | reg = <0x02014000 0x4000>; | |
212 | interrupts = <0 34 0x04>; | |
0e87e043 SG |
213 | clocks = <&clks 115>, <&clks 115>; |
214 | clock-names = "ipg", "per"; | |
7d740f87 SG |
215 | status = "disabled"; |
216 | }; | |
217 | ||
0c456cfa | 218 | uart1: serial@02020000 { |
7d740f87 SG |
219 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
220 | reg = <0x02020000 0x4000>; | |
221 | interrupts = <0 26 0x04>; | |
0e87e043 SG |
222 | clocks = <&clks 160>, <&clks 161>; |
223 | clock-names = "ipg", "per"; | |
72a5cebf HS |
224 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
225 | dma-names = "rx", "tx"; | |
7d740f87 SG |
226 | status = "disabled"; |
227 | }; | |
228 | ||
7b7d6727 | 229 | esai: esai@02024000 { |
7d740f87 SG |
230 | reg = <0x02024000 0x4000>; |
231 | interrupts = <0 51 0x04>; | |
232 | }; | |
233 | ||
b1a5da8e RZ |
234 | ssi1: ssi@02028000 { |
235 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
236 | reg = <0x02028000 0x4000>; |
237 | interrupts = <0 46 0x04>; | |
0e87e043 | 238 | clocks = <&clks 178>; |
5da826ab SG |
239 | dmas = <&sdma 37 1 0>, |
240 | <&sdma 38 1 0>; | |
241 | dma-names = "rx", "tx"; | |
b1a5da8e RZ |
242 | fsl,fifo-depth = <15>; |
243 | fsl,ssi-dma-events = <38 37>; | |
244 | status = "disabled"; | |
7d740f87 SG |
245 | }; |
246 | ||
b1a5da8e RZ |
247 | ssi2: ssi@0202c000 { |
248 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
249 | reg = <0x0202c000 0x4000>; |
250 | interrupts = <0 47 0x04>; | |
0e87e043 | 251 | clocks = <&clks 179>; |
5da826ab SG |
252 | dmas = <&sdma 41 1 0>, |
253 | <&sdma 42 1 0>; | |
254 | dma-names = "rx", "tx"; | |
b1a5da8e RZ |
255 | fsl,fifo-depth = <15>; |
256 | fsl,ssi-dma-events = <42 41>; | |
257 | status = "disabled"; | |
7d740f87 SG |
258 | }; |
259 | ||
b1a5da8e RZ |
260 | ssi3: ssi@02030000 { |
261 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
262 | reg = <0x02030000 0x4000>; |
263 | interrupts = <0 48 0x04>; | |
0e87e043 | 264 | clocks = <&clks 180>; |
5da826ab SG |
265 | dmas = <&sdma 45 1 0>, |
266 | <&sdma 46 1 0>; | |
267 | dma-names = "rx", "tx"; | |
b1a5da8e RZ |
268 | fsl,fifo-depth = <15>; |
269 | fsl,ssi-dma-events = <46 45>; | |
270 | status = "disabled"; | |
7d740f87 SG |
271 | }; |
272 | ||
7b7d6727 | 273 | asrc: asrc@02034000 { |
7d740f87 SG |
274 | reg = <0x02034000 0x4000>; |
275 | interrupts = <0 50 0x04>; | |
276 | }; | |
277 | ||
278 | spba@0203c000 { | |
279 | reg = <0x0203c000 0x4000>; | |
280 | }; | |
281 | }; | |
282 | ||
7b7d6727 | 283 | vpu: vpu@02040000 { |
7d740f87 SG |
284 | reg = <0x02040000 0x3c000>; |
285 | interrupts = <0 3 0x04 0 12 0x04>; | |
286 | }; | |
287 | ||
288 | aipstz@0207c000 { /* AIPSTZ1 */ | |
289 | reg = <0x0207c000 0x4000>; | |
290 | }; | |
291 | ||
7b7d6727 | 292 | pwm1: pwm@02080000 { |
33b38587 SH |
293 | #pwm-cells = <2>; |
294 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
295 | reg = <0x02080000 0x4000>; |
296 | interrupts = <0 83 0x04>; | |
33b38587 SH |
297 | clocks = <&clks 62>, <&clks 145>; |
298 | clock-names = "ipg", "per"; | |
7d740f87 SG |
299 | }; |
300 | ||
7b7d6727 | 301 | pwm2: pwm@02084000 { |
33b38587 SH |
302 | #pwm-cells = <2>; |
303 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
304 | reg = <0x02084000 0x4000>; |
305 | interrupts = <0 84 0x04>; | |
33b38587 SH |
306 | clocks = <&clks 62>, <&clks 146>; |
307 | clock-names = "ipg", "per"; | |
7d740f87 SG |
308 | }; |
309 | ||
7b7d6727 | 310 | pwm3: pwm@02088000 { |
33b38587 SH |
311 | #pwm-cells = <2>; |
312 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
313 | reg = <0x02088000 0x4000>; |
314 | interrupts = <0 85 0x04>; | |
33b38587 SH |
315 | clocks = <&clks 62>, <&clks 147>; |
316 | clock-names = "ipg", "per"; | |
7d740f87 SG |
317 | }; |
318 | ||
7b7d6727 | 319 | pwm4: pwm@0208c000 { |
33b38587 SH |
320 | #pwm-cells = <2>; |
321 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
322 | reg = <0x0208c000 0x4000>; |
323 | interrupts = <0 86 0x04>; | |
33b38587 SH |
324 | clocks = <&clks 62>, <&clks 148>; |
325 | clock-names = "ipg", "per"; | |
7d740f87 SG |
326 | }; |
327 | ||
7b7d6727 | 328 | can1: flexcan@02090000 { |
0f225212 | 329 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 SG |
330 | reg = <0x02090000 0x4000>; |
331 | interrupts = <0 110 0x04>; | |
0f225212 SH |
332 | clocks = <&clks 108>, <&clks 109>; |
333 | clock-names = "ipg", "per"; | |
7d740f87 SG |
334 | }; |
335 | ||
7b7d6727 | 336 | can2: flexcan@02094000 { |
0f225212 | 337 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 SG |
338 | reg = <0x02094000 0x4000>; |
339 | interrupts = <0 111 0x04>; | |
0f225212 SH |
340 | clocks = <&clks 110>, <&clks 111>; |
341 | clock-names = "ipg", "per"; | |
7d740f87 SG |
342 | }; |
343 | ||
7b7d6727 | 344 | gpt: gpt@02098000 { |
97b108f9 | 345 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
7d740f87 SG |
346 | reg = <0x02098000 0x4000>; |
347 | interrupts = <0 55 0x04>; | |
4efccadd SH |
348 | clocks = <&clks 119>, <&clks 120>; |
349 | clock-names = "ipg", "per"; | |
7d740f87 SG |
350 | }; |
351 | ||
4d191868 | 352 | gpio1: gpio@0209c000 { |
aeb27748 | 353 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
354 | reg = <0x0209c000 0x4000>; |
355 | interrupts = <0 66 0x04 0 67 0x04>; | |
356 | gpio-controller; | |
357 | #gpio-cells = <2>; | |
358 | interrupt-controller; | |
88cde8b7 | 359 | #interrupt-cells = <2>; |
7d740f87 SG |
360 | }; |
361 | ||
4d191868 | 362 | gpio2: gpio@020a0000 { |
aeb27748 | 363 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
364 | reg = <0x020a0000 0x4000>; |
365 | interrupts = <0 68 0x04 0 69 0x04>; | |
366 | gpio-controller; | |
367 | #gpio-cells = <2>; | |
368 | interrupt-controller; | |
88cde8b7 | 369 | #interrupt-cells = <2>; |
7d740f87 SG |
370 | }; |
371 | ||
4d191868 | 372 | gpio3: gpio@020a4000 { |
aeb27748 | 373 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
374 | reg = <0x020a4000 0x4000>; |
375 | interrupts = <0 70 0x04 0 71 0x04>; | |
376 | gpio-controller; | |
377 | #gpio-cells = <2>; | |
378 | interrupt-controller; | |
88cde8b7 | 379 | #interrupt-cells = <2>; |
7d740f87 SG |
380 | }; |
381 | ||
4d191868 | 382 | gpio4: gpio@020a8000 { |
aeb27748 | 383 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
384 | reg = <0x020a8000 0x4000>; |
385 | interrupts = <0 72 0x04 0 73 0x04>; | |
386 | gpio-controller; | |
387 | #gpio-cells = <2>; | |
388 | interrupt-controller; | |
88cde8b7 | 389 | #interrupt-cells = <2>; |
7d740f87 SG |
390 | }; |
391 | ||
4d191868 | 392 | gpio5: gpio@020ac000 { |
aeb27748 | 393 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
394 | reg = <0x020ac000 0x4000>; |
395 | interrupts = <0 74 0x04 0 75 0x04>; | |
396 | gpio-controller; | |
397 | #gpio-cells = <2>; | |
398 | interrupt-controller; | |
88cde8b7 | 399 | #interrupt-cells = <2>; |
7d740f87 SG |
400 | }; |
401 | ||
4d191868 | 402 | gpio6: gpio@020b0000 { |
aeb27748 | 403 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
404 | reg = <0x020b0000 0x4000>; |
405 | interrupts = <0 76 0x04 0 77 0x04>; | |
406 | gpio-controller; | |
407 | #gpio-cells = <2>; | |
408 | interrupt-controller; | |
88cde8b7 | 409 | #interrupt-cells = <2>; |
7d740f87 SG |
410 | }; |
411 | ||
4d191868 | 412 | gpio7: gpio@020b4000 { |
aeb27748 | 413 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
414 | reg = <0x020b4000 0x4000>; |
415 | interrupts = <0 78 0x04 0 79 0x04>; | |
416 | gpio-controller; | |
417 | #gpio-cells = <2>; | |
418 | interrupt-controller; | |
88cde8b7 | 419 | #interrupt-cells = <2>; |
7d740f87 SG |
420 | }; |
421 | ||
7b7d6727 | 422 | kpp: kpp@020b8000 { |
7d740f87 SG |
423 | reg = <0x020b8000 0x4000>; |
424 | interrupts = <0 82 0x04>; | |
425 | }; | |
426 | ||
7b7d6727 | 427 | wdog1: wdog@020bc000 { |
7d740f87 SG |
428 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
429 | reg = <0x020bc000 0x4000>; | |
430 | interrupts = <0 80 0x04>; | |
0e87e043 | 431 | clocks = <&clks 0>; |
7d740f87 SG |
432 | }; |
433 | ||
7b7d6727 | 434 | wdog2: wdog@020c0000 { |
7d740f87 SG |
435 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
436 | reg = <0x020c0000 0x4000>; | |
437 | interrupts = <0 81 0x04>; | |
0e87e043 | 438 | clocks = <&clks 0>; |
7d740f87 SG |
439 | status = "disabled"; |
440 | }; | |
441 | ||
0e87e043 | 442 | clks: ccm@020c4000 { |
7d740f87 SG |
443 | compatible = "fsl,imx6q-ccm"; |
444 | reg = <0x020c4000 0x4000>; | |
445 | interrupts = <0 87 0x04 0 88 0x04>; | |
0e87e043 | 446 | #clock-cells = <1>; |
7d740f87 SG |
447 | }; |
448 | ||
baa64151 DA |
449 | anatop: anatop@020c8000 { |
450 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
7d740f87 SG |
451 | reg = <0x020c8000 0x1000>; |
452 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | |
a1e327e6 YCLP |
453 | |
454 | regulator-1p1@110 { | |
455 | compatible = "fsl,anatop-regulator"; | |
456 | regulator-name = "vdd1p1"; | |
457 | regulator-min-microvolt = <800000>; | |
458 | regulator-max-microvolt = <1375000>; | |
459 | regulator-always-on; | |
460 | anatop-reg-offset = <0x110>; | |
461 | anatop-vol-bit-shift = <8>; | |
462 | anatop-vol-bit-width = <5>; | |
463 | anatop-min-bit-val = <4>; | |
464 | anatop-min-voltage = <800000>; | |
465 | anatop-max-voltage = <1375000>; | |
466 | }; | |
467 | ||
468 | regulator-3p0@120 { | |
469 | compatible = "fsl,anatop-regulator"; | |
470 | regulator-name = "vdd3p0"; | |
471 | regulator-min-microvolt = <2800000>; | |
472 | regulator-max-microvolt = <3150000>; | |
473 | regulator-always-on; | |
474 | anatop-reg-offset = <0x120>; | |
475 | anatop-vol-bit-shift = <8>; | |
476 | anatop-vol-bit-width = <5>; | |
477 | anatop-min-bit-val = <0>; | |
478 | anatop-min-voltage = <2625000>; | |
479 | anatop-max-voltage = <3400000>; | |
480 | }; | |
481 | ||
482 | regulator-2p5@130 { | |
483 | compatible = "fsl,anatop-regulator"; | |
484 | regulator-name = "vdd2p5"; | |
485 | regulator-min-microvolt = <2000000>; | |
486 | regulator-max-microvolt = <2750000>; | |
487 | regulator-always-on; | |
488 | anatop-reg-offset = <0x130>; | |
489 | anatop-vol-bit-shift = <8>; | |
490 | anatop-vol-bit-width = <5>; | |
491 | anatop-min-bit-val = <0>; | |
492 | anatop-min-voltage = <2000000>; | |
493 | anatop-max-voltage = <2750000>; | |
494 | }; | |
495 | ||
96574a6d | 496 | reg_arm: regulator-vddcore@140 { |
a1e327e6 YCLP |
497 | compatible = "fsl,anatop-regulator"; |
498 | regulator-name = "cpu"; | |
499 | regulator-min-microvolt = <725000>; | |
500 | regulator-max-microvolt = <1450000>; | |
501 | regulator-always-on; | |
502 | anatop-reg-offset = <0x140>; | |
503 | anatop-vol-bit-shift = <0>; | |
504 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
505 | anatop-delay-reg-offset = <0x170>; |
506 | anatop-delay-bit-shift = <24>; | |
507 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
508 | anatop-min-bit-val = <1>; |
509 | anatop-min-voltage = <725000>; | |
510 | anatop-max-voltage = <1450000>; | |
511 | }; | |
512 | ||
96574a6d | 513 | reg_pu: regulator-vddpu@140 { |
a1e327e6 YCLP |
514 | compatible = "fsl,anatop-regulator"; |
515 | regulator-name = "vddpu"; | |
516 | regulator-min-microvolt = <725000>; | |
517 | regulator-max-microvolt = <1450000>; | |
518 | regulator-always-on; | |
519 | anatop-reg-offset = <0x140>; | |
520 | anatop-vol-bit-shift = <9>; | |
521 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
522 | anatop-delay-reg-offset = <0x170>; |
523 | anatop-delay-bit-shift = <26>; | |
524 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
525 | anatop-min-bit-val = <1>; |
526 | anatop-min-voltage = <725000>; | |
527 | anatop-max-voltage = <1450000>; | |
528 | }; | |
529 | ||
96574a6d | 530 | reg_soc: regulator-vddsoc@140 { |
a1e327e6 YCLP |
531 | compatible = "fsl,anatop-regulator"; |
532 | regulator-name = "vddsoc"; | |
533 | regulator-min-microvolt = <725000>; | |
534 | regulator-max-microvolt = <1450000>; | |
535 | regulator-always-on; | |
536 | anatop-reg-offset = <0x140>; | |
537 | anatop-vol-bit-shift = <18>; | |
538 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
539 | anatop-delay-reg-offset = <0x170>; |
540 | anatop-delay-bit-shift = <28>; | |
541 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
542 | anatop-min-bit-val = <1>; |
543 | anatop-min-voltage = <725000>; | |
544 | anatop-max-voltage = <1450000>; | |
545 | }; | |
7d740f87 SG |
546 | }; |
547 | ||
3fe6373b SG |
548 | tempmon: tempmon { |
549 | compatible = "fsl,imx6q-tempmon"; | |
550 | interrupts = <0 49 0x04>; | |
551 | fsl,tempmon = <&anatop>; | |
552 | fsl,tempmon-data = <&ocotp>; | |
553 | }; | |
554 | ||
74bd88f7 RZ |
555 | usbphy1: usbphy@020c9000 { |
556 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 SG |
557 | reg = <0x020c9000 0x1000>; |
558 | interrupts = <0 44 0x04>; | |
0e87e043 | 559 | clocks = <&clks 182>; |
7d740f87 SG |
560 | }; |
561 | ||
74bd88f7 RZ |
562 | usbphy2: usbphy@020ca000 { |
563 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 SG |
564 | reg = <0x020ca000 0x1000>; |
565 | interrupts = <0 45 0x04>; | |
0e87e043 | 566 | clocks = <&clks 183>; |
7d740f87 SG |
567 | }; |
568 | ||
569 | snvs@020cc000 { | |
c9250388 SG |
570 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
571 | #address-cells = <1>; | |
572 | #size-cells = <1>; | |
573 | ranges = <0 0x020cc000 0x4000>; | |
574 | ||
575 | snvs-rtc-lp@34 { | |
576 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
577 | reg = <0x34 0x58>; | |
578 | interrupts = <0 19 0x04 0 20 0x04>; | |
579 | }; | |
7d740f87 SG |
580 | }; |
581 | ||
7b7d6727 | 582 | epit1: epit@020d0000 { /* EPIT1 */ |
7d740f87 SG |
583 | reg = <0x020d0000 0x4000>; |
584 | interrupts = <0 56 0x04>; | |
585 | }; | |
586 | ||
7b7d6727 | 587 | epit2: epit@020d4000 { /* EPIT2 */ |
7d740f87 SG |
588 | reg = <0x020d4000 0x4000>; |
589 | interrupts = <0 57 0x04>; | |
590 | }; | |
591 | ||
7b7d6727 | 592 | src: src@020d8000 { |
bd3d924d | 593 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
7d740f87 SG |
594 | reg = <0x020d8000 0x4000>; |
595 | interrupts = <0 91 0x04 0 96 0x04>; | |
09ebf366 | 596 | #reset-cells = <1>; |
7d740f87 SG |
597 | }; |
598 | ||
7b7d6727 | 599 | gpc: gpc@020dc000 { |
7d740f87 SG |
600 | compatible = "fsl,imx6q-gpc"; |
601 | reg = <0x020dc000 0x4000>; | |
602 | interrupts = <0 89 0x04 0 90 0x04>; | |
603 | }; | |
604 | ||
df37e0c0 DA |
605 | gpr: iomuxc-gpr@020e0000 { |
606 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
607 | reg = <0x020e0000 0x38>; | |
608 | }; | |
609 | ||
c56009b2 SG |
610 | iomuxc: iomuxc@020e0000 { |
611 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | |
612 | reg = <0x020e0000 0x4000>; | |
613 | ||
614 | audmux { | |
615 | pinctrl_audmux_1: audmux-1 { | |
616 | fsl,pins = < | |
617 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 | |
618 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 | |
619 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 | |
620 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 | |
621 | >; | |
622 | }; | |
623 | ||
624 | pinctrl_audmux_2: audmux-2 { | |
625 | fsl,pins = < | |
626 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | |
627 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | |
628 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | |
629 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | |
630 | >; | |
631 | }; | |
b72ce929 SG |
632 | |
633 | pinctrl_audmux_3: audmux-3 { | |
634 | fsl,pins = < | |
635 | MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 | |
636 | MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 | |
637 | MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 | |
638 | >; | |
639 | }; | |
c56009b2 SG |
640 | }; |
641 | ||
642 | ecspi1 { | |
643 | pinctrl_ecspi1_1: ecspi1grp-1 { | |
644 | fsl,pins = < | |
645 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | |
646 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | |
647 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | |
648 | >; | |
649 | }; | |
650 | ||
651 | pinctrl_ecspi1_2: ecspi1grp-2 { | |
652 | fsl,pins = < | |
653 | MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 | |
654 | MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 | |
655 | MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 | |
656 | >; | |
657 | }; | |
658 | }; | |
659 | ||
660 | ecspi3 { | |
661 | pinctrl_ecspi3_1: ecspi3grp-1 { | |
662 | fsl,pins = < | |
663 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | |
664 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | |
665 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | |
666 | >; | |
667 | }; | |
668 | }; | |
669 | ||
670 | enet { | |
671 | pinctrl_enet_1: enetgrp-1 { | |
672 | fsl,pins = < | |
673 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
674 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
675 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
676 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
677 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
678 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
679 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
680 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
681 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
682 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
683 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
684 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
685 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
686 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
687 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
688 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | |
689 | >; | |
690 | }; | |
691 | ||
692 | pinctrl_enet_2: enetgrp-2 { | |
693 | fsl,pins = < | |
694 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | |
695 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | |
696 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
697 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
698 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
699 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
700 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
701 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
702 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
703 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
704 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
705 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
706 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
707 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
708 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
709 | >; | |
710 | }; | |
711 | ||
712 | pinctrl_enet_3: enetgrp-3 { | |
713 | fsl,pins = < | |
714 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
715 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
716 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
717 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
718 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
719 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
720 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
721 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
722 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
723 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
724 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
725 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
726 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
727 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
728 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
729 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | |
730 | >; | |
731 | }; | |
732 | }; | |
733 | ||
b72ce929 SG |
734 | esai { |
735 | pinctrl_esai_1: esaigrp-1 { | |
736 | fsl,pins = < | |
737 | MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 | |
738 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | |
739 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | |
740 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | |
741 | MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 | |
742 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | |
743 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | |
744 | MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 | |
745 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | |
746 | >; | |
747 | }; | |
748 | ||
749 | pinctrl_esai_2: esaigrp-2 { | |
750 | fsl,pins = < | |
751 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | |
752 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | |
753 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | |
754 | MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 | |
755 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | |
756 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | |
757 | MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 | |
758 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | |
759 | MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 | |
760 | MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 | |
761 | >; | |
762 | }; | |
763 | }; | |
764 | ||
765 | flexcan1 { | |
766 | pinctrl_flexcan1_1: flexcan1grp-1 { | |
767 | fsl,pins = < | |
768 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | |
769 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 | |
770 | >; | |
771 | }; | |
772 | ||
773 | pinctrl_flexcan1_2: flexcan1grp-2 { | |
774 | fsl,pins = < | |
775 | MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 | |
776 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | |
777 | >; | |
778 | }; | |
779 | }; | |
780 | ||
781 | flexcan2 { | |
782 | pinctrl_flexcan2_1: flexcan2grp-1 { | |
783 | fsl,pins = < | |
784 | MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 | |
785 | MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 | |
786 | >; | |
787 | }; | |
788 | }; | |
789 | ||
c56009b2 SG |
790 | gpmi-nand { |
791 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | |
792 | fsl,pins = < | |
793 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | |
794 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | |
795 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | |
796 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | |
797 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | |
798 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | |
799 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | |
800 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | |
801 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | |
802 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | |
803 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | |
804 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | |
805 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | |
806 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | |
807 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | |
808 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | |
809 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | |
810 | >; | |
811 | }; | |
812 | }; | |
813 | ||
b72ce929 SG |
814 | hdmi_hdcp { |
815 | pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { | |
816 | fsl,pins = < | |
817 | MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 | |
818 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | |
819 | >; | |
820 | }; | |
821 | ||
822 | pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { | |
823 | fsl,pins = < | |
824 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | |
825 | MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 | |
826 | >; | |
827 | }; | |
828 | ||
829 | pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { | |
830 | fsl,pins = < | |
831 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | |
832 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | |
833 | >; | |
834 | }; | |
835 | }; | |
836 | ||
837 | hdmi_cec { | |
838 | pinctrl_hdmi_cec_1: hdmicecgrp-1 { | |
839 | fsl,pins = < | |
840 | MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 | |
841 | >; | |
842 | }; | |
843 | ||
844 | pinctrl_hdmi_cec_2: hdmicecgrp-2 { | |
845 | fsl,pins = < | |
846 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | |
847 | >; | |
848 | }; | |
849 | }; | |
850 | ||
c56009b2 SG |
851 | i2c1 { |
852 | pinctrl_i2c1_1: i2c1grp-1 { | |
853 | fsl,pins = < | |
854 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | |
855 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | |
856 | >; | |
857 | }; | |
858 | ||
859 | pinctrl_i2c1_2: i2c1grp-2 { | |
860 | fsl,pins = < | |
861 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | |
862 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | |
863 | >; | |
864 | }; | |
865 | }; | |
866 | ||
867 | i2c2 { | |
868 | pinctrl_i2c2_1: i2c2grp-1 { | |
869 | fsl,pins = < | |
870 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | |
871 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | |
872 | >; | |
873 | }; | |
874 | ||
875 | pinctrl_i2c2_2: i2c2grp-2 { | |
876 | fsl,pins = < | |
877 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | |
878 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | |
879 | >; | |
880 | }; | |
b72ce929 SG |
881 | |
882 | pinctrl_i2c2_3: i2c2grp-3 { | |
883 | fsl,pins = < | |
884 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | |
885 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | |
886 | >; | |
887 | }; | |
c56009b2 SG |
888 | }; |
889 | ||
890 | i2c3 { | |
891 | pinctrl_i2c3_1: i2c3grp-1 { | |
892 | fsl,pins = < | |
893 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | |
894 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | |
895 | >; | |
896 | }; | |
b72ce929 SG |
897 | |
898 | pinctrl_i2c3_2: i2c3grp-2 { | |
899 | fsl,pins = < | |
900 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | |
901 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | |
902 | >; | |
903 | }; | |
904 | ||
905 | pinctrl_i2c3_3: i2c3grp-3 { | |
906 | fsl,pins = < | |
907 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | |
908 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 | |
909 | >; | |
910 | }; | |
911 | ||
912 | pinctrl_i2c3_4: i2c3grp-4 { | |
913 | fsl,pins = < | |
914 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | |
915 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | |
916 | >; | |
917 | }; | |
918 | }; | |
919 | ||
920 | ipu1 { | |
921 | pinctrl_ipu1_1: ipu1grp-1 { | |
922 | fsl,pins = < | |
923 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 | |
924 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 | |
925 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 | |
926 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 | |
927 | MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 | |
928 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 | |
929 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 | |
930 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 | |
931 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 | |
932 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 | |
933 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 | |
934 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 | |
935 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 | |
936 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 | |
937 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 | |
938 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 | |
939 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 | |
940 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 | |
941 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 | |
942 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 | |
943 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 | |
944 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 | |
945 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 | |
946 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 | |
947 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 | |
948 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 | |
949 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 | |
950 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 | |
951 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 | |
952 | >; | |
953 | }; | |
954 | ||
955 | pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ | |
956 | fsl,pins = < | |
957 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | |
958 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | |
959 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | |
960 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | |
961 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | |
962 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | |
963 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | |
964 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | |
965 | MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 | |
966 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | |
967 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | |
968 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | |
969 | >; | |
970 | }; | |
971 | ||
972 | pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ | |
973 | fsl,pins = < | |
974 | MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 | |
975 | MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 | |
976 | MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 | |
977 | MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 | |
978 | MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 | |
979 | MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 | |
980 | MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 | |
981 | MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 | |
982 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | |
983 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | |
984 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | |
985 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | |
986 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | |
987 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | |
988 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | |
989 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | |
990 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | |
991 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | |
992 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | |
993 | >; | |
994 | }; | |
995 | }; | |
996 | ||
997 | mlb { | |
998 | pinctrl_mlb_1: mlbgrp-1 { | |
999 | fsl,pins = < | |
1000 | MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 | |
1001 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | |
1002 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | |
1003 | >; | |
1004 | }; | |
1005 | ||
1006 | pinctrl_mlb_2: mlbgrp-2 { | |
1007 | fsl,pins = < | |
1008 | MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 | |
1009 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | |
1010 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | |
1011 | >; | |
1012 | }; | |
1013 | }; | |
1014 | ||
1015 | pwm0 { | |
1016 | pinctrl_pwm0_1: pwm0grp-1 { | |
1017 | fsl,pins = < | |
1018 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | |
1019 | >; | |
1020 | }; | |
1021 | }; | |
1022 | ||
1023 | pwm3 { | |
1024 | pinctrl_pwm3_1: pwm3grp-1 { | |
1025 | fsl,pins = < | |
1026 | MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 | |
1027 | >; | |
1028 | }; | |
1029 | }; | |
1030 | ||
1031 | spdif { | |
1032 | pinctrl_spdif_1: spdifgrp-1 { | |
1033 | fsl,pins = < | |
1034 | MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 | |
1035 | >; | |
1036 | }; | |
1037 | ||
1038 | pinctrl_spdif_2: spdifgrp-2 { | |
1039 | fsl,pins = < | |
1040 | MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 | |
1041 | MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 | |
1042 | >; | |
1043 | }; | |
c9d96df2 FE |
1044 | |
1045 | pinctrl_spdif_3: spdifgrp-3 { | |
1046 | fsl,pins = < | |
1047 | MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 | |
1048 | >; | |
1049 | }; | |
c56009b2 SG |
1050 | }; |
1051 | ||
1052 | uart1 { | |
1053 | pinctrl_uart1_1: uart1grp-1 { | |
1054 | fsl,pins = < | |
1055 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | |
1056 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | |
1057 | >; | |
1058 | }; | |
1059 | }; | |
1060 | ||
1061 | uart2 { | |
1062 | pinctrl_uart2_1: uart2grp-1 { | |
1063 | fsl,pins = < | |
1064 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | |
1065 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | |
1066 | >; | |
1067 | }; | |
1068 | ||
1069 | pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ | |
1070 | fsl,pins = < | |
1071 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 | |
1072 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 | |
1073 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 | |
1074 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 | |
1075 | >; | |
1076 | }; | |
1077 | }; | |
1078 | ||
c2797984 HS |
1079 | uart3 { |
1080 | pinctrl_uart3_1: uart3grp-1 { | |
1081 | fsl,pins = < | |
1082 | MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 | |
1083 | MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 | |
1084 | MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 | |
1085 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | |
1086 | >; | |
1087 | }; | |
5ff88341 FE |
1088 | |
1089 | pinctrl_uart3_2: uart3grp-2 { | |
1090 | fsl,pins = < | |
1091 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | |
1092 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | |
1093 | MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 | |
1094 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | |
1095 | >; | |
1096 | }; | |
c2797984 HS |
1097 | }; |
1098 | ||
c56009b2 SG |
1099 | uart4 { |
1100 | pinctrl_uart4_1: uart4grp-1 { | |
1101 | fsl,pins = < | |
1102 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | |
1103 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | |
1104 | >; | |
1105 | }; | |
1106 | }; | |
1107 | ||
1108 | usbotg { | |
1109 | pinctrl_usbotg_1: usbotggrp-1 { | |
1110 | fsl,pins = < | |
1111 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | |
1112 | >; | |
1113 | }; | |
1114 | ||
1115 | pinctrl_usbotg_2: usbotggrp-2 { | |
1116 | fsl,pins = < | |
1117 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | |
1118 | >; | |
1119 | }; | |
1120 | }; | |
1121 | ||
b72ce929 SG |
1122 | usbh2 { |
1123 | pinctrl_usbh2_1: usbh2grp-1 { | |
1124 | fsl,pins = < | |
1125 | MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 | |
1126 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 | |
1127 | >; | |
1128 | }; | |
1129 | ||
1130 | pinctrl_usbh2_2: usbh2grp-2 { | |
1131 | fsl,pins = < | |
1132 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 | |
1133 | >; | |
1134 | }; | |
1135 | }; | |
1136 | ||
1137 | usbh3 { | |
1138 | pinctrl_usbh3_1: usbh3grp-1 { | |
1139 | fsl,pins = < | |
1140 | MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 | |
1141 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 | |
1142 | >; | |
1143 | }; | |
1144 | ||
1145 | pinctrl_usbh3_2: usbh3grp-2 { | |
1146 | fsl,pins = < | |
1147 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 | |
1148 | >; | |
1149 | }; | |
1150 | }; | |
1151 | ||
26c3b65d FE |
1152 | usdhc1 { |
1153 | pinctrl_usdhc1_1: usdhc1grp-1 { | |
1154 | fsl,pins = < | |
1155 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 | |
1156 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 | |
1157 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | |
1158 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | |
1159 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | |
1160 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | |
1161 | MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 | |
1162 | MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 | |
1163 | MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 | |
1164 | MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 | |
1165 | >; | |
1166 | }; | |
1167 | ||
1168 | pinctrl_usdhc1_2: usdhc1grp-2 { | |
1169 | fsl,pins = < | |
1170 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 | |
1171 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 | |
1172 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | |
1173 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | |
1174 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | |
1175 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | |
1176 | >; | |
1177 | }; | |
1178 | }; | |
1179 | ||
c56009b2 SG |
1180 | usdhc2 { |
1181 | pinctrl_usdhc2_1: usdhc2grp-1 { | |
1182 | fsl,pins = < | |
1183 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | |
1184 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | |
1185 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | |
1186 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | |
1187 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | |
1188 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | |
1189 | MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 | |
1190 | MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 | |
1191 | MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 | |
1192 | MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 | |
1193 | >; | |
1194 | }; | |
1195 | ||
1196 | pinctrl_usdhc2_2: usdhc2grp-2 { | |
1197 | fsl,pins = < | |
1198 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | |
1199 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | |
1200 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | |
1201 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | |
1202 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | |
1203 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | |
1204 | >; | |
1205 | }; | |
1206 | }; | |
1207 | ||
1208 | usdhc3 { | |
1209 | pinctrl_usdhc3_1: usdhc3grp-1 { | |
1210 | fsl,pins = < | |
1211 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
1212 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
1213 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
1214 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
1215 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
1216 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
1217 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | |
1218 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | |
1219 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | |
1220 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | |
1221 | >; | |
1222 | }; | |
1223 | ||
93e2ca02 DA |
1224 | pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ |
1225 | fsl,pins = < | |
1226 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 | |
1227 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 | |
1228 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 | |
1229 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 | |
1230 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 | |
1231 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 | |
1232 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 | |
1233 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 | |
1234 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 | |
1235 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 | |
1236 | >; | |
1237 | }; | |
1238 | ||
1239 | pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ | |
1240 | fsl,pins = < | |
1241 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 | |
1242 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 | |
1243 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 | |
1244 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 | |
1245 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 | |
1246 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 | |
1247 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 | |
1248 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 | |
1249 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 | |
1250 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 | |
1251 | >; | |
1252 | }; | |
1253 | ||
c56009b2 SG |
1254 | pinctrl_usdhc3_2: usdhc3grp-2 { |
1255 | fsl,pins = < | |
1256 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
1257 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
1258 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
1259 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
1260 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
1261 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
1262 | >; | |
1263 | }; | |
1264 | }; | |
1265 | ||
1266 | usdhc4 { | |
1267 | pinctrl_usdhc4_1: usdhc4grp-1 { | |
1268 | fsl,pins = < | |
1269 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | |
1270 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | |
1271 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | |
1272 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | |
1273 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | |
1274 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | |
1275 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | |
1276 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | |
1277 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | |
1278 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | |
1279 | >; | |
1280 | }; | |
1281 | ||
1282 | pinctrl_usdhc4_2: usdhc4grp-2 { | |
1283 | fsl,pins = < | |
1284 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | |
1285 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | |
1286 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | |
1287 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | |
1288 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | |
1289 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | |
1290 | >; | |
1291 | }; | |
1292 | }; | |
1293 | ||
1294 | weim { | |
1295 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | |
1296 | fsl,pins = < | |
1297 | MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | |
1298 | >; | |
1299 | }; | |
1300 | ||
1301 | pinctrl_weim_nor_1: weim_norgrp-1 { | |
1302 | fsl,pins = < | |
1303 | MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | |
1304 | MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 | |
1305 | MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | |
1306 | /* data */ | |
1307 | MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | |
1308 | MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | |
1309 | MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | |
1310 | MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | |
1311 | MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | |
1312 | MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | |
1313 | MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | |
1314 | MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | |
1315 | MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | |
1316 | MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | |
1317 | MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | |
1318 | MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | |
1319 | MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | |
1320 | MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | |
1321 | MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | |
1322 | MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | |
1323 | /* address */ | |
1324 | MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | |
1325 | MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | |
1326 | MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | |
1327 | MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | |
1328 | MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | |
1329 | MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | |
1330 | MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | |
1331 | MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | |
1332 | MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | |
1333 | MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | |
1334 | MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | |
1335 | MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | |
1336 | MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | |
1337 | MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | |
1338 | MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | |
1339 | MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | |
1340 | MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | |
1341 | MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | |
1342 | MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | |
1343 | MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | |
1344 | MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | |
1345 | MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | |
1346 | MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | |
1347 | MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | |
1348 | >; | |
1349 | }; | |
1350 | }; | |
1351 | }; | |
1352 | ||
41c04342 ST |
1353 | ldb: ldb@020e0008 { |
1354 | #address-cells = <1>; | |
1355 | #size-cells = <0>; | |
1356 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
1357 | gpr = <&gpr>; | |
1358 | status = "disabled"; | |
1359 | ||
1360 | lvds-channel@0 { | |
1361 | reg = <0>; | |
41c04342 ST |
1362 | status = "disabled"; |
1363 | }; | |
1364 | ||
1365 | lvds-channel@1 { | |
1366 | reg = <1>; | |
41c04342 ST |
1367 | status = "disabled"; |
1368 | }; | |
1369 | }; | |
1370 | ||
7b7d6727 | 1371 | dcic1: dcic@020e4000 { |
7d740f87 SG |
1372 | reg = <0x020e4000 0x4000>; |
1373 | interrupts = <0 124 0x04>; | |
1374 | }; | |
1375 | ||
7b7d6727 | 1376 | dcic2: dcic@020e8000 { |
7d740f87 SG |
1377 | reg = <0x020e8000 0x4000>; |
1378 | interrupts = <0 125 0x04>; | |
1379 | }; | |
1380 | ||
7b7d6727 | 1381 | sdma: sdma@020ec000 { |
7d740f87 SG |
1382 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
1383 | reg = <0x020ec000 0x4000>; | |
1384 | interrupts = <0 2 0x04>; | |
0e87e043 SG |
1385 | clocks = <&clks 155>, <&clks 155>; |
1386 | clock-names = "ipg", "ahb"; | |
fb72bb21 | 1387 | #dma-cells = <3>; |
d6b9c591 | 1388 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
7d740f87 SG |
1389 | }; |
1390 | }; | |
1391 | ||
1392 | aips-bus@02100000 { /* AIPS2 */ | |
1393 | compatible = "fsl,aips-bus", "simple-bus"; | |
1394 | #address-cells = <1>; | |
1395 | #size-cells = <1>; | |
1396 | reg = <0x02100000 0x100000>; | |
1397 | ranges; | |
1398 | ||
1399 | caam@02100000 { | |
1400 | reg = <0x02100000 0x40000>; | |
1401 | interrupts = <0 105 0x04 0 106 0x04>; | |
1402 | }; | |
1403 | ||
1404 | aipstz@0217c000 { /* AIPSTZ2 */ | |
1405 | reg = <0x0217c000 0x4000>; | |
1406 | }; | |
1407 | ||
7b7d6727 | 1408 | usbotg: usb@02184000 { |
74bd88f7 RZ |
1409 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
1410 | reg = <0x02184000 0x200>; | |
1411 | interrupts = <0 43 0x04>; | |
0e87e043 | 1412 | clocks = <&clks 162>; |
74bd88f7 | 1413 | fsl,usbphy = <&usbphy1>; |
28342c61 | 1414 | fsl,usbmisc = <&usbmisc 0>; |
74bd88f7 RZ |
1415 | status = "disabled"; |
1416 | }; | |
1417 | ||
7b7d6727 | 1418 | usbh1: usb@02184200 { |
74bd88f7 RZ |
1419 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
1420 | reg = <0x02184200 0x200>; | |
1421 | interrupts = <0 40 0x04>; | |
0e87e043 | 1422 | clocks = <&clks 162>; |
74bd88f7 | 1423 | fsl,usbphy = <&usbphy2>; |
28342c61 | 1424 | fsl,usbmisc = <&usbmisc 1>; |
74bd88f7 RZ |
1425 | status = "disabled"; |
1426 | }; | |
1427 | ||
7b7d6727 | 1428 | usbh2: usb@02184400 { |
74bd88f7 RZ |
1429 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
1430 | reg = <0x02184400 0x200>; | |
1431 | interrupts = <0 41 0x04>; | |
0e87e043 | 1432 | clocks = <&clks 162>; |
28342c61 | 1433 | fsl,usbmisc = <&usbmisc 2>; |
74bd88f7 RZ |
1434 | status = "disabled"; |
1435 | }; | |
1436 | ||
7b7d6727 | 1437 | usbh3: usb@02184600 { |
74bd88f7 RZ |
1438 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
1439 | reg = <0x02184600 0x200>; | |
1440 | interrupts = <0 42 0x04>; | |
0e87e043 | 1441 | clocks = <&clks 162>; |
28342c61 | 1442 | fsl,usbmisc = <&usbmisc 3>; |
74bd88f7 RZ |
1443 | status = "disabled"; |
1444 | }; | |
1445 | ||
60984bdf | 1446 | usbmisc: usbmisc@02184800 { |
28342c61 RZ |
1447 | #index-cells = <1>; |
1448 | compatible = "fsl,imx6q-usbmisc"; | |
1449 | reg = <0x02184800 0x200>; | |
1450 | clocks = <&clks 162>; | |
1451 | }; | |
1452 | ||
7b7d6727 | 1453 | fec: ethernet@02188000 { |
7d740f87 SG |
1454 | compatible = "fsl,imx6q-fec"; |
1455 | reg = <0x02188000 0x4000>; | |
1456 | interrupts = <0 118 0x04 0 119 0x04>; | |
8dd5c66b | 1457 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
7629838c | 1458 | clock-names = "ipg", "ahb", "ptp"; |
7d740f87 SG |
1459 | status = "disabled"; |
1460 | }; | |
1461 | ||
1462 | mlb@0218c000 { | |
1463 | reg = <0x0218c000 0x4000>; | |
1464 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; | |
1465 | }; | |
1466 | ||
7b7d6727 | 1467 | usdhc1: usdhc@02190000 { |
7d740f87 SG |
1468 | compatible = "fsl,imx6q-usdhc"; |
1469 | reg = <0x02190000 0x4000>; | |
1470 | interrupts = <0 22 0x04>; | |
0e87e043 SG |
1471 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
1472 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 1473 | bus-width = <4>; |
7d740f87 SG |
1474 | status = "disabled"; |
1475 | }; | |
1476 | ||
7b7d6727 | 1477 | usdhc2: usdhc@02194000 { |
7d740f87 SG |
1478 | compatible = "fsl,imx6q-usdhc"; |
1479 | reg = <0x02194000 0x4000>; | |
1480 | interrupts = <0 23 0x04>; | |
0e87e043 SG |
1481 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
1482 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 1483 | bus-width = <4>; |
7d740f87 SG |
1484 | status = "disabled"; |
1485 | }; | |
1486 | ||
7b7d6727 | 1487 | usdhc3: usdhc@02198000 { |
7d740f87 SG |
1488 | compatible = "fsl,imx6q-usdhc"; |
1489 | reg = <0x02198000 0x4000>; | |
1490 | interrupts = <0 24 0x04>; | |
0e87e043 SG |
1491 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
1492 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 1493 | bus-width = <4>; |
7d740f87 SG |
1494 | status = "disabled"; |
1495 | }; | |
1496 | ||
7b7d6727 | 1497 | usdhc4: usdhc@0219c000 { |
7d740f87 SG |
1498 | compatible = "fsl,imx6q-usdhc"; |
1499 | reg = <0x0219c000 0x4000>; | |
1500 | interrupts = <0 25 0x04>; | |
0e87e043 SG |
1501 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
1502 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 1503 | bus-width = <4>; |
7d740f87 SG |
1504 | status = "disabled"; |
1505 | }; | |
1506 | ||
7b7d6727 | 1507 | i2c1: i2c@021a0000 { |
7d740f87 SG |
1508 | #address-cells = <1>; |
1509 | #size-cells = <0>; | |
5bdfba29 | 1510 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
1511 | reg = <0x021a0000 0x4000>; |
1512 | interrupts = <0 36 0x04>; | |
0e87e043 | 1513 | clocks = <&clks 125>; |
7d740f87 SG |
1514 | status = "disabled"; |
1515 | }; | |
1516 | ||
7b7d6727 | 1517 | i2c2: i2c@021a4000 { |
7d740f87 SG |
1518 | #address-cells = <1>; |
1519 | #size-cells = <0>; | |
5bdfba29 | 1520 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
1521 | reg = <0x021a4000 0x4000>; |
1522 | interrupts = <0 37 0x04>; | |
0e87e043 | 1523 | clocks = <&clks 126>; |
7d740f87 SG |
1524 | status = "disabled"; |
1525 | }; | |
1526 | ||
7b7d6727 | 1527 | i2c3: i2c@021a8000 { |
7d740f87 SG |
1528 | #address-cells = <1>; |
1529 | #size-cells = <0>; | |
5bdfba29 | 1530 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
1531 | reg = <0x021a8000 0x4000>; |
1532 | interrupts = <0 38 0x04>; | |
0e87e043 | 1533 | clocks = <&clks 127>; |
7d740f87 SG |
1534 | status = "disabled"; |
1535 | }; | |
1536 | ||
1537 | romcp@021ac000 { | |
1538 | reg = <0x021ac000 0x4000>; | |
1539 | }; | |
1540 | ||
7b7d6727 | 1541 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
7d740f87 SG |
1542 | compatible = "fsl,imx6q-mmdc"; |
1543 | reg = <0x021b0000 0x4000>; | |
1544 | }; | |
1545 | ||
7b7d6727 | 1546 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
7d740f87 SG |
1547 | reg = <0x021b4000 0x4000>; |
1548 | }; | |
1549 | ||
05e3f8e7 HS |
1550 | weim: weim@021b8000 { |
1551 | compatible = "fsl,imx6q-weim"; | |
7d740f87 SG |
1552 | reg = <0x021b8000 0x4000>; |
1553 | interrupts = <0 14 0x04>; | |
05e3f8e7 | 1554 | clocks = <&clks 196>; |
7d740f87 SG |
1555 | }; |
1556 | ||
3fe6373b SG |
1557 | ocotp: ocotp@021bc000 { |
1558 | compatible = "fsl,imx6q-ocotp", "syscon"; | |
7d740f87 SG |
1559 | reg = <0x021bc000 0x4000>; |
1560 | }; | |
1561 | ||
7d740f87 SG |
1562 | tzasc@021d0000 { /* TZASC1 */ |
1563 | reg = <0x021d0000 0x4000>; | |
1564 | interrupts = <0 108 0x04>; | |
1565 | }; | |
1566 | ||
1567 | tzasc@021d4000 { /* TZASC2 */ | |
1568 | reg = <0x021d4000 0x4000>; | |
1569 | interrupts = <0 109 0x04>; | |
1570 | }; | |
1571 | ||
7b7d6727 | 1572 | audmux: audmux@021d8000 { |
f965cd55 | 1573 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 1574 | reg = <0x021d8000 0x4000>; |
f965cd55 | 1575 | status = "disabled"; |
7d740f87 SG |
1576 | }; |
1577 | ||
1578 | mipi@021dc000 { /* MIPI-CSI */ | |
1579 | reg = <0x021dc000 0x4000>; | |
1580 | }; | |
1581 | ||
1582 | mipi@021e0000 { /* MIPI-DSI */ | |
1583 | reg = <0x021e0000 0x4000>; | |
1584 | }; | |
1585 | ||
1586 | vdoa@021e4000 { | |
1587 | reg = <0x021e4000 0x4000>; | |
1588 | interrupts = <0 18 0x04>; | |
1589 | }; | |
1590 | ||
0c456cfa | 1591 | uart2: serial@021e8000 { |
7d740f87 SG |
1592 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1593 | reg = <0x021e8000 0x4000>; | |
1594 | interrupts = <0 27 0x04>; | |
0e87e043 SG |
1595 | clocks = <&clks 160>, <&clks 161>; |
1596 | clock-names = "ipg", "per"; | |
72a5cebf HS |
1597 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
1598 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1599 | status = "disabled"; |
1600 | }; | |
1601 | ||
0c456cfa | 1602 | uart3: serial@021ec000 { |
7d740f87 SG |
1603 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1604 | reg = <0x021ec000 0x4000>; | |
1605 | interrupts = <0 28 0x04>; | |
0e87e043 SG |
1606 | clocks = <&clks 160>, <&clks 161>; |
1607 | clock-names = "ipg", "per"; | |
72a5cebf HS |
1608 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
1609 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1610 | status = "disabled"; |
1611 | }; | |
1612 | ||
0c456cfa | 1613 | uart4: serial@021f0000 { |
7d740f87 SG |
1614 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1615 | reg = <0x021f0000 0x4000>; | |
1616 | interrupts = <0 29 0x04>; | |
0e87e043 SG |
1617 | clocks = <&clks 160>, <&clks 161>; |
1618 | clock-names = "ipg", "per"; | |
72a5cebf HS |
1619 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
1620 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1621 | status = "disabled"; |
1622 | }; | |
1623 | ||
0c456cfa | 1624 | uart5: serial@021f4000 { |
7d740f87 SG |
1625 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1626 | reg = <0x021f4000 0x4000>; | |
1627 | interrupts = <0 30 0x04>; | |
0e87e043 SG |
1628 | clocks = <&clks 160>, <&clks 161>; |
1629 | clock-names = "ipg", "per"; | |
72a5cebf HS |
1630 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
1631 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1632 | status = "disabled"; |
1633 | }; | |
1634 | }; | |
91660d74 SH |
1635 | |
1636 | ipu1: ipu@02400000 { | |
1637 | #crtc-cells = <1>; | |
1638 | compatible = "fsl,imx6q-ipu"; | |
1639 | reg = <0x02400000 0x400000>; | |
1640 | interrupts = <0 6 0x4 0 5 0x4>; | |
1641 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; | |
1642 | clock-names = "bus", "di0", "di1"; | |
09ebf366 | 1643 | resets = <&src 2>; |
91660d74 | 1644 | }; |
7d740f87 SG |
1645 | }; |
1646 | }; |