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ARM: dts: imx: use generic DMA bindings for SSI nodes
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
7d740f87
SG		 14
15/ {
16 aliases {
5230f8fe
SG		 17 gpio0 = &gpio1;
18 gpio1 = &gpio2;
19 gpio2 = &gpio3;
20 gpio3 = &gpio4;
21 gpio4 = &gpio5;
22 gpio5 = &gpio6;
23 gpio6 = &gpio7;
80fa0584
SH		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 spi0 = &ecspi1;
33 spi1 = &ecspi2;
34 spi2 = &ecspi3;
35 spi3 = &ecspi4;
7d740f87
SG		 36 };
37
7d740f87
SG		 38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
41 #address-cells = <1>;
42 #size-cells = <1>;
43 interrupt-controller;
44 reg = <0x00a01000 0x1000>,
45 <0x00a00100 0x100>;
46 };
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
55 };
56
57 ckih1 {
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
60 };
61
62 osc {
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
65 };
66 };
67
68 soc {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
73 ranges;
74
f30fb03d 75 dma_apbh: dma-apbh@00110000 {
e5d0f9f5
HS		 76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
f30fb03d
SG		 78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
80 #dma-cells = <1>;
81 dma-channels = <4>;
0e87e043 82 clocks = <&clks 106>;
e5d0f9f5
HS		 83 };
84
be4ccfce 85 gpmi: gpmi-nand@00112000 {
0e87e043
SG		 86 compatible = "fsl,imx6q-gpmi-nand";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
c7aa12a6
SG		 91 interrupts = <0 15 0x04>;
92 interrupt-names = "bch";
0e87e043
SG		 93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
f30fb03d
SG		 97 dmas = <&dma_apbh 0>;
98 dma-names = "rx-tx";
0e87e043 99 status = "disabled";
cf922fa8
HS		 100 };
101
481fbe13
PZ		 102 ocram: sram@00900000 {
103 compatible = "mmio-sram";
104 reg = <0x00900000 0x3f000>;
105 clocks = <&clks 142>;
106 };
107
7d740f87 108 timer@00a00600 {
58458e03
MZ		 109 compatible = "arm,cortex-a9-twd-timer";
110 reg = <0x00a00600 0x20>;
111 interrupts = <1 13 0xf01>;
2bb4b70b 112 clocks = <&clks 15>;
7d740f87
SG		 113 };
114
115 L2: l2-cache@00a02000 {
116 compatible = "arm,pl310-cache";
117 reg = <0x00a02000 0x1000>;
118 interrupts = <0 92 0x04>;
119 cache-unified;
120 cache-level = <2>;
5a5ca56e
DB		 121 arm,tag-latency = <4 2 3>;
122 arm,data-latency = <4 2 3>;
7d740f87
SG		 123 };
124
218abe6f
DB		 125 pmu {
126 compatible = "arm,cortex-a9-pmu";
127 interrupts = <0 94 0x04>;
128 };
129
7d740f87
SG		 130 aips-bus@02000000 { /* AIPS1 */
131 compatible = "fsl,aips-bus", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 reg = <0x02000000 0x100000>;
135 ranges;
136
137 spba-bus@02000000 {
138 compatible = "fsl,spba-bus", "simple-bus";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 reg = <0x02000000 0x40000>;
142 ranges;
143
7b7d6727 144 spdif: spdif@02004000 {
7d740f87
SG		 145 reg = <0x02004000 0x4000>;
146 interrupts = <0 52 0x04>;
147 };
148
7b7d6727 149 ecspi1: ecspi@02008000 {
7d740f87
SG		 150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
153 reg = <0x02008000 0x4000>;
154 interrupts = <0 31 0x04>;
0e87e043
SG		 155 clocks = <&clks 112>, <&clks 112>;
156 clock-names = "ipg", "per";
7d740f87
SG		 157 status = "disabled";
158 };
159
7b7d6727 160 ecspi2: ecspi@0200c000 {
7d740f87
SG		 161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
164 reg = <0x0200c000 0x4000>;
165 interrupts = <0 32 0x04>;
0e87e043
SG		 166 clocks = <&clks 113>, <&clks 113>;
167 clock-names = "ipg", "per";
7d740f87
SG		 168 status = "disabled";
169 };
170
7b7d6727 171 ecspi3: ecspi@02010000 {
7d740f87
SG		 172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x02010000 0x4000>;
176 interrupts = <0 33 0x04>;
0e87e043
SG		 177 clocks = <&clks 114>, <&clks 114>;
178 clock-names = "ipg", "per";
7d740f87
SG		 179 status = "disabled";
180 };
181
7b7d6727 182 ecspi4: ecspi@02014000 {
7d740f87
SG		 183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02014000 0x4000>;
187 interrupts = <0 34 0x04>;
0e87e043
SG		 188 clocks = <&clks 115>, <&clks 115>;
189 clock-names = "ipg", "per";
7d740f87
SG		 190 status = "disabled";
191 };
192
0c456cfa 193 uart1: serial@02020000 {
7d740f87
SG		 194 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
195 reg = <0x02020000 0x4000>;
196 interrupts = <0 26 0x04>;
0e87e043
SG		 197 clocks = <&clks 160>, <&clks 161>;
198 clock-names = "ipg", "per";
72a5cebf
HS		 199 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
200 dma-names = "rx", "tx";
7d740f87
SG		 201 status = "disabled";
202 };
203
7b7d6727 204 esai: esai@02024000 {
7d740f87
SG		 205 reg = <0x02024000 0x4000>;
206 interrupts = <0 51 0x04>;
207 };
208
b1a5da8e
RZ		 209 ssi1: ssi@02028000 {
210 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 211 reg = <0x02028000 0x4000>;
212 interrupts = <0 46 0x04>;
0e87e043 213 clocks = <&clks 178>;
5da826ab
SG		 214 dmas = <&sdma 37 1 0>,
215 <&sdma 38 1 0>;
216 dma-names = "rx", "tx";
b1a5da8e
RZ		 217 fsl,fifo-depth = <15>;
218 fsl,ssi-dma-events = <38 37>;
219 status = "disabled";
7d740f87
SG		 220 };
221
b1a5da8e
RZ		 222 ssi2: ssi@0202c000 {
223 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 224 reg = <0x0202c000 0x4000>;
225 interrupts = <0 47 0x04>;
0e87e043 226 clocks = <&clks 179>;
5da826ab
SG		 227 dmas = <&sdma 41 1 0>,
228 <&sdma 42 1 0>;
229 dma-names = "rx", "tx";
b1a5da8e
RZ		 230 fsl,fifo-depth = <15>;
231 fsl,ssi-dma-events = <42 41>;
232 status = "disabled";
7d740f87
SG		 233 };
234
b1a5da8e
RZ		 235 ssi3: ssi@02030000 {
236 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 237 reg = <0x02030000 0x4000>;
238 interrupts = <0 48 0x04>;
0e87e043 239 clocks = <&clks 180>;
5da826ab
SG		 240 dmas = <&sdma 45 1 0>,
241 <&sdma 46 1 0>;
242 dma-names = "rx", "tx";
b1a5da8e
RZ		 243 fsl,fifo-depth = <15>;
244 fsl,ssi-dma-events = <46 45>;
245 status = "disabled";
7d740f87
SG		 246 };
247
7b7d6727 248 asrc: asrc@02034000 {
7d740f87
SG		 249 reg = <0x02034000 0x4000>;
250 interrupts = <0 50 0x04>;
251 };
252
253 spba@0203c000 {
254 reg = <0x0203c000 0x4000>;
255 };
256 };
257
7b7d6727 258 vpu: vpu@02040000 {
7d740f87
SG		 259 reg = <0x02040000 0x3c000>;
260 interrupts = <0 3 0x04 0 12 0x04>;
261 };
262
263 aipstz@0207c000 { /* AIPSTZ1 */
264 reg = <0x0207c000 0x4000>;
265 };
266
7b7d6727 267 pwm1: pwm@02080000 {
33b38587
SH		 268 #pwm-cells = <2>;
269 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 270 reg = <0x02080000 0x4000>;
271 interrupts = <0 83 0x04>;
33b38587
SH		 272 clocks = <&clks 62>, <&clks 145>;
273 clock-names = "ipg", "per";
7d740f87
SG		 274 };
275
7b7d6727 276 pwm2: pwm@02084000 {
33b38587
SH		 277 #pwm-cells = <2>;
278 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 279 reg = <0x02084000 0x4000>;
280 interrupts = <0 84 0x04>;
33b38587
SH		 281 clocks = <&clks 62>, <&clks 146>;
282 clock-names = "ipg", "per";
7d740f87
SG		 283 };
284
7b7d6727 285 pwm3: pwm@02088000 {
33b38587
SH		 286 #pwm-cells = <2>;
287 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 288 reg = <0x02088000 0x4000>;
289 interrupts = <0 85 0x04>;
33b38587
SH		 290 clocks = <&clks 62>, <&clks 147>;
291 clock-names = "ipg", "per";
7d740f87
SG		 292 };
293
7b7d6727 294 pwm4: pwm@0208c000 {
33b38587
SH		 295 #pwm-cells = <2>;
296 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 297 reg = <0x0208c000 0x4000>;
298 interrupts = <0 86 0x04>;
33b38587
SH		 299 clocks = <&clks 62>, <&clks 148>;
300 clock-names = "ipg", "per";
7d740f87
SG		 301 };
302
7b7d6727 303 can1: flexcan@02090000 {
0f225212 304 compatible = "fsl,imx6q-flexcan";
7d740f87
SG		 305 reg = <0x02090000 0x4000>;
306 interrupts = <0 110 0x04>;
0f225212
SH		 307 clocks = <&clks 108>, <&clks 109>;
308 clock-names = "ipg", "per";
7d740f87
SG		 309 };
310
7b7d6727 311 can2: flexcan@02094000 {
0f225212 312 compatible = "fsl,imx6q-flexcan";
7d740f87
SG		 313 reg = <0x02094000 0x4000>;
314 interrupts = <0 111 0x04>;
0f225212
SH		 315 clocks = <&clks 110>, <&clks 111>;
316 clock-names = "ipg", "per";
7d740f87
SG		 317 };
318
7b7d6727 319 gpt: gpt@02098000 {
97b108f9 320 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
7d740f87
SG		 321 reg = <0x02098000 0x4000>;
322 interrupts = <0 55 0x04>;
4efccadd
SH		 323 clocks = <&clks 119>, <&clks 120>;
324 clock-names = "ipg", "per";
7d740f87
SG		 325 };
326
4d191868 327 gpio1: gpio@0209c000 {
aeb27748 328 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 329 reg = <0x0209c000 0x4000>;
330 interrupts = <0 66 0x04 0 67 0x04>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
88cde8b7 334 #interrupt-cells = <2>;
7d740f87
SG		 335 };
336
4d191868 337 gpio2: gpio@020a0000 {
aeb27748 338 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 339 reg = <0x020a0000 0x4000>;
340 interrupts = <0 68 0x04 0 69 0x04>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
88cde8b7 344 #interrupt-cells = <2>;
7d740f87
SG		 345 };
346
4d191868 347 gpio3: gpio@020a4000 {
aeb27748 348 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 349 reg = <0x020a4000 0x4000>;
350 interrupts = <0 70 0x04 0 71 0x04>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
88cde8b7 354 #interrupt-cells = <2>;
7d740f87
SG		 355 };
356
4d191868 357 gpio4: gpio@020a8000 {
aeb27748 358 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 359 reg = <0x020a8000 0x4000>;
360 interrupts = <0 72 0x04 0 73 0x04>;
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
88cde8b7 364 #interrupt-cells = <2>;
7d740f87
SG		 365 };
366
4d191868 367 gpio5: gpio@020ac000 {
aeb27748 368 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 369 reg = <0x020ac000 0x4000>;
370 interrupts = <0 74 0x04 0 75 0x04>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
88cde8b7 374 #interrupt-cells = <2>;
7d740f87
SG		 375 };
376
4d191868 377 gpio6: gpio@020b0000 {
aeb27748 378 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 379 reg = <0x020b0000 0x4000>;
380 interrupts = <0 76 0x04 0 77 0x04>;
381 gpio-controller;
382 #gpio-cells = <2>;
383 interrupt-controller;
88cde8b7 384 #interrupt-cells = <2>;
7d740f87
SG		 385 };
386
4d191868 387 gpio7: gpio@020b4000 {
aeb27748 388 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 389 reg = <0x020b4000 0x4000>;
390 interrupts = <0 78 0x04 0 79 0x04>;
391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
88cde8b7 394 #interrupt-cells = <2>;
7d740f87
SG		 395 };
396
7b7d6727 397 kpp: kpp@020b8000 {
7d740f87
SG		 398 reg = <0x020b8000 0x4000>;
399 interrupts = <0 82 0x04>;
400 };
401
7b7d6727 402 wdog1: wdog@020bc000 {
7d740f87
SG		 403 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
404 reg = <0x020bc000 0x4000>;
405 interrupts = <0 80 0x04>;
0e87e043 406 clocks = <&clks 0>;
7d740f87
SG		 407 };
408
7b7d6727 409 wdog2: wdog@020c0000 {
7d740f87
SG		 410 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
411 reg = <0x020c0000 0x4000>;
412 interrupts = <0 81 0x04>;
0e87e043 413 clocks = <&clks 0>;
7d740f87
SG		 414 status = "disabled";
415 };
416
0e87e043 417 clks: ccm@020c4000 {
7d740f87
SG		 418 compatible = "fsl,imx6q-ccm";
419 reg = <0x020c4000 0x4000>;
420 interrupts = <0 87 0x04 0 88 0x04>;
0e87e043 421 #clock-cells = <1>;
7d740f87
SG		 422 };
423
baa64151
DA		 424 anatop: anatop@020c8000 {
425 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
7d740f87
SG		 426 reg = <0x020c8000 0x1000>;
427 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
a1e327e6
YCLP		 428
429 regulator-1p1@110 {
430 compatible = "fsl,anatop-regulator";
431 regulator-name = "vdd1p1";
432 regulator-min-microvolt = <800000>;
433 regulator-max-microvolt = <1375000>;
434 regulator-always-on;
435 anatop-reg-offset = <0x110>;
436 anatop-vol-bit-shift = <8>;
437 anatop-vol-bit-width = <5>;
438 anatop-min-bit-val = <4>;
439 anatop-min-voltage = <800000>;
440 anatop-max-voltage = <1375000>;
441 };
442
443 regulator-3p0@120 {
444 compatible = "fsl,anatop-regulator";
445 regulator-name = "vdd3p0";
446 regulator-min-microvolt = <2800000>;
447 regulator-max-microvolt = <3150000>;
448 regulator-always-on;
449 anatop-reg-offset = <0x120>;
450 anatop-vol-bit-shift = <8>;
451 anatop-vol-bit-width = <5>;
452 anatop-min-bit-val = <0>;
453 anatop-min-voltage = <2625000>;
454 anatop-max-voltage = <3400000>;
455 };
456
457 regulator-2p5@130 {
458 compatible = "fsl,anatop-regulator";
459 regulator-name = "vdd2p5";
460 regulator-min-microvolt = <2000000>;
461 regulator-max-microvolt = <2750000>;
462 regulator-always-on;
463 anatop-reg-offset = <0x130>;
464 anatop-vol-bit-shift = <8>;
465 anatop-vol-bit-width = <5>;
466 anatop-min-bit-val = <0>;
467 anatop-min-voltage = <2000000>;
468 anatop-max-voltage = <2750000>;
469 };
470
96574a6d 471 reg_arm: regulator-vddcore@140 {
a1e327e6
YCLP		 472 compatible = "fsl,anatop-regulator";
473 regulator-name = "cpu";
474 regulator-min-microvolt = <725000>;
475 regulator-max-microvolt = <1450000>;
476 regulator-always-on;
477 anatop-reg-offset = <0x140>;
478 anatop-vol-bit-shift = <0>;
479 anatop-vol-bit-width = <5>;
46743dd6
AH		 480 anatop-delay-reg-offset = <0x170>;
481 anatop-delay-bit-shift = <24>;
482 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 483 anatop-min-bit-val = <1>;
484 anatop-min-voltage = <725000>;
485 anatop-max-voltage = <1450000>;
486 };
487
96574a6d 488 reg_pu: regulator-vddpu@140 {
a1e327e6
YCLP		 489 compatible = "fsl,anatop-regulator";
490 regulator-name = "vddpu";
491 regulator-min-microvolt = <725000>;
492 regulator-max-microvolt = <1450000>;
493 regulator-always-on;
494 anatop-reg-offset = <0x140>;
495 anatop-vol-bit-shift = <9>;
496 anatop-vol-bit-width = <5>;
46743dd6
AH		 497 anatop-delay-reg-offset = <0x170>;
498 anatop-delay-bit-shift = <26>;
499 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 500 anatop-min-bit-val = <1>;
501 anatop-min-voltage = <725000>;
502 anatop-max-voltage = <1450000>;
503 };
504
96574a6d 505 reg_soc: regulator-vddsoc@140 {
a1e327e6
YCLP		 506 compatible = "fsl,anatop-regulator";
507 regulator-name = "vddsoc";
508 regulator-min-microvolt = <725000>;
509 regulator-max-microvolt = <1450000>;
510 regulator-always-on;
511 anatop-reg-offset = <0x140>;
512 anatop-vol-bit-shift = <18>;
513 anatop-vol-bit-width = <5>;
46743dd6
AH		 514 anatop-delay-reg-offset = <0x170>;
515 anatop-delay-bit-shift = <28>;
516 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 517 anatop-min-bit-val = <1>;
518 anatop-min-voltage = <725000>;
519 anatop-max-voltage = <1450000>;
520 };
7d740f87
SG		 521 };
522
3fe6373b
SG		 523 tempmon: tempmon {
524 compatible = "fsl,imx6q-tempmon";
525 interrupts = <0 49 0x04>;
526 fsl,tempmon = <&anatop>;
527 fsl,tempmon-data = <&ocotp>;
528 };
529
74bd88f7
RZ		 530 usbphy1: usbphy@020c9000 {
531 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 532 reg = <0x020c9000 0x1000>;
533 interrupts = <0 44 0x04>;
0e87e043 534 clocks = <&clks 182>;
7d740f87
SG		 535 };
536
74bd88f7
RZ		 537 usbphy2: usbphy@020ca000 {
538 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 539 reg = <0x020ca000 0x1000>;
540 interrupts = <0 45 0x04>;
0e87e043 541 clocks = <&clks 183>;
7d740f87
SG		 542 };
543
544 snvs@020cc000 {
c9250388
SG		 545 compatible = "fsl,sec-v4.0-mon", "simple-bus";
546 #address-cells = <1>;
547 #size-cells = <1>;
548 ranges = <0 0x020cc000 0x4000>;
549
550 snvs-rtc-lp@34 {
551 compatible = "fsl,sec-v4.0-mon-rtc-lp";
552 reg = <0x34 0x58>;
553 interrupts = <0 19 0x04 0 20 0x04>;
554 };
7d740f87
SG		 555 };
556
7b7d6727 557 epit1: epit@020d0000 { /* EPIT1 */
7d740f87
SG		 558 reg = <0x020d0000 0x4000>;
559 interrupts = <0 56 0x04>;
560 };
561
7b7d6727 562 epit2: epit@020d4000 { /* EPIT2 */
7d740f87
SG		 563 reg = <0x020d4000 0x4000>;
564 interrupts = <0 57 0x04>;
565 };
566
7b7d6727 567 src: src@020d8000 {
bd3d924d 568 compatible = "fsl,imx6q-src", "fsl,imx51-src";
7d740f87
SG		 569 reg = <0x020d8000 0x4000>;
570 interrupts = <0 91 0x04 0 96 0x04>;
09ebf366 571 #reset-cells = <1>;
7d740f87
SG		 572 };
573
7b7d6727 574 gpc: gpc@020dc000 {
7d740f87
SG		 575 compatible = "fsl,imx6q-gpc";
576 reg = <0x020dc000 0x4000>;
577 interrupts = <0 89 0x04 0 90 0x04>;
578 };
579
df37e0c0
DA		 580 gpr: iomuxc-gpr@020e0000 {
581 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
582 reg = <0x020e0000 0x38>;
583 };
584
c56009b2
SG		 585 iomuxc: iomuxc@020e0000 {
586 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
587 reg = <0x020e0000 0x4000>;
588
589 audmux {
590 pinctrl_audmux_1: audmux-1 {
591 fsl,pins = <
592 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
593 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
594 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
595 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
596 >;
597 };
598
599 pinctrl_audmux_2: audmux-2 {
600 fsl,pins = <
601 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
602 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
603 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
604 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
605 >;
606 };
b72ce929
SG		 607
608 pinctrl_audmux_3: audmux-3 {
609 fsl,pins = <
610 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
611 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
612 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
613 >;
614 };
c56009b2
SG		 615 };
616
617 ecspi1 {
618 pinctrl_ecspi1_1: ecspi1grp-1 {
619 fsl,pins = <
620 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
621 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
622 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
623 >;
624 };
625
626 pinctrl_ecspi1_2: ecspi1grp-2 {
627 fsl,pins = <
628 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
629 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
630 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
631 >;
632 };
633 };
634
635 ecspi3 {
636 pinctrl_ecspi3_1: ecspi3grp-1 {
637 fsl,pins = <
638 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
639 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
640 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
641 >;
642 };
643 };
644
645 enet {
646 pinctrl_enet_1: enetgrp-1 {
647 fsl,pins = <
648 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
649 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
650 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
651 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
652 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
653 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
654 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
655 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
656 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
657 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
658 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
659 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
660 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
661 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
662 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
663 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
664 >;
665 };
666
667 pinctrl_enet_2: enetgrp-2 {
668 fsl,pins = <
669 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
670 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
671 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
672 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
673 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
674 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
675 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
676 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
677 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
678 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
679 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
680 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
681 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
682 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
683 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
684 >;
685 };
686
687 pinctrl_enet_3: enetgrp-3 {
688 fsl,pins = <
689 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
690 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
691 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
692 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
693 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
694 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
695 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
696 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
697 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
698 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
699 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
700 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
701 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
702 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
703 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
704 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
705 >;
706 };
707 };
708
b72ce929
SG		 709 esai {
710 pinctrl_esai_1: esaigrp-1 {
711 fsl,pins = <
712 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
713 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
714 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
715 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
716 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
717 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
718 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
719 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
720 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
721 >;
722 };
723
724 pinctrl_esai_2: esaigrp-2 {
725 fsl,pins = <
726 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
727 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
728 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
729 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
730 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
731 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
732 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
733 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
734 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
735 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
736 >;
737 };
738 };
739
740 flexcan1 {
741 pinctrl_flexcan1_1: flexcan1grp-1 {
742 fsl,pins = <
743 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
744 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
745 >;
746 };
747
748 pinctrl_flexcan1_2: flexcan1grp-2 {
749 fsl,pins = <
750 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
751 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
752 >;
753 };
754 };
755
756 flexcan2 {
757 pinctrl_flexcan2_1: flexcan2grp-1 {
758 fsl,pins = <
759 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
760 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
761 >;
762 };
763 };
764
c56009b2
SG		 765 gpmi-nand {
766 pinctrl_gpmi_nand_1: gpmi-nand-1 {
767 fsl,pins = <
768 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
769 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
770 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
771 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
772 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
773 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
774 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
775 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
776 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
777 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
778 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
779 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
780 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
781 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
782 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
783 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
784 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
785 >;
786 };
787 };
788
b72ce929
SG		 789 hdmi_hdcp {
790 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
791 fsl,pins = <
792 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
793 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
794 >;
795 };
796
797 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
798 fsl,pins = <
799 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
800 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
801 >;
802 };
803
804 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
805 fsl,pins = <
806 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
807 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
808 >;
809 };
810 };
811
812 hdmi_cec {
813 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
814 fsl,pins = <
815 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
816 >;
817 };
818
819 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
820 fsl,pins = <
821 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
822 >;
823 };
824 };
825
c56009b2
SG		 826 i2c1 {
827 pinctrl_i2c1_1: i2c1grp-1 {
828 fsl,pins = <
829 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
830 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
831 >;
832 };
833
834 pinctrl_i2c1_2: i2c1grp-2 {
835 fsl,pins = <
836 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
837 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
838 >;
839 };
840 };
841
842 i2c2 {
843 pinctrl_i2c2_1: i2c2grp-1 {
844 fsl,pins = <
845 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
846 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
847 >;
848 };
849
850 pinctrl_i2c2_2: i2c2grp-2 {
851 fsl,pins = <
852 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
853 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
854 >;
855 };
b72ce929
SG		 856
857 pinctrl_i2c2_3: i2c2grp-3 {
858 fsl,pins = <
859 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
860 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
861 >;
862 };
c56009b2
SG		 863 };
864
865 i2c3 {
866 pinctrl_i2c3_1: i2c3grp-1 {
867 fsl,pins = <
868 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
869 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
870 >;
871 };
b72ce929
SG		 872
873 pinctrl_i2c3_2: i2c3grp-2 {
874 fsl,pins = <
875 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
876 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
877 >;
878 };
879
880 pinctrl_i2c3_3: i2c3grp-3 {
881 fsl,pins = <
882 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
883 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
884 >;
885 };
886
887 pinctrl_i2c3_4: i2c3grp-4 {
888 fsl,pins = <
889 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
890 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
891 >;
892 };
893 };
894
895 ipu1 {
896 pinctrl_ipu1_1: ipu1grp-1 {
897 fsl,pins = <
898 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
899 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
900 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
901 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
902 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
903 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
904 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
905 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
906 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
907 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
908 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
909 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
910 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
911 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
912 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
913 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
914 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
915 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
916 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
917 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
918 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
919 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
920 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
921 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
922 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
923 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
924 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
925 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
926 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
927 >;
928 };
929
930 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
931 fsl,pins = <
932 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
933 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
934 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
935 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
936 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
937 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
938 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
939 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
940 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
941 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
942 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
943 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
944 >;
945 };
946
947 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
948 fsl,pins = <
949 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
950 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
951 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
952 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
953 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
954 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
955 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
956 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
957 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
958 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
959 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
960 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
961 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
962 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
963 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
964 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
965 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
966 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
967 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
968 >;
969 };
970 };
971
972 mlb {
973 pinctrl_mlb_1: mlbgrp-1 {
974 fsl,pins = <
975 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
976 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
977 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
978 >;
979 };
980
981 pinctrl_mlb_2: mlbgrp-2 {
982 fsl,pins = <
983 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
984 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
985 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
986 >;
987 };
988 };
989
990 pwm0 {
991 pinctrl_pwm0_1: pwm0grp-1 {
992 fsl,pins = <
993 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
994 >;
995 };
996 };
997
998 pwm3 {
999 pinctrl_pwm3_1: pwm3grp-1 {
1000 fsl,pins = <
1001 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1002 >;
1003 };
1004 };
1005
1006 spdif {
1007 pinctrl_spdif_1: spdifgrp-1 {
1008 fsl,pins = <
1009 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1010 >;
1011 };
1012
1013 pinctrl_spdif_2: spdifgrp-2 {
1014 fsl,pins = <
1015 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1016 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1017 >;
1018 };
c56009b2
SG		 1019 };
1020
1021 uart1 {
1022 pinctrl_uart1_1: uart1grp-1 {
1023 fsl,pins = <
1024 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1025 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1026 >;
1027 };
1028 };
1029
1030 uart2 {
1031 pinctrl_uart2_1: uart2grp-1 {
1032 fsl,pins = <
1033 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1034 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1035 >;
1036 };
1037
1038 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1039 fsl,pins = <
1040 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1041 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1042 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1043 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1044 >;
1045 };
1046 };
1047
c2797984
HS		 1048 uart3 {
1049 pinctrl_uart3_1: uart3grp-1 {
1050 fsl,pins = <
1051 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1052 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1053 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1054 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1055 >;
1056 };
5ff88341
FE		 1057
1058 pinctrl_uart3_2: uart3grp-2 {
1059 fsl,pins = <
1060 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1061 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1062 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1063 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1064 >;
1065 };
c2797984
HS		 1066 };
1067
c56009b2
SG		 1068 uart4 {
1069 pinctrl_uart4_1: uart4grp-1 {
1070 fsl,pins = <
1071 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1072 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1073 >;
1074 };
1075 };
1076
1077 usbotg {
1078 pinctrl_usbotg_1: usbotggrp-1 {
1079 fsl,pins = <
1080 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1081 >;
1082 };
1083
1084 pinctrl_usbotg_2: usbotggrp-2 {
1085 fsl,pins = <
1086 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1087 >;
1088 };
1089 };
1090
b72ce929
SG		 1091 usbh2 {
1092 pinctrl_usbh2_1: usbh2grp-1 {
1093 fsl,pins = <
1094 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1095 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1096 >;
1097 };
1098
1099 pinctrl_usbh2_2: usbh2grp-2 {
1100 fsl,pins = <
1101 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1102 >;
1103 };
1104 };
1105
1106 usbh3 {
1107 pinctrl_usbh3_1: usbh3grp-1 {
1108 fsl,pins = <
1109 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1110 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1111 >;
1112 };
1113
1114 pinctrl_usbh3_2: usbh3grp-2 {
1115 fsl,pins = <
1116 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1117 >;
1118 };
1119 };
1120
26c3b65d
FE		 1121 usdhc1 {
1122 pinctrl_usdhc1_1: usdhc1grp-1 {
1123 fsl,pins = <
1124 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1125 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1126 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1127 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1128 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1129 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1130 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1131 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1132 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1133 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1134 >;
1135 };
1136
1137 pinctrl_usdhc1_2: usdhc1grp-2 {
1138 fsl,pins = <
1139 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1140 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1141 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1142 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1143 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1144 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1145 >;
1146 };
1147 };
1148
c56009b2
SG		 1149 usdhc2 {
1150 pinctrl_usdhc2_1: usdhc2grp-1 {
1151 fsl,pins = <
1152 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1153 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1154 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1155 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1156 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1157 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1158 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1159 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1160 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1161 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1162 >;
1163 };
1164
1165 pinctrl_usdhc2_2: usdhc2grp-2 {
1166 fsl,pins = <
1167 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1168 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1169 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1170 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1171 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1172 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1173 >;
1174 };
1175 };
1176
1177 usdhc3 {
1178 pinctrl_usdhc3_1: usdhc3grp-1 {
1179 fsl,pins = <
1180 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1181 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1182 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1183 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1184 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1185 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1186 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1187 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1188 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1189 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1190 >;
1191 };
1192
1193 pinctrl_usdhc3_2: usdhc3grp-2 {
1194 fsl,pins = <
1195 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1196 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1197 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1198 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1199 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1200 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1201 >;
1202 };
1203 };
1204
1205 usdhc4 {
1206 pinctrl_usdhc4_1: usdhc4grp-1 {
1207 fsl,pins = <
1208 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1209 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1210 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1211 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1212 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1213 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1214 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1215 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1216 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1217 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1218 >;
1219 };
1220
1221 pinctrl_usdhc4_2: usdhc4grp-2 {
1222 fsl,pins = <
1223 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1224 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1225 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1226 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1227 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1228 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1229 >;
1230 };
1231 };
1232
1233 weim {
1234 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1235 fsl,pins = <
1236 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1237 >;
1238 };
1239
1240 pinctrl_weim_nor_1: weim_norgrp-1 {
1241 fsl,pins = <
1242 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1243 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1244 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1245 /* data */
1246 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1247 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1248 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1249 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1250 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1251 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1252 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1253 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1254 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1255 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1256 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1257 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1258 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1259 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1260 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1261 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1262 /* address */
1263 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1264 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1265 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1266 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1267 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1268 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1269 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1270 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1271 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1272 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1273 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1274 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1275 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1276 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1277 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1278 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1279 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1280 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1281 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1282 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1283 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1284 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1285 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1286 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1287 >;
1288 };
1289 };
1290 };
1291
41c04342
ST		 1292 ldb: ldb@020e0008 {
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1295 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1296 gpr = <&gpr>;
1297 status = "disabled";
1298
1299 lvds-channel@0 {
1300 reg = <0>;
41c04342
ST		 1301 status = "disabled";
1302 };
1303
1304 lvds-channel@1 {
1305 reg = <1>;
41c04342
ST		 1306 status = "disabled";
1307 };
1308 };
1309
7b7d6727 1310 dcic1: dcic@020e4000 {
7d740f87
SG		 1311 reg = <0x020e4000 0x4000>;
1312 interrupts = <0 124 0x04>;
1313 };
1314
7b7d6727 1315 dcic2: dcic@020e8000 {
7d740f87
SG		 1316 reg = <0x020e8000 0x4000>;
1317 interrupts = <0 125 0x04>;
1318 };
1319
7b7d6727 1320 sdma: sdma@020ec000 {
7d740f87
SG		 1321 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1322 reg = <0x020ec000 0x4000>;
1323 interrupts = <0 2 0x04>;
0e87e043
SG		 1324 clocks = <&clks 155>, <&clks 155>;
1325 clock-names = "ipg", "ahb";
fb72bb21 1326 #dma-cells = <3>;
d6b9c591 1327 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
7d740f87
SG		 1328 };
1329 };
1330
1331 aips-bus@02100000 { /* AIPS2 */
1332 compatible = "fsl,aips-bus", "simple-bus";
1333 #address-cells = <1>;
1334 #size-cells = <1>;
1335 reg = <0x02100000 0x100000>;
1336 ranges;
1337
1338 caam@02100000 {
1339 reg = <0x02100000 0x40000>;
1340 interrupts = <0 105 0x04 0 106 0x04>;
1341 };
1342
1343 aipstz@0217c000 { /* AIPSTZ2 */
1344 reg = <0x0217c000 0x4000>;
1345 };
1346
7b7d6727 1347 usbotg: usb@02184000 {
74bd88f7
RZ		 1348 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1349 reg = <0x02184000 0x200>;
1350 interrupts = <0 43 0x04>;
0e87e043 1351 clocks = <&clks 162>;
74bd88f7 1352 fsl,usbphy = <&usbphy1>;
28342c61 1353 fsl,usbmisc = <&usbmisc 0>;
74bd88f7
RZ		 1354 status = "disabled";
1355 };
1356
7b7d6727 1357 usbh1: usb@02184200 {
74bd88f7
RZ		 1358 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1359 reg = <0x02184200 0x200>;
1360 interrupts = <0 40 0x04>;
0e87e043 1361 clocks = <&clks 162>;
74bd88f7 1362 fsl,usbphy = <&usbphy2>;
28342c61 1363 fsl,usbmisc = <&usbmisc 1>;
74bd88f7
RZ		 1364 status = "disabled";
1365 };
1366
7b7d6727 1367 usbh2: usb@02184400 {
74bd88f7
RZ		 1368 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1369 reg = <0x02184400 0x200>;
1370 interrupts = <0 41 0x04>;
0e87e043 1371 clocks = <&clks 162>;
28342c61 1372 fsl,usbmisc = <&usbmisc 2>;
74bd88f7
RZ		 1373 status = "disabled";
1374 };
1375
7b7d6727 1376 usbh3: usb@02184600 {
74bd88f7
RZ		 1377 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1378 reg = <0x02184600 0x200>;
1379 interrupts = <0 42 0x04>;
0e87e043 1380 clocks = <&clks 162>;
28342c61 1381 fsl,usbmisc = <&usbmisc 3>;
74bd88f7
RZ		 1382 status = "disabled";
1383 };
1384
60984bdf 1385 usbmisc: usbmisc@02184800 {
28342c61
RZ		 1386 #index-cells = <1>;
1387 compatible = "fsl,imx6q-usbmisc";
1388 reg = <0x02184800 0x200>;
1389 clocks = <&clks 162>;
1390 };
1391
7b7d6727 1392 fec: ethernet@02188000 {
7d740f87
SG		 1393 compatible = "fsl,imx6q-fec";
1394 reg = <0x02188000 0x4000>;
1395 interrupts = <0 118 0x04 0 119 0x04>;
8dd5c66b 1396 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
7629838c 1397 clock-names = "ipg", "ahb", "ptp";
7d740f87
SG		 1398 status = "disabled";
1399 };
1400
1401 mlb@0218c000 {
1402 reg = <0x0218c000 0x4000>;
1403 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1404 };
1405
7b7d6727 1406 usdhc1: usdhc@02190000 {
7d740f87
SG		 1407 compatible = "fsl,imx6q-usdhc";
1408 reg = <0x02190000 0x4000>;
1409 interrupts = <0 22 0x04>;
0e87e043
SG		 1410 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1411 clock-names = "ipg", "ahb", "per";
c104b6a2 1412 bus-width = <4>;
7d740f87
SG		 1413 status = "disabled";
1414 };
1415
7b7d6727 1416 usdhc2: usdhc@02194000 {
7d740f87
SG		 1417 compatible = "fsl,imx6q-usdhc";
1418 reg = <0x02194000 0x4000>;
1419 interrupts = <0 23 0x04>;
0e87e043
SG		 1420 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1421 clock-names = "ipg", "ahb", "per";
c104b6a2 1422 bus-width = <4>;
7d740f87
SG		 1423 status = "disabled";
1424 };
1425
7b7d6727 1426 usdhc3: usdhc@02198000 {
7d740f87
SG		 1427 compatible = "fsl,imx6q-usdhc";
1428 reg = <0x02198000 0x4000>;
1429 interrupts = <0 24 0x04>;
0e87e043
SG		 1430 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1431 clock-names = "ipg", "ahb", "per";
c104b6a2 1432 bus-width = <4>;
7d740f87
SG		 1433 status = "disabled";
1434 };
1435
7b7d6727 1436 usdhc4: usdhc@0219c000 {
7d740f87
SG		 1437 compatible = "fsl,imx6q-usdhc";
1438 reg = <0x0219c000 0x4000>;
1439 interrupts = <0 25 0x04>;
0e87e043
SG		 1440 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1441 clock-names = "ipg", "ahb", "per";
c104b6a2 1442 bus-width = <4>;
7d740f87
SG		 1443 status = "disabled";
1444 };
1445
7b7d6727 1446 i2c1: i2c@021a0000 {
7d740f87
SG		 1447 #address-cells = <1>;
1448 #size-cells = <0>;
5bdfba29 1449 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 1450 reg = <0x021a0000 0x4000>;
1451 interrupts = <0 36 0x04>;
0e87e043 1452 clocks = <&clks 125>;
7d740f87
SG		 1453 status = "disabled";
1454 };
1455
7b7d6727 1456 i2c2: i2c@021a4000 {
7d740f87
SG		 1457 #address-cells = <1>;
1458 #size-cells = <0>;
5bdfba29 1459 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 1460 reg = <0x021a4000 0x4000>;
1461 interrupts = <0 37 0x04>;
0e87e043 1462 clocks = <&clks 126>;
7d740f87
SG		 1463 status = "disabled";
1464 };
1465
7b7d6727 1466 i2c3: i2c@021a8000 {
7d740f87
SG		 1467 #address-cells = <1>;
1468 #size-cells = <0>;
5bdfba29 1469 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 1470 reg = <0x021a8000 0x4000>;
1471 interrupts = <0 38 0x04>;
0e87e043 1472 clocks = <&clks 127>;
7d740f87
SG		 1473 status = "disabled";
1474 };
1475
1476 romcp@021ac000 {
1477 reg = <0x021ac000 0x4000>;
1478 };
1479
7b7d6727 1480 mmdc0: mmdc@021b0000 { /* MMDC0 */
7d740f87
SG		 1481 compatible = "fsl,imx6q-mmdc";
1482 reg = <0x021b0000 0x4000>;
1483 };
1484
7b7d6727 1485 mmdc1: mmdc@021b4000 { /* MMDC1 */
7d740f87
SG		 1486 reg = <0x021b4000 0x4000>;
1487 };
1488
05e3f8e7
HS		 1489 weim: weim@021b8000 {
1490 compatible = "fsl,imx6q-weim";
7d740f87
SG		 1491 reg = <0x021b8000 0x4000>;
1492 interrupts = <0 14 0x04>;
05e3f8e7 1493 clocks = <&clks 196>;
7d740f87
SG		 1494 };
1495
3fe6373b
SG		 1496 ocotp: ocotp@021bc000 {
1497 compatible = "fsl,imx6q-ocotp", "syscon";
7d740f87
SG		 1498 reg = <0x021bc000 0x4000>;
1499 };
1500
7d740f87
SG		 1501 tzasc@021d0000 { /* TZASC1 */
1502 reg = <0x021d0000 0x4000>;
1503 interrupts = <0 108 0x04>;
1504 };
1505
1506 tzasc@021d4000 { /* TZASC2 */
1507 reg = <0x021d4000 0x4000>;
1508 interrupts = <0 109 0x04>;
1509 };
1510
7b7d6727 1511 audmux: audmux@021d8000 {
f965cd55 1512 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 1513 reg = <0x021d8000 0x4000>;
f965cd55 1514 status = "disabled";
7d740f87
SG		 1515 };
1516
1517 mipi@021dc000 { /* MIPI-CSI */
1518 reg = <0x021dc000 0x4000>;
1519 };
1520
1521 mipi@021e0000 { /* MIPI-DSI */
1522 reg = <0x021e0000 0x4000>;
1523 };
1524
1525 vdoa@021e4000 {
1526 reg = <0x021e4000 0x4000>;
1527 interrupts = <0 18 0x04>;
1528 };
1529
0c456cfa 1530 uart2: serial@021e8000 {
7d740f87
SG		 1531 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1532 reg = <0x021e8000 0x4000>;
1533 interrupts = <0 27 0x04>;
0e87e043
SG		 1534 clocks = <&clks 160>, <&clks 161>;
1535 clock-names = "ipg", "per";
72a5cebf
HS		 1536 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1537 dma-names = "rx", "tx";
7d740f87
SG		 1538 status = "disabled";
1539 };
1540
0c456cfa 1541 uart3: serial@021ec000 {
7d740f87
SG		 1542 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1543 reg = <0x021ec000 0x4000>;
1544 interrupts = <0 28 0x04>;
0e87e043
SG		 1545 clocks = <&clks 160>, <&clks 161>;
1546 clock-names = "ipg", "per";
72a5cebf
HS		 1547 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1548 dma-names = "rx", "tx";
7d740f87
SG		 1549 status = "disabled";
1550 };
1551
0c456cfa 1552 uart4: serial@021f0000 {
7d740f87
SG		 1553 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1554 reg = <0x021f0000 0x4000>;
1555 interrupts = <0 29 0x04>;
0e87e043
SG		 1556 clocks = <&clks 160>, <&clks 161>;
1557 clock-names = "ipg", "per";
72a5cebf
HS		 1558 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1559 dma-names = "rx", "tx";
7d740f87
SG		 1560 status = "disabled";
1561 };
1562
0c456cfa 1563 uart5: serial@021f4000 {
7d740f87
SG		 1564 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1565 reg = <0x021f4000 0x4000>;
1566 interrupts = <0 30 0x04>;
0e87e043
SG		 1567 clocks = <&clks 160>, <&clks 161>;
1568 clock-names = "ipg", "per";
72a5cebf
HS		 1569 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1570 dma-names = "rx", "tx";
7d740f87
SG		 1571 status = "disabled";
1572 };
1573 };
91660d74
SH		 1574
1575 ipu1: ipu@02400000 {
1576 #crtc-cells = <1>;
1577 compatible = "fsl,imx6q-ipu";
1578 reg = <0x02400000 0x400000>;
1579 interrupts = <0 6 0x4 0 5 0x4>;
1580 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1581 clock-names = "bus", "di0", "di1";
09ebf366 1582 resets = <&src 2>;
91660d74 1583 };
7d740f87
SG		 1584 };
1585};
Linux kernel - Deliverables
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