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ARM: imx25-pinfunc: remove SION from all modes
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
8888f651 13#include <dt-bindings/clock/imx6qdl-clock.h>
07134a36
LS		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
36dffd8f 16#include "skeleton.dtsi"
7d740f87
SG		 17
18/ {
19 aliases {
22970070 20 ethernet0 = &fec;
5f8fbc2c
LW		 21 can0 = &can1;
22 can1 = &can2;
5230f8fe
SG		 23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
80fa0584
SH		 30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
41beef39 33 ipu0 = &ipu1;
fb06d65c
SH		 34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
36 mmc2 = &usdhc3;
37 mmc3 = &usdhc4;
80fa0584
SH		 38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 spi0 = &ecspi1;
44 spi1 = &ecspi2;
45 spi2 = &ecspi3;
46 spi3 = &ecspi4;
8189c51f
PC		 47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
7d740f87
SG		 49 };
50
7d740f87
SG		 51 clocks {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 ckil {
56 compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043 57 #clock-cells = <0>;
7d740f87
SG		 58 clock-frequency = <32768>;
59 };
60
61 ckih1 {
62 compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043 63 #clock-cells = <0>;
7d740f87
SG		 64 clock-frequency = <0>;
65 };
66
67 osc {
68 compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043 69 #clock-cells = <0>;
7d740f87
SG		 70 clock-frequency = <24000000>;
71 };
72 };
73
74 soc {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "simple-bus";
b923ff6a 78 interrupt-parent = <&gpc>;
7d740f87
SG		 79 ranges;
80
f30fb03d 81 dma_apbh: dma-apbh@00110000 {
e5d0f9f5
HS		 82 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
83 reg = <0x00110000 0x2000>;
275c08b5
TK		 84 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
85 <0 13 IRQ_TYPE_LEVEL_HIGH>,
86 <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 <0 13 IRQ_TYPE_LEVEL_HIGH>;
f30fb03d
SG		 88 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
89 #dma-cells = <1>;
90 dma-channels = <4>;
8888f651 91 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
e5d0f9f5
HS		 92 };
93
be4ccfce 94 gpmi: gpmi-nand@00112000 {
0e87e043
SG		 95 compatible = "fsl,imx6q-gpmi-nand";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
99 reg-names = "gpmi-nand", "bch";
275c08b5 100 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
c7aa12a6 101 interrupt-names = "bch";
8888f651
SG		 102 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
103 <&clks IMX6QDL_CLK_GPMI_APB>,
104 <&clks IMX6QDL_CLK_GPMI_BCH>,
105 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
106 <&clks IMX6QDL_CLK_PER1_BCH>;
0e87e043
SG		 107 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
108 "gpmi_bch_apb", "per1_bch";
f30fb03d
SG		 109 dmas = <&dma_apbh 0>;
110 dma-names = "rx-tx";
0e87e043 111 status = "disabled";
cf922fa8
HS		 112 };
113
ac4af82b
LS		 114 hdmi: hdmi@0120000 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 reg = <0x00120000 0x9000>;
118 interrupts = <0 115 0x04>;
119 gpr = <&gpr>;
120 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
121 <&clks IMX6QDL_CLK_HDMI_ISFR>;
122 clock-names = "iahb", "isfr";
123 status = "disabled";
124
125 port@0 {
126 reg = <0>;
127
128 hdmi_mux_0: endpoint {
129 remote-endpoint = <&ipu1_di0_hdmi>;
130 };
131 };
132
133 port@1 {
134 reg = <1>;
135
136 hdmi_mux_1: endpoint {
137 remote-endpoint = <&ipu1_di1_hdmi>;
138 };
139 };
140 };
141
419e202b
LS		 142 gpu_3d: gpu@00130000 {
143 compatible = "vivante,gc";
144 reg = <0x00130000 0x4000>;
145 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
147 <&clks IMX6QDL_CLK_GPU3D_CORE>,
148 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
149 clock-names = "bus", "core", "shader";
150 power-domains = <&gpc 1>;
151 };
152
153 gpu_2d: gpu@00134000 {
154 compatible = "vivante,gc";
155 reg = <0x00134000 0x4000>;
156 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
158 <&clks IMX6QDL_CLK_GPU2D_CORE>;
159 clock-names = "bus", "core";
160 power-domains = <&gpc 1>;
161 };
162
7d740f87 163 timer@00a00600 {
58458e03
MZ		 164 compatible = "arm,cortex-a9-twd-timer";
165 reg = <0x00a00600 0x20>;
166 interrupts = <1 13 0xf01>;
b923ff6a 167 interrupt-parent = <&intc>;
8888f651 168 clocks = <&clks IMX6QDL_CLK_TWD>;
7d740f87
SG		 169 };
170
67157882
LS		 171 intc: interrupt-controller@00a01000 {
172 compatible = "arm,cortex-a9-gic";
173 #interrupt-cells = <3>;
174 interrupt-controller;
175 reg = <0x00a01000 0x1000>,
176 <0x00a00100 0x100>;
177 interrupt-parent = <&intc>;
178 };
179
7d740f87
SG		 180 L2: l2-cache@00a02000 {
181 compatible = "arm,pl310-cache";
182 reg = <0x00a02000 0x1000>;
275c08b5 183 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 184 cache-unified;
185 cache-level = <2>;
5a5ca56e
DB		 186 arm,tag-latency = <4 2 3>;
187 arm,data-latency = <4 2 3>;
7d740f87
SG		 188 };
189
3a57291f
SC		 190 pcie: pcie@0x01000000 {
191 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
fcd17303
LS		 192 reg = <0x01ffc000 0x04000>,
193 <0x01f00000 0x80000>;
194 reg-names = "dbi", "config";
3a57291f
SC		 195 #address-cells = <3>;
196 #size-cells = <2>;
197 device_type = "pci";
d9cf0a12 198 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
3a57291f
SC		 199 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
200 num-lanes = <1>;
92a7eb7c
LS		 201 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "msi";
07134a36
LS		 203 #interrupt-cells = <1>;
204 interrupt-map-mask = <0 0 0 0x7>;
1a9fa190
LS		 205 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
206 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
207 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
208 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 209 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
210 <&clks IMX6QDL_CLK_LVDS1_GATE>,
211 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
92a7eb7c 212 clock-names = "pcie", "pcie_bus", "pcie_phy";
3a57291f
SC		 213 status = "disabled";
214 };
215
218abe6f
DB		 216 pmu {
217 compatible = "arm,cortex-a9-pmu";
275c08b5 218 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
218abe6f
DB		 219 };
220
7d740f87
SG		 221 aips-bus@02000000 { /* AIPS1 */
222 compatible = "fsl,aips-bus", "simple-bus";
223 #address-cells = <1>;
224 #size-cells = <1>;
225 reg = <0x02000000 0x100000>;
226 ranges;
227
228 spba-bus@02000000 {
229 compatible = "fsl,spba-bus", "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 reg = <0x02000000 0x40000>;
233 ranges;
234
7b7d6727 235 spdif: spdif@02004000 {
c9d96df2 236 compatible = "fsl,imx35-spdif";
7d740f87 237 reg = <0x02004000 0x4000>;
275c08b5 238 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
c9d96df2
FE		 239 dmas = <&sdma 14 18 0>,
240 <&sdma 15 18 0>;
241 dma-names = "rx", "tx";
833f2cbf
SW		 242 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
243 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
244 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
245 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
246 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
c9d96df2
FE		 247 clock-names = "core", "rxtx0",
248 "rxtx1", "rxtx2",
249 "rxtx3", "rxtx4",
250 "rxtx5", "rxtx6",
09d3059a 251 "rxtx7", "spba";
c9d96df2 252 status = "disabled";
7d740f87
SG		 253 };
254
7b7d6727 255 ecspi1: ecspi@02008000 {
7d740f87
SG		 256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
259 reg = <0x02008000 0x4000>;
275c08b5 260 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 261 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
262 <&clks IMX6QDL_CLK_ECSPI1>;
0e87e043 263 clock-names = "ipg", "per";
dd4b487b 264 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
b3810c3d 265 dma-names = "rx", "tx";
7d740f87
SG		 266 status = "disabled";
267 };
268
7b7d6727 269 ecspi2: ecspi@0200c000 {
7d740f87
SG		 270 #address-cells = <1>;
271 #size-cells = <0>;
272 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
273 reg = <0x0200c000 0x4000>;
275c08b5 274 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 275 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
276 <&clks IMX6QDL_CLK_ECSPI2>;
0e87e043 277 clock-names = "ipg", "per";
dd4b487b 278 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
b3810c3d 279 dma-names = "rx", "tx";
7d740f87
SG		 280 status = "disabled";
281 };
282
7b7d6727 283 ecspi3: ecspi@02010000 {
7d740f87
SG		 284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
287 reg = <0x02010000 0x4000>;
275c08b5 288 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 289 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
290 <&clks IMX6QDL_CLK_ECSPI3>;
0e87e043 291 clock-names = "ipg", "per";
dd4b487b 292 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
b3810c3d 293 dma-names = "rx", "tx";
7d740f87
SG		 294 status = "disabled";
295 };
296
7b7d6727 297 ecspi4: ecspi@02014000 {
7d740f87
SG		 298 #address-cells = <1>;
299 #size-cells = <0>;
300 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
301 reg = <0x02014000 0x4000>;
275c08b5 302 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 303 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
304 <&clks IMX6QDL_CLK_ECSPI4>;
0e87e043 305 clock-names = "ipg", "per";
dd4b487b 306 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
b3810c3d 307 dma-names = "rx", "tx";
7d740f87
SG		 308 status = "disabled";
309 };
310
0c456cfa 311 uart1: serial@02020000 {
7d740f87
SG		 312 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
313 reg = <0x02020000 0x4000>;
275c08b5 314 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 315 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
316 <&clks IMX6QDL_CLK_UART_SERIAL>;
0e87e043 317 clock-names = "ipg", "per";
72a5cebf
HS		 318 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
319 dma-names = "rx", "tx";
7d740f87
SG		 320 status = "disabled";
321 };
322
7b7d6727 323 esai: esai@02024000 {
97dae859
SW		 324 #sound-dai-cells = <0>;
325 compatible = "fsl,imx35-esai";
7d740f87 326 reg = <0x02024000 0x4000>;
275c08b5 327 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
97dae859
SW		 328 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
329 <&clks IMX6QDL_CLK_ESAI_MEM>,
330 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
331 <&clks IMX6QDL_CLK_ESAI_IPG>,
332 <&clks IMX6QDL_CLK_SPBA>;
09d3059a 333 clock-names = "core", "mem", "extal", "fsys", "spba";
97dae859
SW		 334 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
335 dma-names = "rx", "tx";
336 status = "disabled";
7d740f87
SG		 337 };
338
b1a5da8e 339 ssi1: ssi@02028000 {
6ff7f51e 340 #sound-dai-cells = <0>;
98ea6ad2 341 compatible = "fsl,imx6q-ssi",
4c03527e 342 "fsl,imx51-ssi";
7d740f87 343 reg = <0x02028000 0x4000>;
275c08b5 344 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
935632e9
SW		 345 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
346 <&clks IMX6QDL_CLK_SSI1>;
347 clock-names = "ipg", "baud";
5da826ab
SG		 348 dmas = <&sdma 37 1 0>,
349 <&sdma 38 1 0>;
350 dma-names = "rx", "tx";
b1a5da8e 351 fsl,fifo-depth = <15>;
b1a5da8e 352 status = "disabled";
7d740f87
SG		 353 };
354
b1a5da8e 355 ssi2: ssi@0202c000 {
6ff7f51e 356 #sound-dai-cells = <0>;
98ea6ad2 357 compatible = "fsl,imx6q-ssi",
4c03527e 358 "fsl,imx51-ssi";
7d740f87 359 reg = <0x0202c000 0x4000>;
275c08b5 360 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
935632e9
SW		 361 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
362 <&clks IMX6QDL_CLK_SSI2>;
363 clock-names = "ipg", "baud";
5da826ab
SG		 364 dmas = <&sdma 41 1 0>,
365 <&sdma 42 1 0>;
366 dma-names = "rx", "tx";
b1a5da8e 367 fsl,fifo-depth = <15>;
b1a5da8e 368 status = "disabled";
7d740f87
SG		 369 };
370
b1a5da8e 371 ssi3: ssi@02030000 {
6ff7f51e 372 #sound-dai-cells = <0>;
98ea6ad2 373 compatible = "fsl,imx6q-ssi",
4c03527e 374 "fsl,imx51-ssi";
7d740f87 375 reg = <0x02030000 0x4000>;
275c08b5 376 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
935632e9
SW		 377 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
378 <&clks IMX6QDL_CLK_SSI3>;
379 clock-names = "ipg", "baud";
5da826ab
SG		 380 dmas = <&sdma 45 1 0>,
381 <&sdma 46 1 0>;
382 dma-names = "rx", "tx";
b1a5da8e 383 fsl,fifo-depth = <15>;
b1a5da8e 384 status = "disabled";
7d740f87
SG		 385 };
386
7b7d6727 387 asrc: asrc@02034000 {
97dae859 388 compatible = "fsl,imx53-asrc";
7d740f87 389 reg = <0x02034000 0x4000>;
275c08b5 390 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
97dae859
SW		 391 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
392 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
393 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
394 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
395 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
396 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
397 <&clks IMX6QDL_CLK_SPBA>;
398 clock-names = "mem", "ipg", "asrck_0",
399 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
400 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
401 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
09d3059a 402 "asrck_d", "asrck_e", "asrck_f", "spba";
97dae859
SW		 403 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
404 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
405 dma-names = "rxa", "rxb", "rxc",
406 "txa", "txb", "txc";
407 fsl,asrc-rate = <48000>;
408 fsl,asrc-width = <16>;
409 status = "okay";
7d740f87
SG		 410 };
411
412 spba@0203c000 {
413 reg = <0x0203c000 0x4000>;
414 };
415 };
416
7b7d6727 417 vpu: vpu@02040000 {
a04a0b6f 418 compatible = "cnm,coda960";
7d740f87 419 reg = <0x02040000 0x3c000>;
b2faf1a1
PZ		 420 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
421 <0 3 IRQ_TYPE_LEVEL_HIGH>;
a04a0b6f
PZ		 422 interrupt-names = "bit", "jpeg";
423 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
c9997ba2
FE		 424 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
425 clock-names = "per", "ahb";
29eea64c 426 power-domains = <&gpc 1>;
a04a0b6f
PZ		 427 resets = <&src 1>;
428 iram = <&ocram>;
7d740f87
SG		 429 };
430
431 aipstz@0207c000 { /* AIPSTZ1 */
432 reg = <0x0207c000 0x4000>;
433 };
434
7b7d6727 435 pwm1: pwm@02080000 {
33b38587
SH		 436 #pwm-cells = <2>;
437 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 438 reg = <0x02080000 0x4000>;
275c08b5 439 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 440 clocks = <&clks IMX6QDL_CLK_IPG>,
441 <&clks IMX6QDL_CLK_PWM1>;
33b38587 442 clock-names = "ipg", "per";
e2675266 443 status = "disabled";
7d740f87
SG		 444 };
445
7b7d6727 446 pwm2: pwm@02084000 {
33b38587
SH		 447 #pwm-cells = <2>;
448 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 449 reg = <0x02084000 0x4000>;
275c08b5 450 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 451 clocks = <&clks IMX6QDL_CLK_IPG>,
452 <&clks IMX6QDL_CLK_PWM2>;
33b38587 453 clock-names = "ipg", "per";
e2675266 454 status = "disabled";
7d740f87
SG		 455 };
456
7b7d6727 457 pwm3: pwm@02088000 {
33b38587
SH		 458 #pwm-cells = <2>;
459 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 460 reg = <0x02088000 0x4000>;
275c08b5 461 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 462 clocks = <&clks IMX6QDL_CLK_IPG>,
463 <&clks IMX6QDL_CLK_PWM3>;
33b38587 464 clock-names = "ipg", "per";
e2675266 465 status = "disabled";
7d740f87
SG		 466 };
467
7b7d6727 468 pwm4: pwm@0208c000 {
33b38587
SH		 469 #pwm-cells = <2>;
470 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 471 reg = <0x0208c000 0x4000>;
275c08b5 472 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 473 clocks = <&clks IMX6QDL_CLK_IPG>,
474 <&clks IMX6QDL_CLK_PWM4>;
33b38587 475 clock-names = "ipg", "per";
e2675266 476 status = "disabled";
7d740f87
SG		 477 };
478
7b7d6727 479 can1: flexcan@02090000 {
0f225212 480 compatible = "fsl,imx6q-flexcan";
7d740f87 481 reg = <0x02090000 0x4000>;
275c08b5 482 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 483 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
484 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
0f225212 485 clock-names = "ipg", "per";
a1135337 486 status = "disabled";
7d740f87
SG		 487 };
488
7b7d6727 489 can2: flexcan@02094000 {
0f225212 490 compatible = "fsl,imx6q-flexcan";
7d740f87 491 reg = <0x02094000 0x4000>;
275c08b5 492 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 493 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
494 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
0f225212 495 clock-names = "ipg", "per";
a1135337 496 status = "disabled";
7d740f87
SG		 497 };
498
7b7d6727 499 gpt: gpt@02098000 {
97b108f9 500 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
7d740f87 501 reg = <0x02098000 0x4000>;
275c08b5 502 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
8888f651 503 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
2b2244a3
AH		 504 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
505 <&clks IMX6QDL_CLK_GPT_3M>;
506 clock-names = "ipg", "per", "osc_per";
7d740f87
SG		 507 };
508
4d191868 509 gpio1: gpio@0209c000 {
aeb27748 510 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 511 reg = <0x0209c000 0x4000>;
275c08b5
TK		 512 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
513 <0 67 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-controller;
88cde8b7 517 #interrupt-cells = <2>;
7d740f87
SG		 518 };
519
4d191868 520 gpio2: gpio@020a0000 {
aeb27748 521 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 522 reg = <0x020a0000 0x4000>;
275c08b5
TK		 523 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
524 <0 69 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 525 gpio-controller;
526 #gpio-cells = <2>;
527 interrupt-controller;
88cde8b7 528 #interrupt-cells = <2>;
7d740f87
SG		 529 };
530
4d191868 531 gpio3: gpio@020a4000 {
aeb27748 532 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 533 reg = <0x020a4000 0x4000>;
275c08b5
TK		 534 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
535 <0 71 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 536 gpio-controller;
537 #gpio-cells = <2>;
538 interrupt-controller;
88cde8b7 539 #interrupt-cells = <2>;
7d740f87
SG		 540 };
541
4d191868 542 gpio4: gpio@020a8000 {
aeb27748 543 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 544 reg = <0x020a8000 0x4000>;
275c08b5
TK		 545 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
546 <0 73 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 547 gpio-controller;
548 #gpio-cells = <2>;
549 interrupt-controller;
88cde8b7 550 #interrupt-cells = <2>;
7d740f87
SG		 551 };
552
4d191868 553 gpio5: gpio@020ac000 {
aeb27748 554 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 555 reg = <0x020ac000 0x4000>;
275c08b5
TK		 556 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
557 <0 75 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 558 gpio-controller;
559 #gpio-cells = <2>;
560 interrupt-controller;
88cde8b7 561 #interrupt-cells = <2>;
7d740f87
SG		 562 };
563
4d191868 564 gpio6: gpio@020b0000 {
aeb27748 565 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 566 reg = <0x020b0000 0x4000>;
275c08b5
TK		 567 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
568 <0 77 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 569 gpio-controller;
570 #gpio-cells = <2>;
571 interrupt-controller;
88cde8b7 572 #interrupt-cells = <2>;
7d740f87
SG		 573 };
574
4d191868 575 gpio7: gpio@020b4000 {
aeb27748 576 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 577 reg = <0x020b4000 0x4000>;
275c08b5
TK		 578 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
579 <0 79 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 580 gpio-controller;
581 #gpio-cells = <2>;
582 interrupt-controller;
88cde8b7 583 #interrupt-cells = <2>;
7d740f87
SG		 584 };
585
7b7d6727 586 kpp: kpp@020b8000 {
36d3a8f0 587 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
7d740f87 588 reg = <0x020b8000 0x4000>;
275c08b5 589 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
8888f651 590 clocks = <&clks IMX6QDL_CLK_IPG>;
1b6f2368 591 status = "disabled";
7d740f87
SG		 592 };
593
7b7d6727 594 wdog1: wdog@020bc000 {
7d740f87
SG		 595 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
596 reg = <0x020bc000 0x4000>;
275c08b5 597 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
8888f651 598 clocks = <&clks IMX6QDL_CLK_DUMMY>;
7d740f87
SG		 599 };
600
7b7d6727 601 wdog2: wdog@020c0000 {
7d740f87
SG		 602 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
603 reg = <0x020c0000 0x4000>;
275c08b5 604 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
8888f651 605 clocks = <&clks IMX6QDL_CLK_DUMMY>;
7d740f87
SG		 606 status = "disabled";
607 };
608
0e87e043 609 clks: ccm@020c4000 {
7d740f87
SG		 610 compatible = "fsl,imx6q-ccm";
611 reg = <0x020c4000 0x4000>;
275c08b5
TK		 612 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
613 <0 88 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 614 #clock-cells = <1>;
7d740f87
SG		 615 };
616
baa64151
DA		 617 anatop: anatop@020c8000 {
618 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
7d740f87 619 reg = <0x020c8000 0x1000>;
275c08b5
TK		 620 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
621 <0 54 IRQ_TYPE_LEVEL_HIGH>,
622 <0 127 IRQ_TYPE_LEVEL_HIGH>;
a1e327e6 623
c77ebb45 624 regulator-1p1 {
a1e327e6
YCLP		 625 compatible = "fsl,anatop-regulator";
626 regulator-name = "vdd1p1";
627 regulator-min-microvolt = <800000>;
628 regulator-max-microvolt = <1375000>;
629 regulator-always-on;
630 anatop-reg-offset = <0x110>;
631 anatop-vol-bit-shift = <8>;
632 anatop-vol-bit-width = <5>;
633 anatop-min-bit-val = <4>;
634 anatop-min-voltage = <800000>;
635 anatop-max-voltage = <1375000>;
636 };
637
c77ebb45 638 regulator-3p0 {
a1e327e6
YCLP		 639 compatible = "fsl,anatop-regulator";
640 regulator-name = "vdd3p0";
641 regulator-min-microvolt = <2800000>;
642 regulator-max-microvolt = <3150000>;
643 regulator-always-on;
644 anatop-reg-offset = <0x120>;
645 anatop-vol-bit-shift = <8>;
646 anatop-vol-bit-width = <5>;
647 anatop-min-bit-val = <0>;
648 anatop-min-voltage = <2625000>;
649 anatop-max-voltage = <3400000>;
650 };
651
c77ebb45 652 regulator-2p5 {
a1e327e6
YCLP		 653 compatible = "fsl,anatop-regulator";
654 regulator-name = "vdd2p5";
655 regulator-min-microvolt = <2000000>;
656 regulator-max-microvolt = <2750000>;
657 regulator-always-on;
658 anatop-reg-offset = <0x130>;
659 anatop-vol-bit-shift = <8>;
660 anatop-vol-bit-width = <5>;
661 anatop-min-bit-val = <0>;
662 anatop-min-voltage = <2000000>;
663 anatop-max-voltage = <2750000>;
664 };
665
c77ebb45 666 reg_arm: regulator-vddcore {
a1e327e6 667 compatible = "fsl,anatop-regulator";
118c98a6 668 regulator-name = "vddarm";
a1e327e6
YCLP		 669 regulator-min-microvolt = <725000>;
670 regulator-max-microvolt = <1450000>;
671 regulator-always-on;
672 anatop-reg-offset = <0x140>;
673 anatop-vol-bit-shift = <0>;
674 anatop-vol-bit-width = <5>;
46743dd6
AH		 675 anatop-delay-reg-offset = <0x170>;
676 anatop-delay-bit-shift = <24>;
677 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 678 anatop-min-bit-val = <1>;
679 anatop-min-voltage = <725000>;
680 anatop-max-voltage = <1450000>;
681 };
682
c77ebb45 683 reg_pu: regulator-vddpu {
a1e327e6
YCLP		 684 compatible = "fsl,anatop-regulator";
685 regulator-name = "vddpu";
686 regulator-min-microvolt = <725000>;
687 regulator-max-microvolt = <1450000>;
40130d32 688 regulator-enable-ramp-delay = <150>;
a1e327e6
YCLP		 689 anatop-reg-offset = <0x140>;
690 anatop-vol-bit-shift = <9>;
691 anatop-vol-bit-width = <5>;
46743dd6
AH		 692 anatop-delay-reg-offset = <0x170>;
693 anatop-delay-bit-shift = <26>;
694 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 695 anatop-min-bit-val = <1>;
696 anatop-min-voltage = <725000>;
697 anatop-max-voltage = <1450000>;
698 };
699
c77ebb45 700 reg_soc: regulator-vddsoc {
a1e327e6
YCLP		 701 compatible = "fsl,anatop-regulator";
702 regulator-name = "vddsoc";
703 regulator-min-microvolt = <725000>;
704 regulator-max-microvolt = <1450000>;
705 regulator-always-on;
706 anatop-reg-offset = <0x140>;
707 anatop-vol-bit-shift = <18>;
708 anatop-vol-bit-width = <5>;
46743dd6
AH		 709 anatop-delay-reg-offset = <0x170>;
710 anatop-delay-bit-shift = <28>;
711 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 712 anatop-min-bit-val = <1>;
713 anatop-min-voltage = <725000>;
714 anatop-max-voltage = <1450000>;
715 };
7d740f87
SG		 716 };
717
3fe6373b
SG		 718 tempmon: tempmon {
719 compatible = "fsl,imx6q-tempmon";
275c08b5 720 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
3fe6373b
SG		 721 fsl,tempmon = <&anatop>;
722 fsl,tempmon-data = <&ocotp>;
8888f651 723 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
3fe6373b
SG		 724 };
725
74bd88f7
RZ		 726 usbphy1: usbphy@020c9000 {
727 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87 728 reg = <0x020c9000 0x1000>;
275c08b5 729 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
8888f651 730 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
76a38855 731 fsl,anatop = <&anatop>;
7d740f87
SG		 732 };
733
74bd88f7
RZ		 734 usbphy2: usbphy@020ca000 {
735 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87 736 reg = <0x020ca000 0x1000>;
275c08b5 737 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
8888f651 738 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
76a38855 739 fsl,anatop = <&anatop>;
7d740f87
SG		 740 };
741
95d739b5
FL		 742 snvs: snvs@020cc000 {
743 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
744 reg = <0x020cc000 0x4000>;
c9250388 745
95d739b5 746 snvs_rtc: snvs-rtc-lp {
c9250388 747 compatible = "fsl,sec-v4.0-mon-rtc-lp";
95d739b5
FL		 748 regmap = <&snvs>;
749 offset = <0x34>;
275c08b5
TK		 750 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
751 <0 20 IRQ_TYPE_LEVEL_HIGH>;
c9250388 752 };
422b0676 753
95d739b5
FL		 754 snvs_poweroff: snvs-poweroff {
755 compatible = "syscon-poweroff";
756 regmap = <&snvs>;
757 offset = <0x38>;
758 mask = <0x60>;
422b0676
RG		 759 status = "disabled";
760 };
7d740f87
SG		 761 };
762
7b7d6727 763 epit1: epit@020d0000 { /* EPIT1 */
7d740f87 764 reg = <0x020d0000 0x4000>;
275c08b5 765 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 766 };
767
7b7d6727 768 epit2: epit@020d4000 { /* EPIT2 */
7d740f87 769 reg = <0x020d4000 0x4000>;
275c08b5 770 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 771 };
772
7b7d6727 773 src: src@020d8000 {
bd3d924d 774 compatible = "fsl,imx6q-src", "fsl,imx51-src";
7d740f87 775 reg = <0x020d8000 0x4000>;
275c08b5
TK		 776 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
777 <0 96 IRQ_TYPE_LEVEL_HIGH>;
09ebf366 778 #reset-cells = <1>;
7d740f87
SG		 779 };
780
7b7d6727 781 gpc: gpc@020dc000 {
7d740f87
SG		 782 compatible = "fsl,imx6q-gpc";
783 reg = <0x020dc000 0x4000>;
b923ff6a
MZ		 784 interrupt-controller;
785 #interrupt-cells = <3>;
275c08b5
TK		 786 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
787 <0 90 IRQ_TYPE_LEVEL_HIGH>;
b923ff6a 788 interrupt-parent = <&intc>;
729c8881
PZ		 789 pu-supply = <&reg_pu>;
790 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
791 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
792 <&clks IMX6QDL_CLK_GPU2D_CORE>,
793 <&clks IMX6QDL_CLK_GPU2D_AXI>,
794 <&clks IMX6QDL_CLK_OPENVG_AXI>,
795 <&clks IMX6QDL_CLK_VPU_AXI>;
796 #power-domain-cells = <1>;
7d740f87
SG		 797 };
798
df37e0c0
DA		 799 gpr: iomuxc-gpr@020e0000 {
800 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
801 reg = <0x020e0000 0x38>;
802 };
803
c56009b2
SG		 804 iomuxc: iomuxc@020e0000 {
805 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
806 reg = <0x020e0000 0x4000>;
c56009b2
SG		 807 };
808
41c04342
ST		 809 ldb: ldb@020e0008 {
810 #address-cells = <1>;
811 #size-cells = <0>;
812 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
813 gpr = <&gpr>;
814 status = "disabled";
815
816 lvds-channel@0 {
4520e692
PZ		 817 #address-cells = <1>;
818 #size-cells = <0>;
41c04342 819 reg = <0>;
41c04342 820 status = "disabled";
4520e692
PZ		 821
822 port@0 {
823 reg = <0>;
824
825 lvds0_mux_0: endpoint {
826 remote-endpoint = <&ipu1_di0_lvds0>;
827 };
828 };
829
830 port@1 {
831 reg = <1>;
832
833 lvds0_mux_1: endpoint {
834 remote-endpoint = <&ipu1_di1_lvds0>;
835 };
836 };
41c04342
ST		 837 };
838
839 lvds-channel@1 {
4520e692
PZ		 840 #address-cells = <1>;
841 #size-cells = <0>;
41c04342 842 reg = <1>;
41c04342 843 status = "disabled";
4520e692
PZ		 844
845 port@0 {
846 reg = <0>;
847
848 lvds1_mux_0: endpoint {
849 remote-endpoint = <&ipu1_di0_lvds1>;
850 };
851 };
852
853 port@1 {
854 reg = <1>;
855
856 lvds1_mux_1: endpoint {
857 remote-endpoint = <&ipu1_di1_lvds1>;
858 };
859 };
41c04342
ST		 860 };
861 };
862
7b7d6727 863 dcic1: dcic@020e4000 {
7d740f87 864 reg = <0x020e4000 0x4000>;
275c08b5 865 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 866 };
867
7b7d6727 868 dcic2: dcic@020e8000 {
7d740f87 869 reg = <0x020e8000 0x4000>;
275c08b5 870 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 871 };
872
7b7d6727 873 sdma: sdma@020ec000 {
7d740f87
SG		 874 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
875 reg = <0x020ec000 0x4000>;
275c08b5 876 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 877 clocks = <&clks IMX6QDL_CLK_SDMA>,
878 <&clks IMX6QDL_CLK_SDMA>;
0e87e043 879 clock-names = "ipg", "ahb";
fb72bb21 880 #dma-cells = <3>;
d6b9c591 881 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
7d740f87
SG		 882 };
883 };
884
885 aips-bus@02100000 { /* AIPS2 */
886 compatible = "fsl,aips-bus", "simple-bus";
887 #address-cells = <1>;
888 #size-cells = <1>;
889 reg = <0x02100000 0x100000>;
890 ranges;
891
d462ce99
VM		 892 crypto: caam@2100000 {
893 compatible = "fsl,sec-v4.0";
894 fsl,sec-era = <4>;
895 #address-cells = <1>;
896 #size-cells = <1>;
897 reg = <0x2100000 0x10000>;
898 ranges = <0 0x2100000 0x10000>;
d462ce99
VM		 899 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
900 <&clks IMX6QDL_CLK_CAAM_ACLK>,
901 <&clks IMX6QDL_CLK_CAAM_IPG>,
902 <&clks IMX6QDL_CLK_EIM_SLOW>;
903 clock-names = "mem", "aclk", "ipg", "emi_slow";
904
905 sec_jr0: jr0@1000 {
906 compatible = "fsl,sec-v4.0-job-ring";
907 reg = <0x1000 0x1000>;
908 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
909 };
910
911 sec_jr1: jr1@2000 {
912 compatible = "fsl,sec-v4.0-job-ring";
913 reg = <0x2000 0x1000>;
914 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
915 };
7d740f87
SG		 916 };
917
918 aipstz@0217c000 { /* AIPSTZ2 */
919 reg = <0x0217c000 0x4000>;
920 };
921
7b7d6727 922 usbotg: usb@02184000 {
74bd88f7
RZ		 923 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
924 reg = <0x02184000 0x200>;
275c08b5 925 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
8888f651 926 clocks = <&clks IMX6QDL_CLK_USBOH3>;
74bd88f7 927 fsl,usbphy = <&usbphy1>;
28342c61 928 fsl,usbmisc = <&usbmisc 0>;
9493bf54 929 ahb-burst-config = <0x0>;
2b1a40e8
PC		 930 tx-burst-size-dword = <0x10>;
931 rx-burst-size-dword = <0x10>;
74bd88f7
RZ		 932 status = "disabled";
933 };
934
7b7d6727 935 usbh1: usb@02184200 {
74bd88f7
RZ		 936 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
937 reg = <0x02184200 0x200>;
275c08b5 938 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
8888f651 939 clocks = <&clks IMX6QDL_CLK_USBOH3>;
74bd88f7 940 fsl,usbphy = <&usbphy2>;
28342c61 941 fsl,usbmisc = <&usbmisc 1>;
3ec481ed 942 dr_mode = "host";
9493bf54 943 ahb-burst-config = <0x0>;
2b1a40e8
PC		 944 tx-burst-size-dword = <0x10>;
945 rx-burst-size-dword = <0x10>;
74bd88f7
RZ		 946 status = "disabled";
947 };
948
7b7d6727 949 usbh2: usb@02184400 {
74bd88f7
RZ		 950 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
951 reg = <0x02184400 0x200>;
275c08b5 952 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
8888f651 953 clocks = <&clks IMX6QDL_CLK_USBOH3>;
28342c61 954 fsl,usbmisc = <&usbmisc 2>;
3ec481ed 955 dr_mode = "host";
9493bf54 956 ahb-burst-config = <0x0>;
2b1a40e8
PC		 957 tx-burst-size-dword = <0x10>;
958 rx-burst-size-dword = <0x10>;
74bd88f7
RZ		 959 status = "disabled";
960 };
961
7b7d6727 962 usbh3: usb@02184600 {
74bd88f7
RZ		 963 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
964 reg = <0x02184600 0x200>;
275c08b5 965 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
8888f651 966 clocks = <&clks IMX6QDL_CLK_USBOH3>;
28342c61 967 fsl,usbmisc = <&usbmisc 3>;
3ec481ed 968 dr_mode = "host";
9493bf54 969 ahb-burst-config = <0x0>;
2b1a40e8
PC		 970 tx-burst-size-dword = <0x10>;
971 rx-burst-size-dword = <0x10>;
74bd88f7
RZ		 972 status = "disabled";
973 };
974
60984bdf 975 usbmisc: usbmisc@02184800 {
28342c61
RZ		 976 #index-cells = <1>;
977 compatible = "fsl,imx6q-usbmisc";
978 reg = <0x02184800 0x200>;
8888f651 979 clocks = <&clks IMX6QDL_CLK_USBOH3>;
28342c61
RZ		 980 };
981
7b7d6727 982 fec: ethernet@02188000 {
7d740f87
SG		 983 compatible = "fsl,imx6q-fec";
984 reg = <0x02188000 0x4000>;
454cf8f5
TK		 985 interrupts-extended =
986 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
987 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 988 clocks = <&clks IMX6QDL_CLK_ENET>,
989 <&clks IMX6QDL_CLK_ENET>,
990 <&clks IMX6QDL_CLK_ENET_REF>;
7629838c 991 clock-names = "ipg", "ahb", "ptp";
7d740f87
SG		 992 status = "disabled";
993 };
994
995 mlb@0218c000 {
996 reg = <0x0218c000 0x4000>;
275c08b5
TK		 997 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
998 <0 117 IRQ_TYPE_LEVEL_HIGH>,
999 <0 126 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 1000 };
1001
7b7d6727 1002 usdhc1: usdhc@02190000 {
7d740f87
SG		 1003 compatible = "fsl,imx6q-usdhc";
1004 reg = <0x02190000 0x4000>;
275c08b5 1005 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1006 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1007 <&clks IMX6QDL_CLK_USDHC1>,
1008 <&clks IMX6QDL_CLK_USDHC1>;
0e87e043 1009 clock-names = "ipg", "ahb", "per";
c104b6a2 1010 bus-width = <4>;
7d740f87
SG		 1011 status = "disabled";
1012 };
1013
7b7d6727 1014 usdhc2: usdhc@02194000 {
7d740f87
SG		 1015 compatible = "fsl,imx6q-usdhc";
1016 reg = <0x02194000 0x4000>;
275c08b5 1017 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1018 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1019 <&clks IMX6QDL_CLK_USDHC2>,
1020 <&clks IMX6QDL_CLK_USDHC2>;
0e87e043 1021 clock-names = "ipg", "ahb", "per";
c104b6a2 1022 bus-width = <4>;
7d740f87
SG		 1023 status = "disabled";
1024 };
1025
7b7d6727 1026 usdhc3: usdhc@02198000 {
7d740f87
SG		 1027 compatible = "fsl,imx6q-usdhc";
1028 reg = <0x02198000 0x4000>;
275c08b5 1029 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1030 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1031 <&clks IMX6QDL_CLK_USDHC3>,
1032 <&clks IMX6QDL_CLK_USDHC3>;
0e87e043 1033 clock-names = "ipg", "ahb", "per";
c104b6a2 1034 bus-width = <4>;
7d740f87
SG		 1035 status = "disabled";
1036 };
1037
7b7d6727 1038 usdhc4: usdhc@0219c000 {
7d740f87
SG		 1039 compatible = "fsl,imx6q-usdhc";
1040 reg = <0x0219c000 0x4000>;
275c08b5 1041 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1042 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1043 <&clks IMX6QDL_CLK_USDHC4>,
1044 <&clks IMX6QDL_CLK_USDHC4>;
0e87e043 1045 clock-names = "ipg", "ahb", "per";
c104b6a2 1046 bus-width = <4>;
7d740f87
SG		 1047 status = "disabled";
1048 };
1049
7b7d6727 1050 i2c1: i2c@021a0000 {
7d740f87
SG		 1051 #address-cells = <1>;
1052 #size-cells = <0>;
5bdfba29 1053 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 1054 reg = <0x021a0000 0x4000>;
275c08b5 1055 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
8888f651 1056 clocks = <&clks IMX6QDL_CLK_I2C1>;
7d740f87
SG		 1057 status = "disabled";
1058 };
1059
7b7d6727 1060 i2c2: i2c@021a4000 {
7d740f87
SG		 1061 #address-cells = <1>;
1062 #size-cells = <0>;
5bdfba29 1063 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 1064 reg = <0x021a4000 0x4000>;
275c08b5 1065 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
8888f651 1066 clocks = <&clks IMX6QDL_CLK_I2C2>;
7d740f87
SG		 1067 status = "disabled";
1068 };
1069
7b7d6727 1070 i2c3: i2c@021a8000 {
7d740f87
SG		 1071 #address-cells = <1>;
1072 #size-cells = <0>;
5bdfba29 1073 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 1074 reg = <0x021a8000 0x4000>;
275c08b5 1075 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
8888f651 1076 clocks = <&clks IMX6QDL_CLK_I2C3>;
7d740f87
SG		 1077 status = "disabled";
1078 };
1079
1080 romcp@021ac000 {
1081 reg = <0x021ac000 0x4000>;
1082 };
1083
7b7d6727 1084 mmdc0: mmdc@021b0000 { /* MMDC0 */
7d740f87
SG		 1085 compatible = "fsl,imx6q-mmdc";
1086 reg = <0x021b0000 0x4000>;
1087 };
1088
7b7d6727 1089 mmdc1: mmdc@021b4000 { /* MMDC1 */
7d740f87
SG		 1090 reg = <0x021b4000 0x4000>;
1091 };
1092
05e3f8e7
HS		 1093 weim: weim@021b8000 {
1094 compatible = "fsl,imx6q-weim";
7d740f87 1095 reg = <0x021b8000 0x4000>;
275c08b5 1096 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
8888f651 1097 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
7d740f87
SG		 1098 };
1099
3fe6373b
SG		 1100 ocotp: ocotp@021bc000 {
1101 compatible = "fsl,imx6q-ocotp", "syscon";
7d740f87 1102 reg = <0x021bc000 0x4000>;
b8ecd889 1103 clocks = <&clks IMX6QDL_CLK_IIM>;
7d740f87
SG		 1104 };
1105
7d740f87
SG		 1106 tzasc@021d0000 { /* TZASC1 */
1107 reg = <0x021d0000 0x4000>;
275c08b5 1108 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 1109 };
1110
1111 tzasc@021d4000 { /* TZASC2 */
1112 reg = <0x021d4000 0x4000>;
275c08b5 1113 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 1114 };
1115
7b7d6727 1116 audmux: audmux@021d8000 {
f965cd55 1117 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 1118 reg = <0x021d8000 0x4000>;
f965cd55 1119 status = "disabled";
7d740f87
SG		 1120 };
1121
5e0c7cd4 1122 mipi_csi: mipi@021dc000 {
7d740f87
SG		 1123 reg = <0x021dc000 0x4000>;
1124 };
1125
4520e692
PZ		 1126 mipi_dsi: mipi@021e0000 {
1127 #address-cells = <1>;
1128 #size-cells = <0>;
7d740f87 1129 reg = <0x021e0000 0x4000>;
4520e692
PZ		 1130 status = "disabled";
1131
70c2652c
LY		 1132 ports {
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135
1136 port@0 {
1137 reg = <0>;
4520e692 1138
70c2652c
LY		 1139 mipi_mux_0: endpoint {
1140 remote-endpoint = <&ipu1_di0_mipi>;
1141 };
4520e692 1142 };
4520e692 1143
70c2652c
LY		 1144 port@1 {
1145 reg = <1>;
4520e692 1146
70c2652c
LY		 1147 mipi_mux_1: endpoint {
1148 remote-endpoint = <&ipu1_di1_mipi>;
1149 };
4520e692
PZ		 1150 };
1151 };
7d740f87
SG		 1152 };
1153
1154 vdoa@021e4000 {
1155 reg = <0x021e4000 0x4000>;
275c08b5 1156 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 1157 };
1158
0c456cfa 1159 uart2: serial@021e8000 {
7d740f87
SG		 1160 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1161 reg = <0x021e8000 0x4000>;
275c08b5 1162 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1163 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1164 <&clks IMX6QDL_CLK_UART_SERIAL>;
0e87e043 1165 clock-names = "ipg", "per";
72a5cebf
HS		 1166 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1167 dma-names = "rx", "tx";
7d740f87
SG		 1168 status = "disabled";
1169 };
1170
0c456cfa 1171 uart3: serial@021ec000 {
7d740f87
SG		 1172 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1173 reg = <0x021ec000 0x4000>;
275c08b5 1174 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1175 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1176 <&clks IMX6QDL_CLK_UART_SERIAL>;
0e87e043 1177 clock-names = "ipg", "per";
72a5cebf
HS		 1178 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1179 dma-names = "rx", "tx";
7d740f87
SG		 1180 status = "disabled";
1181 };
1182
0c456cfa 1183 uart4: serial@021f0000 {
7d740f87
SG		 1184 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1185 reg = <0x021f0000 0x4000>;
275c08b5 1186 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1187 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1188 <&clks IMX6QDL_CLK_UART_SERIAL>;
0e87e043 1189 clock-names = "ipg", "per";
72a5cebf
HS		 1190 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1191 dma-names = "rx", "tx";
7d740f87
SG		 1192 status = "disabled";
1193 };
1194
0c456cfa 1195 uart5: serial@021f4000 {
7d740f87
SG		 1196 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1197 reg = <0x021f4000 0x4000>;
275c08b5 1198 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1199 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1200 <&clks IMX6QDL_CLK_UART_SERIAL>;
0e87e043 1201 clock-names = "ipg", "per";
72a5cebf
HS		 1202 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1203 dma-names = "rx", "tx";
7d740f87
SG		 1204 status = "disabled";
1205 };
1206 };
91660d74
SH		 1207
1208 ipu1: ipu@02400000 {
4520e692
PZ		 1209 #address-cells = <1>;
1210 #size-cells = <0>;
91660d74
SH		 1211 compatible = "fsl,imx6q-ipu";
1212 reg = <0x02400000 0x400000>;
275c08b5
TK		 1213 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1214 <0 5 IRQ_TYPE_LEVEL_HIGH>;
8888f651
SG		 1215 clocks = <&clks IMX6QDL_CLK_IPU1>,
1216 <&clks IMX6QDL_CLK_IPU1_DI0>,
1217 <&clks IMX6QDL_CLK_IPU1_DI1>;
91660d74 1218 clock-names = "bus", "di0", "di1";
09ebf366 1219 resets = <&src 2>;
4520e692 1220
c0470c38
PZ		 1221 ipu1_csi0: port@0 {
1222 reg = <0>;
1223 };
1224
1225 ipu1_csi1: port@1 {
1226 reg = <1>;
1227 };
1228
4520e692
PZ		 1229 ipu1_di0: port@2 {
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1232 reg = <2>;
1233
416196cd 1234 ipu1_di0_disp0: disp0-endpoint {
4520e692
PZ		 1235 };
1236
416196cd 1237 ipu1_di0_hdmi: hdmi-endpoint {
4520e692
PZ		 1238 remote-endpoint = <&hdmi_mux_0>;
1239 };
1240
416196cd 1241 ipu1_di0_mipi: mipi-endpoint {
4520e692
PZ		 1242 remote-endpoint = <&mipi_mux_0>;
1243 };
1244
416196cd 1245 ipu1_di0_lvds0: lvds0-endpoint {
4520e692
PZ		 1246 remote-endpoint = <&lvds0_mux_0>;
1247 };
1248
416196cd 1249 ipu1_di0_lvds1: lvds1-endpoint {
4520e692
PZ		 1250 remote-endpoint = <&lvds1_mux_0>;
1251 };
1252 };
1253
1254 ipu1_di1: port@3 {
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1257 reg = <3>;
1258
f255f89f 1259 ipu1_di1_disp1: disp1-endpoint {
4520e692
PZ		 1260 };
1261
416196cd 1262 ipu1_di1_hdmi: hdmi-endpoint {
4520e692
PZ		 1263 remote-endpoint = <&hdmi_mux_1>;
1264 };
1265
416196cd 1266 ipu1_di1_mipi: mipi-endpoint {
4520e692
PZ		 1267 remote-endpoint = <&mipi_mux_1>;
1268 };
1269
416196cd 1270 ipu1_di1_lvds0: lvds0-endpoint {
4520e692
PZ		 1271 remote-endpoint = <&lvds0_mux_1>;
1272 };
1273
416196cd 1274 ipu1_di1_lvds1: lvds1-endpoint {
4520e692
PZ		 1275 remote-endpoint = <&lvds1_mux_1>;
1276 };
1277 };
91660d74 1278 };
7d740f87
SG		 1279 };
1280};
Linux kernel - Deliverables
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