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ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
7d740f87
SG		 14
15/ {
16 aliases {
8f9ffecf
RZ		 17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
7d740f87
SG		 29 };
30
7d740f87
SG		 31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
f30fb03d 68 dma_apbh: dma-apbh@00110000 {
e5d0f9f5
HS		 69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
f30fb03d
SG		 71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
73 #dma-cells = <1>;
74 dma-channels = <4>;
0e87e043 75 clocks = <&clks 106>;
e5d0f9f5
HS		 76 };
77
be4ccfce 78 gpmi: gpmi-nand@00112000 {
0e87e043
SG		 79 compatible = "fsl,imx6q-gpmi-nand";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
f30fb03d
SG		 90 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx";
0e87e043
SG		 92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled";
cf922fa8
HS		 94 };
95
7d740f87 96 timer@00a00600 {
58458e03
MZ		 97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
2bb4b70b 100 clocks = <&clks 15>;
7d740f87
SG		 101 };
102
103 L2: l2-cache@00a02000 {
104 compatible = "arm,pl310-cache";
105 reg = <0x00a02000 0x1000>;
106 interrupts = <0 92 0x04>;
107 cache-unified;
108 cache-level = <2>;
109 };
110
218abe6f
DB		 111 pmu {
112 compatible = "arm,cortex-a9-pmu";
113 interrupts = <0 94 0x04>;
114 };
115
7d740f87
SG		 116 aips-bus@02000000 { /* AIPS1 */
117 compatible = "fsl,aips-bus", "simple-bus";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 reg = <0x02000000 0x100000>;
121 ranges;
122
123 spba-bus@02000000 {
124 compatible = "fsl,spba-bus", "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x02000000 0x40000>;
128 ranges;
129
7b7d6727 130 spdif: spdif@02004000 {
7d740f87
SG		 131 reg = <0x02004000 0x4000>;
132 interrupts = <0 52 0x04>;
133 };
134
7b7d6727 135 ecspi1: ecspi@02008000 {
7d740f87
SG		 136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
139 reg = <0x02008000 0x4000>;
140 interrupts = <0 31 0x04>;
0e87e043
SG		 141 clocks = <&clks 112>, <&clks 112>;
142 clock-names = "ipg", "per";
7d740f87
SG		 143 status = "disabled";
144 };
145
7b7d6727 146 ecspi2: ecspi@0200c000 {
7d740f87
SG		 147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
150 reg = <0x0200c000 0x4000>;
151 interrupts = <0 32 0x04>;
0e87e043
SG		 152 clocks = <&clks 113>, <&clks 113>;
153 clock-names = "ipg", "per";
7d740f87
SG		 154 status = "disabled";
155 };
156
7b7d6727 157 ecspi3: ecspi@02010000 {
7d740f87
SG		 158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
161 reg = <0x02010000 0x4000>;
162 interrupts = <0 33 0x04>;
0e87e043
SG		 163 clocks = <&clks 114>, <&clks 114>;
164 clock-names = "ipg", "per";
7d740f87
SG		 165 status = "disabled";
166 };
167
7b7d6727 168 ecspi4: ecspi@02014000 {
7d740f87
SG		 169 #address-cells = <1>;
170 #size-cells = <0>;
171 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
172 reg = <0x02014000 0x4000>;
173 interrupts = <0 34 0x04>;
0e87e043
SG		 174 clocks = <&clks 115>, <&clks 115>;
175 clock-names = "ipg", "per";
7d740f87
SG		 176 status = "disabled";
177 };
178
0c456cfa 179 uart1: serial@02020000 {
7d740f87
SG		 180 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
181 reg = <0x02020000 0x4000>;
182 interrupts = <0 26 0x04>;
0e87e043
SG		 183 clocks = <&clks 160>, <&clks 161>;
184 clock-names = "ipg", "per";
7d740f87
SG		 185 status = "disabled";
186 };
187
7b7d6727 188 esai: esai@02024000 {
7d740f87
SG		 189 reg = <0x02024000 0x4000>;
190 interrupts = <0 51 0x04>;
191 };
192
b1a5da8e
RZ		 193 ssi1: ssi@02028000 {
194 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 195 reg = <0x02028000 0x4000>;
196 interrupts = <0 46 0x04>;
0e87e043 197 clocks = <&clks 178>;
b1a5da8e
RZ		 198 fsl,fifo-depth = <15>;
199 fsl,ssi-dma-events = <38 37>;
200 status = "disabled";
7d740f87
SG		 201 };
202
b1a5da8e
RZ		 203 ssi2: ssi@0202c000 {
204 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 205 reg = <0x0202c000 0x4000>;
206 interrupts = <0 47 0x04>;
0e87e043 207 clocks = <&clks 179>;
b1a5da8e
RZ		 208 fsl,fifo-depth = <15>;
209 fsl,ssi-dma-events = <42 41>;
210 status = "disabled";
7d740f87
SG		 211 };
212
b1a5da8e
RZ		 213 ssi3: ssi@02030000 {
214 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 215 reg = <0x02030000 0x4000>;
216 interrupts = <0 48 0x04>;
0e87e043 217 clocks = <&clks 180>;
b1a5da8e
RZ		 218 fsl,fifo-depth = <15>;
219 fsl,ssi-dma-events = <46 45>;
220 status = "disabled";
7d740f87
SG		 221 };
222
7b7d6727 223 asrc: asrc@02034000 {
7d740f87
SG		 224 reg = <0x02034000 0x4000>;
225 interrupts = <0 50 0x04>;
226 };
227
228 spba@0203c000 {
229 reg = <0x0203c000 0x4000>;
230 };
231 };
232
7b7d6727 233 vpu: vpu@02040000 {
7d740f87
SG		 234 reg = <0x02040000 0x3c000>;
235 interrupts = <0 3 0x04 0 12 0x04>;
236 };
237
238 aipstz@0207c000 { /* AIPSTZ1 */
239 reg = <0x0207c000 0x4000>;
240 };
241
7b7d6727 242 pwm1: pwm@02080000 {
33b38587
SH		 243 #pwm-cells = <2>;
244 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 245 reg = <0x02080000 0x4000>;
246 interrupts = <0 83 0x04>;
33b38587
SH		 247 clocks = <&clks 62>, <&clks 145>;
248 clock-names = "ipg", "per";
7d740f87
SG		 249 };
250
7b7d6727 251 pwm2: pwm@02084000 {
33b38587
SH		 252 #pwm-cells = <2>;
253 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 254 reg = <0x02084000 0x4000>;
255 interrupts = <0 84 0x04>;
33b38587
SH		 256 clocks = <&clks 62>, <&clks 146>;
257 clock-names = "ipg", "per";
7d740f87
SG		 258 };
259
7b7d6727 260 pwm3: pwm@02088000 {
33b38587
SH		 261 #pwm-cells = <2>;
262 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 263 reg = <0x02088000 0x4000>;
264 interrupts = <0 85 0x04>;
33b38587
SH		 265 clocks = <&clks 62>, <&clks 147>;
266 clock-names = "ipg", "per";
7d740f87
SG		 267 };
268
7b7d6727 269 pwm4: pwm@0208c000 {
33b38587
SH		 270 #pwm-cells = <2>;
271 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 272 reg = <0x0208c000 0x4000>;
273 interrupts = <0 86 0x04>;
33b38587
SH		 274 clocks = <&clks 62>, <&clks 148>;
275 clock-names = "ipg", "per";
7d740f87
SG		 276 };
277
7b7d6727 278 can1: flexcan@02090000 {
7d740f87
SG		 279 reg = <0x02090000 0x4000>;
280 interrupts = <0 110 0x04>;
281 };
282
7b7d6727 283 can2: flexcan@02094000 {
7d740f87
SG		 284 reg = <0x02094000 0x4000>;
285 interrupts = <0 111 0x04>;
286 };
287
7b7d6727 288 gpt: gpt@02098000 {
7d740f87
SG		 289 compatible = "fsl,imx6q-gpt";
290 reg = <0x02098000 0x4000>;
291 interrupts = <0 55 0x04>;
4efccadd
SH		 292 clocks = <&clks 119>, <&clks 120>;
293 clock-names = "ipg", "per";
7d740f87
SG		 294 };
295
4d191868 296 gpio1: gpio@0209c000 {
aeb27748 297 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 298 reg = <0x0209c000 0x4000>;
299 interrupts = <0 66 0x04 0 67 0x04>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
88cde8b7 303 #interrupt-cells = <2>;
7d740f87
SG		 304 };
305
4d191868 306 gpio2: gpio@020a0000 {
aeb27748 307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 308 reg = <0x020a0000 0x4000>;
309 interrupts = <0 68 0x04 0 69 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
88cde8b7 313 #interrupt-cells = <2>;
7d740f87
SG		 314 };
315
4d191868 316 gpio3: gpio@020a4000 {
aeb27748 317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 318 reg = <0x020a4000 0x4000>;
319 interrupts = <0 70 0x04 0 71 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
88cde8b7 323 #interrupt-cells = <2>;
7d740f87
SG		 324 };
325
4d191868 326 gpio4: gpio@020a8000 {
aeb27748 327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 328 reg = <0x020a8000 0x4000>;
329 interrupts = <0 72 0x04 0 73 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
88cde8b7 333 #interrupt-cells = <2>;
7d740f87
SG		 334 };
335
4d191868 336 gpio5: gpio@020ac000 {
aeb27748 337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 338 reg = <0x020ac000 0x4000>;
339 interrupts = <0 74 0x04 0 75 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
88cde8b7 343 #interrupt-cells = <2>;
7d740f87
SG		 344 };
345
4d191868 346 gpio6: gpio@020b0000 {
aeb27748 347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 348 reg = <0x020b0000 0x4000>;
349 interrupts = <0 76 0x04 0 77 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
88cde8b7 353 #interrupt-cells = <2>;
7d740f87
SG		 354 };
355
4d191868 356 gpio7: gpio@020b4000 {
aeb27748 357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 358 reg = <0x020b4000 0x4000>;
359 interrupts = <0 78 0x04 0 79 0x04>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
88cde8b7 363 #interrupt-cells = <2>;
7d740f87
SG		 364 };
365
7b7d6727 366 kpp: kpp@020b8000 {
7d740f87
SG		 367 reg = <0x020b8000 0x4000>;
368 interrupts = <0 82 0x04>;
369 };
370
7b7d6727 371 wdog1: wdog@020bc000 {
7d740f87
SG		 372 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
373 reg = <0x020bc000 0x4000>;
374 interrupts = <0 80 0x04>;
0e87e043 375 clocks = <&clks 0>;
7d740f87
SG		 376 };
377
7b7d6727 378 wdog2: wdog@020c0000 {
7d740f87
SG		 379 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
380 reg = <0x020c0000 0x4000>;
381 interrupts = <0 81 0x04>;
0e87e043 382 clocks = <&clks 0>;
7d740f87
SG		 383 status = "disabled";
384 };
385
0e87e043 386 clks: ccm@020c4000 {
7d740f87
SG		 387 compatible = "fsl,imx6q-ccm";
388 reg = <0x020c4000 0x4000>;
389 interrupts = <0 87 0x04 0 88 0x04>;
0e87e043 390 #clock-cells = <1>;
7d740f87
SG		 391 };
392
baa64151
DA		 393 anatop: anatop@020c8000 {
394 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
7d740f87
SG		 395 reg = <0x020c8000 0x1000>;
396 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
a1e327e6
YCLP		 397
398 regulator-1p1@110 {
399 compatible = "fsl,anatop-regulator";
400 regulator-name = "vdd1p1";
401 regulator-min-microvolt = <800000>;
402 regulator-max-microvolt = <1375000>;
403 regulator-always-on;
404 anatop-reg-offset = <0x110>;
405 anatop-vol-bit-shift = <8>;
406 anatop-vol-bit-width = <5>;
407 anatop-min-bit-val = <4>;
408 anatop-min-voltage = <800000>;
409 anatop-max-voltage = <1375000>;
410 };
411
412 regulator-3p0@120 {
413 compatible = "fsl,anatop-regulator";
414 regulator-name = "vdd3p0";
415 regulator-min-microvolt = <2800000>;
416 regulator-max-microvolt = <3150000>;
417 regulator-always-on;
418 anatop-reg-offset = <0x120>;
419 anatop-vol-bit-shift = <8>;
420 anatop-vol-bit-width = <5>;
421 anatop-min-bit-val = <0>;
422 anatop-min-voltage = <2625000>;
423 anatop-max-voltage = <3400000>;
424 };
425
426 regulator-2p5@130 {
427 compatible = "fsl,anatop-regulator";
428 regulator-name = "vdd2p5";
429 regulator-min-microvolt = <2000000>;
430 regulator-max-microvolt = <2750000>;
431 regulator-always-on;
432 anatop-reg-offset = <0x130>;
433 anatop-vol-bit-shift = <8>;
434 anatop-vol-bit-width = <5>;
435 anatop-min-bit-val = <0>;
436 anatop-min-voltage = <2000000>;
437 anatop-max-voltage = <2750000>;
438 };
439
96574a6d 440 reg_arm: regulator-vddcore@140 {
a1e327e6
YCLP		 441 compatible = "fsl,anatop-regulator";
442 regulator-name = "cpu";
443 regulator-min-microvolt = <725000>;
444 regulator-max-microvolt = <1450000>;
445 regulator-always-on;
446 anatop-reg-offset = <0x140>;
447 anatop-vol-bit-shift = <0>;
448 anatop-vol-bit-width = <5>;
46743dd6
AH		 449 anatop-delay-reg-offset = <0x170>;
450 anatop-delay-bit-shift = <24>;
451 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 452 anatop-min-bit-val = <1>;
453 anatop-min-voltage = <725000>;
454 anatop-max-voltage = <1450000>;
455 };
456
96574a6d 457 reg_pu: regulator-vddpu@140 {
a1e327e6
YCLP		 458 compatible = "fsl,anatop-regulator";
459 regulator-name = "vddpu";
460 regulator-min-microvolt = <725000>;
461 regulator-max-microvolt = <1450000>;
462 regulator-always-on;
463 anatop-reg-offset = <0x140>;
464 anatop-vol-bit-shift = <9>;
465 anatop-vol-bit-width = <5>;
46743dd6
AH		 466 anatop-delay-reg-offset = <0x170>;
467 anatop-delay-bit-shift = <26>;
468 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 469 anatop-min-bit-val = <1>;
470 anatop-min-voltage = <725000>;
471 anatop-max-voltage = <1450000>;
472 };
473
96574a6d 474 reg_soc: regulator-vddsoc@140 {
a1e327e6
YCLP		 475 compatible = "fsl,anatop-regulator";
476 regulator-name = "vddsoc";
477 regulator-min-microvolt = <725000>;
478 regulator-max-microvolt = <1450000>;
479 regulator-always-on;
480 anatop-reg-offset = <0x140>;
481 anatop-vol-bit-shift = <18>;
482 anatop-vol-bit-width = <5>;
46743dd6
AH		 483 anatop-delay-reg-offset = <0x170>;
484 anatop-delay-bit-shift = <28>;
485 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 486 anatop-min-bit-val = <1>;
487 anatop-min-voltage = <725000>;
488 anatop-max-voltage = <1450000>;
489 };
7d740f87
SG		 490 };
491
74bd88f7
RZ		 492 usbphy1: usbphy@020c9000 {
493 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 494 reg = <0x020c9000 0x1000>;
495 interrupts = <0 44 0x04>;
0e87e043 496 clocks = <&clks 182>;
7d740f87
SG		 497 };
498
74bd88f7
RZ		 499 usbphy2: usbphy@020ca000 {
500 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 501 reg = <0x020ca000 0x1000>;
502 interrupts = <0 45 0x04>;
0e87e043 503 clocks = <&clks 183>;
7d740f87
SG		 504 };
505
506 snvs@020cc000 {
c9250388
SG		 507 compatible = "fsl,sec-v4.0-mon", "simple-bus";
508 #address-cells = <1>;
509 #size-cells = <1>;
510 ranges = <0 0x020cc000 0x4000>;
511
512 snvs-rtc-lp@34 {
513 compatible = "fsl,sec-v4.0-mon-rtc-lp";
514 reg = <0x34 0x58>;
515 interrupts = <0 19 0x04 0 20 0x04>;
516 };
7d740f87
SG		 517 };
518
7b7d6727 519 epit1: epit@020d0000 { /* EPIT1 */
7d740f87
SG		 520 reg = <0x020d0000 0x4000>;
521 interrupts = <0 56 0x04>;
522 };
523
7b7d6727 524 epit2: epit@020d4000 { /* EPIT2 */
7d740f87
SG		 525 reg = <0x020d4000 0x4000>;
526 interrupts = <0 57 0x04>;
527 };
528
7b7d6727 529 src: src@020d8000 {
bd3d924d 530 compatible = "fsl,imx6q-src", "fsl,imx51-src";
7d740f87
SG		 531 reg = <0x020d8000 0x4000>;
532 interrupts = <0 91 0x04 0 96 0x04>;
09ebf366 533 #reset-cells = <1>;
7d740f87
SG		 534 };
535
7b7d6727 536 gpc: gpc@020dc000 {
7d740f87
SG		 537 compatible = "fsl,imx6q-gpc";
538 reg = <0x020dc000 0x4000>;
539 interrupts = <0 89 0x04 0 90 0x04>;
540 };
541
df37e0c0
DA		 542 gpr: iomuxc-gpr@020e0000 {
543 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
544 reg = <0x020e0000 0x38>;
545 };
546
41c04342
ST		 547 ldb: ldb@020e0008 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
551 gpr = <&gpr>;
552 status = "disabled";
553
554 lvds-channel@0 {
555 reg = <0>;
556 crtcs = <&ipu1 0>;
557 status = "disabled";
558 };
559
560 lvds-channel@1 {
561 reg = <1>;
562 crtcs = <&ipu1 1>;
563 status = "disabled";
564 };
565 };
566
7b7d6727 567 dcic1: dcic@020e4000 {
7d740f87
SG		 568 reg = <0x020e4000 0x4000>;
569 interrupts = <0 124 0x04>;
570 };
571
7b7d6727 572 dcic2: dcic@020e8000 {
7d740f87
SG		 573 reg = <0x020e8000 0x4000>;
574 interrupts = <0 125 0x04>;
575 };
576
7b7d6727 577 sdma: sdma@020ec000 {
7d740f87
SG		 578 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
579 reg = <0x020ec000 0x4000>;
580 interrupts = <0 2 0x04>;
0e87e043
SG		 581 clocks = <&clks 155>, <&clks 155>;
582 clock-names = "ipg", "ahb";
d6b9c591 583 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
7d740f87
SG		 584 };
585 };
586
587 aips-bus@02100000 { /* AIPS2 */
588 compatible = "fsl,aips-bus", "simple-bus";
589 #address-cells = <1>;
590 #size-cells = <1>;
591 reg = <0x02100000 0x100000>;
592 ranges;
593
594 caam@02100000 {
595 reg = <0x02100000 0x40000>;
596 interrupts = <0 105 0x04 0 106 0x04>;
597 };
598
599 aipstz@0217c000 { /* AIPSTZ2 */
600 reg = <0x0217c000 0x4000>;
601 };
602
7b7d6727 603 usbotg: usb@02184000 {
74bd88f7
RZ		 604 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
605 reg = <0x02184000 0x200>;
606 interrupts = <0 43 0x04>;
0e87e043 607 clocks = <&clks 162>;
74bd88f7 608 fsl,usbphy = <&usbphy1>;
28342c61 609 fsl,usbmisc = <&usbmisc 0>;
74bd88f7
RZ		 610 status = "disabled";
611 };
612
7b7d6727 613 usbh1: usb@02184200 {
74bd88f7
RZ		 614 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
615 reg = <0x02184200 0x200>;
616 interrupts = <0 40 0x04>;
0e87e043 617 clocks = <&clks 162>;
74bd88f7 618 fsl,usbphy = <&usbphy2>;
28342c61 619 fsl,usbmisc = <&usbmisc 1>;
74bd88f7
RZ		 620 status = "disabled";
621 };
622
7b7d6727 623 usbh2: usb@02184400 {
74bd88f7
RZ		 624 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
625 reg = <0x02184400 0x200>;
626 interrupts = <0 41 0x04>;
0e87e043 627 clocks = <&clks 162>;
28342c61 628 fsl,usbmisc = <&usbmisc 2>;
74bd88f7
RZ		 629 status = "disabled";
630 };
631
7b7d6727 632 usbh3: usb@02184600 {
74bd88f7
RZ		 633 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
634 reg = <0x02184600 0x200>;
635 interrupts = <0 42 0x04>;
0e87e043 636 clocks = <&clks 162>;
28342c61 637 fsl,usbmisc = <&usbmisc 3>;
74bd88f7
RZ		 638 status = "disabled";
639 };
640
7b7d6727 641 usbmisc: usbmisc: usbmisc@02184800 {
28342c61
RZ		 642 #index-cells = <1>;
643 compatible = "fsl,imx6q-usbmisc";
644 reg = <0x02184800 0x200>;
645 clocks = <&clks 162>;
646 };
647
7b7d6727 648 fec: ethernet@02188000 {
7d740f87
SG		 649 compatible = "fsl,imx6q-fec";
650 reg = <0x02188000 0x4000>;
651 interrupts = <0 118 0x04 0 119 0x04>;
8dd5c66b 652 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
7629838c 653 clock-names = "ipg", "ahb", "ptp";
7d740f87
SG		 654 status = "disabled";
655 };
656
657 mlb@0218c000 {
658 reg = <0x0218c000 0x4000>;
659 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
660 };
661
7b7d6727 662 usdhc1: usdhc@02190000 {
7d740f87
SG		 663 compatible = "fsl,imx6q-usdhc";
664 reg = <0x02190000 0x4000>;
665 interrupts = <0 22 0x04>;
0e87e043
SG		 666 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
667 clock-names = "ipg", "ahb", "per";
c104b6a2 668 bus-width = <4>;
7d740f87
SG		 669 status = "disabled";
670 };
671
7b7d6727 672 usdhc2: usdhc@02194000 {
7d740f87
SG		 673 compatible = "fsl,imx6q-usdhc";
674 reg = <0x02194000 0x4000>;
675 interrupts = <0 23 0x04>;
0e87e043
SG		 676 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
677 clock-names = "ipg", "ahb", "per";
c104b6a2 678 bus-width = <4>;
7d740f87
SG		 679 status = "disabled";
680 };
681
7b7d6727 682 usdhc3: usdhc@02198000 {
7d740f87
SG		 683 compatible = "fsl,imx6q-usdhc";
684 reg = <0x02198000 0x4000>;
685 interrupts = <0 24 0x04>;
0e87e043
SG		 686 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
687 clock-names = "ipg", "ahb", "per";
c104b6a2 688 bus-width = <4>;
7d740f87
SG		 689 status = "disabled";
690 };
691
7b7d6727 692 usdhc4: usdhc@0219c000 {
7d740f87
SG		 693 compatible = "fsl,imx6q-usdhc";
694 reg = <0x0219c000 0x4000>;
695 interrupts = <0 25 0x04>;
0e87e043
SG		 696 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
697 clock-names = "ipg", "ahb", "per";
c104b6a2 698 bus-width = <4>;
7d740f87
SG		 699 status = "disabled";
700 };
701
7b7d6727 702 i2c1: i2c@021a0000 {
7d740f87
SG		 703 #address-cells = <1>;
704 #size-cells = <0>;
5bdfba29 705 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 706 reg = <0x021a0000 0x4000>;
707 interrupts = <0 36 0x04>;
0e87e043 708 clocks = <&clks 125>;
7d740f87
SG		 709 status = "disabled";
710 };
711
7b7d6727 712 i2c2: i2c@021a4000 {
7d740f87
SG		 713 #address-cells = <1>;
714 #size-cells = <0>;
5bdfba29 715 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 716 reg = <0x021a4000 0x4000>;
717 interrupts = <0 37 0x04>;
0e87e043 718 clocks = <&clks 126>;
7d740f87
SG		 719 status = "disabled";
720 };
721
7b7d6727 722 i2c3: i2c@021a8000 {
7d740f87
SG		 723 #address-cells = <1>;
724 #size-cells = <0>;
5bdfba29 725 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 726 reg = <0x021a8000 0x4000>;
727 interrupts = <0 38 0x04>;
0e87e043 728 clocks = <&clks 127>;
7d740f87
SG		 729 status = "disabled";
730 };
731
732 romcp@021ac000 {
733 reg = <0x021ac000 0x4000>;
734 };
735
7b7d6727 736 mmdc0: mmdc@021b0000 { /* MMDC0 */
7d740f87
SG		 737 compatible = "fsl,imx6q-mmdc";
738 reg = <0x021b0000 0x4000>;
739 };
740
7b7d6727 741 mmdc1: mmdc@021b4000 { /* MMDC1 */
7d740f87
SG		 742 reg = <0x021b4000 0x4000>;
743 };
744
745 weim@021b8000 {
746 reg = <0x021b8000 0x4000>;
747 interrupts = <0 14 0x04>;
748 };
749
750 ocotp@021bc000 {
96574a6d 751 compatible = "fsl,imx6q-ocotp";
7d740f87
SG		 752 reg = <0x021bc000 0x4000>;
753 };
754
755 ocotp@021c0000 {
756 reg = <0x021c0000 0x4000>;
757 interrupts = <0 21 0x04>;
758 };
759
760 tzasc@021d0000 { /* TZASC1 */
761 reg = <0x021d0000 0x4000>;
762 interrupts = <0 108 0x04>;
763 };
764
765 tzasc@021d4000 { /* TZASC2 */
766 reg = <0x021d4000 0x4000>;
767 interrupts = <0 109 0x04>;
768 };
769
7b7d6727 770 audmux: audmux@021d8000 {
f965cd55 771 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 772 reg = <0x021d8000 0x4000>;
f965cd55 773 status = "disabled";
7d740f87
SG		 774 };
775
776 mipi@021dc000 { /* MIPI-CSI */
777 reg = <0x021dc000 0x4000>;
778 };
779
780 mipi@021e0000 { /* MIPI-DSI */
781 reg = <0x021e0000 0x4000>;
782 };
783
784 vdoa@021e4000 {
785 reg = <0x021e4000 0x4000>;
786 interrupts = <0 18 0x04>;
787 };
788
0c456cfa 789 uart2: serial@021e8000 {
7d740f87
SG		 790 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
791 reg = <0x021e8000 0x4000>;
792 interrupts = <0 27 0x04>;
0e87e043
SG		 793 clocks = <&clks 160>, <&clks 161>;
794 clock-names = "ipg", "per";
7d740f87
SG		 795 status = "disabled";
796 };
797
0c456cfa 798 uart3: serial@021ec000 {
7d740f87
SG		 799 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
800 reg = <0x021ec000 0x4000>;
801 interrupts = <0 28 0x04>;
0e87e043
SG		 802 clocks = <&clks 160>, <&clks 161>;
803 clock-names = "ipg", "per";
7d740f87
SG		 804 status = "disabled";
805 };
806
0c456cfa 807 uart4: serial@021f0000 {
7d740f87
SG		 808 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
809 reg = <0x021f0000 0x4000>;
810 interrupts = <0 29 0x04>;
0e87e043
SG		 811 clocks = <&clks 160>, <&clks 161>;
812 clock-names = "ipg", "per";
7d740f87
SG		 813 status = "disabled";
814 };
815
0c456cfa 816 uart5: serial@021f4000 {
7d740f87
SG		 817 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
818 reg = <0x021f4000 0x4000>;
819 interrupts = <0 30 0x04>;
0e87e043
SG		 820 clocks = <&clks 160>, <&clks 161>;
821 clock-names = "ipg", "per";
7d740f87
SG		 822 status = "disabled";
823 };
824 };
91660d74
SH		 825
826 ipu1: ipu@02400000 {
827 #crtc-cells = <1>;
828 compatible = "fsl,imx6q-ipu";
829 reg = <0x02400000 0x400000>;
830 interrupts = <0 6 0x4 0 5 0x4>;
831 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
832 clock-names = "bus", "di0", "di1";
09ebf366 833 resets = <&src 2>;
91660d74 834 };
7d740f87
SG		 835 };
836};
Linux kernel - Deliverables
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