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ARM: dts: imx6sl-evk: enable the SPI NOR
[deliverable/linux.git] / arch / arm / boot / dts / imx6sl.dtsi
CommitLineData
e29fe21c
SG		 1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include "skeleton.dtsi"
11#include "imx6sl-pinfunc.h"
12#include <dt-bindings/clock/imx6sl-clock.h>
13
14/ {
15 aliases {
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SG		 16 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 gpio3 = &gpio4;
20 gpio4 = &gpio5;
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FE		 21 serial0 = &uart1;
22 serial1 = &uart2;
23 serial2 = &uart3;
24 serial3 = &uart4;
25 serial4 = &uart5;
26 spi0 = &ecspi1;
27 spi1 = &ecspi2;
28 spi2 = &ecspi3;
29 spi3 = &ecspi4;
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SG		 30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <0x0>;
40 next-level-cache = <&L2>;
41 };
42 };
43
44 intc: interrupt-controller@00a01000 {
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
47 #address-cells = <1>;
48 #size-cells = <1>;
49 interrupt-controller;
50 reg = <0x00a01000 0x1000>,
51 <0x00a00100 0x100>;
52 };
53
54 clocks {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 ckil {
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
61 };
62
63 osc {
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 };
67 };
68
69 soc {
70 #address-cells = <1>;
71 #size-cells = <1>;
72 compatible = "simple-bus";
73 interrupt-parent = <&intc>;
74 ranges;
75
76 L2: l2-cache@00a02000 {
77 compatible = "arm,pl310-cache";
78 reg = <0x00a02000 0x1000>;
79 interrupts = <0 92 0x04>;
80 cache-unified;
81 cache-level = <2>;
82 arm,tag-latency = <4 2 3>;
83 arm,data-latency = <4 2 3>;
84 };
85
86 pmu {
87 compatible = "arm,cortex-a9-pmu";
88 interrupts = <0 94 0x04>;
89 };
90
91 aips1: aips-bus@02000000 {
92 compatible = "fsl,aips-bus", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0x02000000 0x100000>;
96 ranges;
97
98 spba: spba-bus@02000000 {
99 compatible = "fsl,spba-bus", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x02000000 0x40000>;
103 ranges;
104
105 spdif: spdif@02004000 {
106 reg = <0x02004000 0x4000>;
107 interrupts = <0 52 0x04>;
108 };
109
110 ecspi1: ecspi@02008000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
114 reg = <0x02008000 0x4000>;
115 interrupts = <0 31 0x04>;
116 clocks = <&clks IMX6SL_CLK_ECSPI1>,
117 <&clks IMX6SL_CLK_ECSPI1>;
118 clock-names = "ipg", "per";
119 status = "disabled";
120 };
121
122 ecspi2: ecspi@0200c000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
126 reg = <0x0200c000 0x4000>;
127 interrupts = <0 32 0x04>;
128 clocks = <&clks IMX6SL_CLK_ECSPI2>,
129 <&clks IMX6SL_CLK_ECSPI2>;
130 clock-names = "ipg", "per";
131 status = "disabled";
132 };
133
134 ecspi3: ecspi@02010000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
138 reg = <0x02010000 0x4000>;
139 interrupts = <0 33 0x04>;
140 clocks = <&clks IMX6SL_CLK_ECSPI3>,
141 <&clks IMX6SL_CLK_ECSPI3>;
142 clock-names = "ipg", "per";
143 status = "disabled";
144 };
145
146 ecspi4: ecspi@02014000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
150 reg = <0x02014000 0x4000>;
151 interrupts = <0 34 0x04>;
152 clocks = <&clks IMX6SL_CLK_ECSPI4>,
153 <&clks IMX6SL_CLK_ECSPI4>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
157
158 uart5: serial@02018000 {
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HS		 159 compatible = "fsl,imx6sl-uart",
160 "fsl,imx6q-uart", "fsl,imx21-uart";
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SG		 161 reg = <0x02018000 0x4000>;
162 interrupts = <0 30 0x04>;
163 clocks = <&clks IMX6SL_CLK_UART>,
164 <&clks IMX6SL_CLK_UART_SERIAL>;
165 clock-names = "ipg", "per";
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HS		 166 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
167 dma-names = "rx", "tx";
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SG		 168 status = "disabled";
169 };
170
171 uart1: serial@02020000 {
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HS		 172 compatible = "fsl,imx6sl-uart",
173 "fsl,imx6q-uart", "fsl,imx21-uart";
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SG		 174 reg = <0x02020000 0x4000>;
175 interrupts = <0 26 0x04>;
176 clocks = <&clks IMX6SL_CLK_UART>,
177 <&clks IMX6SL_CLK_UART_SERIAL>;
178 clock-names = "ipg", "per";
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HS		 179 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
180 dma-names = "rx", "tx";
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SG		 181 status = "disabled";
182 };
183
184 uart2: serial@02024000 {
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HS		 185 compatible = "fsl,imx6sl-uart",
186 "fsl,imx6q-uart", "fsl,imx21-uart";
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SG		 187 reg = <0x02024000 0x4000>;
188 interrupts = <0 27 0x04>;
189 clocks = <&clks IMX6SL_CLK_UART>,
190 <&clks IMX6SL_CLK_UART_SERIAL>;
191 clock-names = "ipg", "per";
72a5cebf
HS		 192 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
193 dma-names = "rx", "tx";
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SG		 194 status = "disabled";
195 };
196
197 ssi1: ssi@02028000 {
198 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
199 reg = <0x02028000 0x4000>;
200 interrupts = <0 46 0x04>;
201 clocks = <&clks IMX6SL_CLK_SSI1>;
5da826ab
SG		 202 dmas = <&sdma 37 1 0>,
203 <&sdma 38 1 0>;
204 dma-names = "rx", "tx";
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SG		 205 fsl,fifo-depth = <15>;
206 status = "disabled";
207 };
208
209 ssi2: ssi@0202c000 {
210 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
211 reg = <0x0202c000 0x4000>;
212 interrupts = <0 47 0x04>;
213 clocks = <&clks IMX6SL_CLK_SSI2>;
5da826ab
SG		 214 dmas = <&sdma 41 1 0>,
215 <&sdma 42 1 0>;
216 dma-names = "rx", "tx";
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SG		 217 fsl,fifo-depth = <15>;
218 status = "disabled";
219 };
220
221 ssi3: ssi@02030000 {
222 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
223 reg = <0x02030000 0x4000>;
224 interrupts = <0 48 0x04>;
225 clocks = <&clks IMX6SL_CLK_SSI3>;
5da826ab
SG		 226 dmas = <&sdma 45 1 0>,
227 <&sdma 46 1 0>;
228 dma-names = "rx", "tx";
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SG		 229 fsl,fifo-depth = <15>;
230 status = "disabled";
231 };
232
233 uart3: serial@02034000 {
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HS		 234 compatible = "fsl,imx6sl-uart",
235 "fsl,imx6q-uart", "fsl,imx21-uart";
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SG		 236 reg = <0x02034000 0x4000>;
237 interrupts = <0 28 0x04>;
238 clocks = <&clks IMX6SL_CLK_UART>,
239 <&clks IMX6SL_CLK_UART_SERIAL>;
240 clock-names = "ipg", "per";
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HS		 241 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
242 dma-names = "rx", "tx";
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SG		 243 status = "disabled";
244 };
245
246 uart4: serial@02038000 {
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HS		 247 compatible = "fsl,imx6sl-uart",
248 "fsl,imx6q-uart", "fsl,imx21-uart";
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SG		 249 reg = <0x02038000 0x4000>;
250 interrupts = <0 29 0x04>;
251 clocks = <&clks IMX6SL_CLK_UART>,
252 <&clks IMX6SL_CLK_UART_SERIAL>;
253 clock-names = "ipg", "per";
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HS		 254 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
255 dma-names = "rx", "tx";
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SG		 256 status = "disabled";
257 };
258 };
259
260 pwm1: pwm@02080000 {
261 #pwm-cells = <2>;
262 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
263 reg = <0x02080000 0x4000>;
264 interrupts = <0 83 0x04>;
265 clocks = <&clks IMX6SL_CLK_PWM1>,
266 <&clks IMX6SL_CLK_PWM1>;
267 clock-names = "ipg", "per";
268 };
269
270 pwm2: pwm@02084000 {
271 #pwm-cells = <2>;
272 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
273 reg = <0x02084000 0x4000>;
274 interrupts = <0 84 0x04>;
275 clocks = <&clks IMX6SL_CLK_PWM2>,
276 <&clks IMX6SL_CLK_PWM2>;
277 clock-names = "ipg", "per";
278 };
279
280 pwm3: pwm@02088000 {
281 #pwm-cells = <2>;
282 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
283 reg = <0x02088000 0x4000>;
284 interrupts = <0 85 0x04>;
285 clocks = <&clks IMX6SL_CLK_PWM3>,
286 <&clks IMX6SL_CLK_PWM3>;
287 clock-names = "ipg", "per";
288 };
289
290 pwm4: pwm@0208c000 {
291 #pwm-cells = <2>;
292 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
293 reg = <0x0208c000 0x4000>;
294 interrupts = <0 86 0x04>;
295 clocks = <&clks IMX6SL_CLK_PWM4>,
296 <&clks IMX6SL_CLK_PWM4>;
297 clock-names = "ipg", "per";
298 };
299
300 gpt: gpt@02098000 {
301 compatible = "fsl,imx6sl-gpt";
302 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>;
304 clocks = <&clks IMX6SL_CLK_GPT>,
305 <&clks IMX6SL_CLK_GPT_SERIAL>;
306 clock-names = "ipg", "per";
307 };
308
309 gpio1: gpio@0209c000 {
310 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
311 reg = <0x0209c000 0x4000>;
312 interrupts = <0 66 0x04 0 67 0x04>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318
319 gpio2: gpio@020a0000 {
320 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
321 reg = <0x020a0000 0x4000>;
322 interrupts = <0 68 0x04 0 69 0x04>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 gpio3: gpio@020a4000 {
330 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
331 reg = <0x020a4000 0x4000>;
332 interrupts = <0 70 0x04 0 71 0x04>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 };
338
339 gpio4: gpio@020a8000 {
340 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
341 reg = <0x020a8000 0x4000>;
342 interrupts = <0 72 0x04 0 73 0x04>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 };
348
349 gpio5: gpio@020ac000 {
350 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
351 reg = <0x020ac000 0x4000>;
352 interrupts = <0 74 0x04 0 75 0x04>;
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 };
358
359 kpp: kpp@020b8000 {
360 reg = <0x020b8000 0x4000>;
361 interrupts = <0 82 0x04>;
362 };
363
364 wdog1: wdog@020bc000 {
365 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
366 reg = <0x020bc000 0x4000>;
367 interrupts = <0 80 0x04>;
368 clocks = <&clks IMX6SL_CLK_DUMMY>;
369 };
370
371 wdog2: wdog@020c0000 {
372 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
373 reg = <0x020c0000 0x4000>;
374 interrupts = <0 81 0x04>;
375 clocks = <&clks IMX6SL_CLK_DUMMY>;
376 status = "disabled";
377 };
378
379 clks: ccm@020c4000 {
380 compatible = "fsl,imx6sl-ccm";
381 reg = <0x020c4000 0x4000>;
382 interrupts = <0 87 0x04 0 88 0x04>;
383 #clock-cells = <1>;
384 };
385
386 anatop: anatop@020c8000 {
387 compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
388 reg = <0x020c8000 0x1000>;
389 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
390
391 regulator-1p1@110 {
392 compatible = "fsl,anatop-regulator";
393 regulator-name = "vdd1p1";
394 regulator-min-microvolt = <800000>;
395 regulator-max-microvolt = <1375000>;
396 regulator-always-on;
397 anatop-reg-offset = <0x110>;
398 anatop-vol-bit-shift = <8>;
399 anatop-vol-bit-width = <5>;
400 anatop-min-bit-val = <4>;
401 anatop-min-voltage = <800000>;
402 anatop-max-voltage = <1375000>;
403 };
404
405 regulator-3p0@120 {
406 compatible = "fsl,anatop-regulator";
407 regulator-name = "vdd3p0";
408 regulator-min-microvolt = <2800000>;
409 regulator-max-microvolt = <3150000>;
410 regulator-always-on;
411 anatop-reg-offset = <0x120>;
412 anatop-vol-bit-shift = <8>;
413 anatop-vol-bit-width = <5>;
414 anatop-min-bit-val = <0>;
415 anatop-min-voltage = <2625000>;
416 anatop-max-voltage = <3400000>;
417 };
418
419 regulator-2p5@130 {
420 compatible = "fsl,anatop-regulator";
421 regulator-name = "vdd2p5";
422 regulator-min-microvolt = <2100000>;
423 regulator-max-microvolt = <2850000>;
424 regulator-always-on;
425 anatop-reg-offset = <0x130>;
426 anatop-vol-bit-shift = <8>;
427 anatop-vol-bit-width = <5>;
428 anatop-min-bit-val = <0>;
429 anatop-min-voltage = <2100000>;
430 anatop-max-voltage = <2850000>;
431 };
432
433 reg_arm: regulator-vddcore@140 {
434 compatible = "fsl,anatop-regulator";
435 regulator-name = "cpu";
436 regulator-min-microvolt = <725000>;
437 regulator-max-microvolt = <1450000>;
438 regulator-always-on;
439 anatop-reg-offset = <0x140>;
440 anatop-vol-bit-shift = <0>;
441 anatop-vol-bit-width = <5>;
442 anatop-delay-reg-offset = <0x170>;
443 anatop-delay-bit-shift = <24>;
444 anatop-delay-bit-width = <2>;
445 anatop-min-bit-val = <1>;
446 anatop-min-voltage = <725000>;
447 anatop-max-voltage = <1450000>;
448 };
449
450 reg_pu: regulator-vddpu@140 {
451 compatible = "fsl,anatop-regulator";
452 regulator-name = "vddpu";
453 regulator-min-microvolt = <725000>;
454 regulator-max-microvolt = <1450000>;
455 regulator-always-on;
456 anatop-reg-offset = <0x140>;
457 anatop-vol-bit-shift = <9>;
458 anatop-vol-bit-width = <5>;
459 anatop-delay-reg-offset = <0x170>;
460 anatop-delay-bit-shift = <26>;
461 anatop-delay-bit-width = <2>;
462 anatop-min-bit-val = <1>;
463 anatop-min-voltage = <725000>;
464 anatop-max-voltage = <1450000>;
465 };
466
467 reg_soc: regulator-vddsoc@140 {
468 compatible = "fsl,anatop-regulator";
469 regulator-name = "vddsoc";
470 regulator-min-microvolt = <725000>;
471 regulator-max-microvolt = <1450000>;
472 regulator-always-on;
473 anatop-reg-offset = <0x140>;
474 anatop-vol-bit-shift = <18>;
475 anatop-vol-bit-width = <5>;
476 anatop-delay-reg-offset = <0x170>;
477 anatop-delay-bit-shift = <28>;
478 anatop-delay-bit-width = <2>;
479 anatop-min-bit-val = <1>;
480 anatop-min-voltage = <725000>;
481 anatop-max-voltage = <1450000>;
482 };
483 };
484
485 usbphy1: usbphy@020c9000 {
486 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
487 reg = <0x020c9000 0x1000>;
488 interrupts = <0 44 0x04>;
489 clocks = <&clks IMX6SL_CLK_USBPHY1>;
490 };
491
492 usbphy2: usbphy@020ca000 {
493 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
494 reg = <0x020ca000 0x1000>;
495 interrupts = <0 45 0x04>;
496 clocks = <&clks IMX6SL_CLK_USBPHY2>;
497 };
498
499 snvs@020cc000 {
500 compatible = "fsl,sec-v4.0-mon", "simple-bus";
501 #address-cells = <1>;
502 #size-cells = <1>;
503 ranges = <0 0x020cc000 0x4000>;
504
505 snvs-rtc-lp@34 {
506 compatible = "fsl,sec-v4.0-mon-rtc-lp";
507 reg = <0x34 0x58>;
508 interrupts = <0 19 0x04 0 20 0x04>;
509 };
510 };
511
512 epit1: epit@020d0000 {
513 reg = <0x020d0000 0x4000>;
514 interrupts = <0 56 0x04>;
515 };
516
517 epit2: epit@020d4000 {
518 reg = <0x020d4000 0x4000>;
519 interrupts = <0 57 0x04>;
520 };
521
522 src: src@020d8000 {
523 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
524 reg = <0x020d8000 0x4000>;
525 interrupts = <0 91 0x04 0 96 0x04>;
526 #reset-cells = <1>;
527 };
528
529 gpc: gpc@020dc000 {
530 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
531 reg = <0x020dc000 0x4000>;
532 interrupts = <0 89 0x04>;
533 };
e03d10f9
FD		 534
535 gpr: iomuxc-gpr@020e0000 {
536 compatible = "fsl,imx6sl-iomuxc-gpr", "syscon";
537 reg = <0x020e0000 0x38>;
538 };
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SG		 539
540 iomuxc: iomuxc@020e0000 {
541 compatible = "fsl,imx6sl-iomuxc";
542 reg = <0x020e0000 0x4000>;
543
dc108920
HS		 544 ecspi1 {
545 pinctrl_ecspi1_1: ecspi1grp-1 {
546 fsl,pins = <
547 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
548 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
549 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
550 >;
551 };
552 };
553
e29fe21c
SG		 554 fec {
555 pinctrl_fec_1: fecgrp-1 {
556 fsl,pins = <
557 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
558 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
559 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
560 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
561 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
562 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
563 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
564 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
565 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
566 >;
567 };
568 };
569
570 uart1 {
571 pinctrl_uart1_1: uart1grp-1 {
572 fsl,pins = <
573 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
574 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
575 >;
576 };
577 };
578
6022232b
PC		 579 usbotg1 {
580 pinctrl_usbotg1_1: usbotg1grp-1 {
581 fsl,pins = <
582 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
583 >;
584 };
585
586 pinctrl_usbotg1_2: usbotg1grp-2 {
587 fsl,pins = <
588 MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
589 >;
590 };
591
592 pinctrl_usbotg1_3: usbotg1grp-3 {
593 fsl,pins = <
594 MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
595 >;
596 };
597
598 pinctrl_usbotg1_4: usbotg1grp-4 {
599 fsl,pins = <
600 MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
601 >;
602 };
603
604 pinctrl_usbotg1_5: usbotg1grp-5 {
605 fsl,pins = <
606 MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
607 >;
608 };
609 };
610
611 usbotg2 {
612 pinctrl_usbotg2_1: usbotg2grp-1 {
613 fsl,pins = <
614 MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
615 >;
616 };
617
618 pinctrl_usbotg2_2: usbotg2grp-2 {
619 fsl,pins = <
620 MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
621 >;
622 };
623
624 pinctrl_usbotg2_3: usbotg2grp-3 {
625 fsl,pins = <
626 MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
627 >;
628 };
629
630 pinctrl_usbotg2_4: usbotg2grp-4 {
631 fsl,pins = <
632 MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
633 >;
634 };
635 };
636
e29fe21c
SG		 637 usdhc1 {
638 pinctrl_usdhc1_1: usdhc1grp-1 {
639 fsl,pins = <
640 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
641 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
642 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
643 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
644 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
645 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
646 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
647 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
648 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
649 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
650 >;
651 };
fa87dfd6
DA		 652
653 pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
654 fsl,pins = <
655 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
656 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
657 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
658 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
659 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
660 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
661 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
662 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
663 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
664 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
665 >;
666 };
667
668 pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
669 fsl,pins = <
670 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
671 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
672 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
673 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
674 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
675 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
676 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
677 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
678 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
679 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
680 >;
681 };
682
683
e29fe21c
SG		 684 };
685
686 usdhc2 {
687 pinctrl_usdhc2_1: usdhc2grp-1 {
688 fsl,pins = <
689 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
690 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
691 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
692 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
693 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
694 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
695 >;
696 };
fa87dfd6
DA		 697
698 pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
699 fsl,pins = <
700 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
701 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
702 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
703 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
704 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
705 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
706 >;
707 };
708
709 pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
710 fsl,pins = <
711 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
712 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
713 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
714 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
715 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
716 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
717 >;
718 };
719
e29fe21c
SG		 720 };
721
722 usdhc3 {
723 pinctrl_usdhc3_1: usdhc3grp-1 {
724 fsl,pins = <
725 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
726 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
727 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
728 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
729 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
730 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
731 >;
732 };
fa87dfd6
DA		 733
734 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
735 fsl,pins = <
736 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
737 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
738 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
739 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
740 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
741 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
742 >;
743 };
744
745 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
746 fsl,pins = <
747 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
748 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
749 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
750 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
751 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
752 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
753 >;
754 };
e29fe21c
SG		 755 };
756 };
757
758 csi: csi@020e4000 {
759 reg = <0x020e4000 0x4000>;
760 interrupts = <0 7 0x04>;
761 };
762
763 spdc: spdc@020e8000 {
764 reg = <0x020e8000 0x4000>;
765 interrupts = <0 6 0x04>;
766 };
767
768 sdma: sdma@020ec000 {
769 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
770 reg = <0x020ec000 0x4000>;
771 interrupts = <0 2 0x04>;
772 clocks = <&clks IMX6SL_CLK_SDMA>,
773 <&clks IMX6SL_CLK_SDMA>;
774 clock-names = "ipg", "ahb";
fb72bb21 775 #dma-cells = <3>;
44a26877
SG		 776 /* imx6sl reuses imx6q sdma firmware */
777 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
e29fe21c
SG		 778 };
779
780 pxp: pxp@020f0000 {
781 reg = <0x020f0000 0x4000>;
782 interrupts = <0 98 0x04>;
783 };
784
785 epdc: epdc@020f4000 {
786 reg = <0x020f4000 0x4000>;
787 interrupts = <0 97 0x04>;
788 };
789
790 lcdif: lcdif@020f8000 {
791 reg = <0x020f8000 0x4000>;
792 interrupts = <0 39 0x04>;
793 };
794
795 dcp: dcp@020fc000 {
796 reg = <0x020fc000 0x4000>;
797 interrupts = <0 99 0x04>;
798 };
799 };
800
801 aips2: aips-bus@02100000 {
802 compatible = "fsl,aips-bus", "simple-bus";
803 #address-cells = <1>;
804 #size-cells = <1>;
805 reg = <0x02100000 0x100000>;
806 ranges;
807
808 usbotg1: usb@02184000 {
809 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
810 reg = <0x02184000 0x200>;
811 interrupts = <0 43 0x04>;
812 clocks = <&clks IMX6SL_CLK_USBOH3>;
813 fsl,usbphy = <&usbphy1>;
814 fsl,usbmisc = <&usbmisc 0>;
815 status = "disabled";
816 };
817
818 usbotg2: usb@02184200 {
819 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
820 reg = <0x02184200 0x200>;
6022232b 821 interrupts = <0 42 0x04>;
e29fe21c
SG		 822 clocks = <&clks IMX6SL_CLK_USBOH3>;
823 fsl,usbphy = <&usbphy2>;
824 fsl,usbmisc = <&usbmisc 1>;
825 status = "disabled";
826 };
827
828 usbh: usb@02184400 {
829 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
830 reg = <0x02184400 0x200>;
6022232b 831 interrupts = <0 40 0x04>;
e29fe21c
SG		 832 clocks = <&clks IMX6SL_CLK_USBOH3>;
833 fsl,usbmisc = <&usbmisc 2>;
834 status = "disabled";
835 };
836
837 usbmisc: usbmisc@02184800 {
838 #index-cells = <1>;
839 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
840 reg = <0x02184800 0x200>;
841 clocks = <&clks IMX6SL_CLK_USBOH3>;
842 };
843
844 fec: ethernet@02188000 {
845 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
846 reg = <0x02188000 0x4000>;
847 interrupts = <0 114 0x04>;
848 clocks = <&clks IMX6SL_CLK_ENET_REF>,
849 <&clks IMX6SL_CLK_ENET_REF>;
850 clock-names = "ipg", "ahb";
851 status = "disabled";
852 };
853
854 usdhc1: usdhc@02190000 {
855 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
856 reg = <0x02190000 0x4000>;
857 interrupts = <0 22 0x04>;
858 clocks = <&clks IMX6SL_CLK_USDHC1>,
859 <&clks IMX6SL_CLK_USDHC1>,
860 <&clks IMX6SL_CLK_USDHC1>;
861 clock-names = "ipg", "ahb", "per";
862 bus-width = <4>;
863 status = "disabled";
864 };
865
866 usdhc2: usdhc@02194000 {
867 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
868 reg = <0x02194000 0x4000>;
869 interrupts = <0 23 0x04>;
870 clocks = <&clks IMX6SL_CLK_USDHC2>,
871 <&clks IMX6SL_CLK_USDHC2>,
872 <&clks IMX6SL_CLK_USDHC2>;
873 clock-names = "ipg", "ahb", "per";
874 bus-width = <4>;
875 status = "disabled";
876 };
877
878 usdhc3: usdhc@02198000 {
879 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
880 reg = <0x02198000 0x4000>;
881 interrupts = <0 24 0x04>;
882 clocks = <&clks IMX6SL_CLK_USDHC3>,
883 <&clks IMX6SL_CLK_USDHC3>,
884 <&clks IMX6SL_CLK_USDHC3>;
885 clock-names = "ipg", "ahb", "per";
886 bus-width = <4>;
887 status = "disabled";
888 };
889
890 usdhc4: usdhc@0219c000 {
891 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
892 reg = <0x0219c000 0x4000>;
893 interrupts = <0 25 0x04>;
894 clocks = <&clks IMX6SL_CLK_USDHC4>,
895 <&clks IMX6SL_CLK_USDHC4>,
896 <&clks IMX6SL_CLK_USDHC4>;
897 clock-names = "ipg", "ahb", "per";
898 bus-width = <4>;
899 status = "disabled";
900 };
901
902 i2c1: i2c@021a0000 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
906 reg = <0x021a0000 0x4000>;
907 interrupts = <0 36 0x04>;
908 clocks = <&clks IMX6SL_CLK_I2C1>;
909 status = "disabled";
910 };
911
912 i2c2: i2c@021a4000 {
913 #address-cells = <1>;
914 #size-cells = <0>;
915 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
916 reg = <0x021a4000 0x4000>;
917 interrupts = <0 37 0x04>;
918 clocks = <&clks IMX6SL_CLK_I2C2>;
919 status = "disabled";
920 };
921
922 i2c3: i2c@021a8000 {
923 #address-cells = <1>;
924 #size-cells = <0>;
925 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
926 reg = <0x021a8000 0x4000>;
927 interrupts = <0 38 0x04>;
928 clocks = <&clks IMX6SL_CLK_I2C3>;
929 status = "disabled";
930 };
931
932 mmdc: mmdc@021b0000 {
933 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
934 reg = <0x021b0000 0x4000>;
935 };
936
937 rngb: rngb@021b4000 {
938 reg = <0x021b4000 0x4000>;
939 interrupts = <0 5 0x04>;
940 };
941
942 weim: weim@021b8000 {
943 reg = <0x021b8000 0x4000>;
944 interrupts = <0 14 0x04>;
945 };
946
947 ocotp: ocotp@021bc000 {
948 compatible = "fsl,imx6sl-ocotp";
949 reg = <0x021bc000 0x4000>;
950 };
951
952 audmux: audmux@021d8000 {
953 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
954 reg = <0x021d8000 0x4000>;
955 status = "disabled";
956 };
957 };
958 };
959};
Linux kernel - Deliverables
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