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ARM: dts: imx6qdl: Add mmc aliases
[deliverable/linux.git] / arch / arm / boot / dts / imx6sl.dtsi
CommitLineData
e29fe21c
SG		 1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
13088c23 10#include <dt-bindings/interrupt-controller/irq.h>
e29fe21c
SG		 11#include "skeleton.dtsi"
12#include "imx6sl-pinfunc.h"
13#include <dt-bindings/clock/imx6sl-clock.h>
14
15/ {
16 aliases {
e29fe21c
SG		 17 gpio0 = &gpio1;
18 gpio1 = &gpio2;
19 gpio2 = &gpio3;
20 gpio3 = &gpio4;
21 gpio4 = &gpio5;
640a7f3f
FE		 22 serial0 = &uart1;
23 serial1 = &uart2;
24 serial2 = &uart3;
25 serial3 = &uart4;
26 serial4 = &uart5;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &ecspi3;
30 spi3 = &ecspi4;
8189c51f
PC		 31 usbphy0 = &usbphy1;
32 usbphy1 = &usbphy2;
e29fe21c
SG		 33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 compatible = "arm,cortex-a9";
41 device_type = "cpu";
42 reg = <0x0>;
43 next-level-cache = <&L2>;
b0d300d3
JT		 44 operating-points = <
45 /* kHz uV */
46 996000 1275000
47 792000 1175000
48 396000 975000
49 >;
50 fsl,soc-operating-points = <
51 /* ARM kHz SOC-PU uV */
52 996000 1225000
53 792000 1175000
54 396000 1175000
55 >;
56 clock-latency = <61036>; /* two CLK32 periods */
57 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
58 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
59 <&clks IMX6SL_CLK_PLL1_SYS>;
60 clock-names = "arm", "pll2_pfd2_396m", "step",
61 "pll1_sw", "pll1_sys";
62 arm-supply = <&reg_arm>;
63 pu-supply = <&reg_pu>;
64 soc-supply = <&reg_soc>;
e29fe21c
SG		 65 };
66 };
67
68 intc: interrupt-controller@00a01000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 interrupt-controller;
74 reg = <0x00a01000 0x1000>,
75 <0x00a00100 0x100>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ckil {
83 compatible = "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 osc {
88 compatible = "fixed-clock";
89 clock-frequency = <24000000>;
90 };
91 };
92
93 soc {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "simple-bus";
97 interrupt-parent = <&intc>;
98 ranges;
99
248f15a3
AH		 100 ocram: sram@00900000 {
101 compatible = "mmio-sram";
102 reg = <0x00900000 0x20000>;
103 clocks = <&clks IMX6SL_CLK_OCRAM>;
104 };
105
e29fe21c
SG		 106 L2: l2-cache@00a02000 {
107 compatible = "arm,pl310-cache";
108 reg = <0x00a02000 0x1000>;
13088c23 109 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 110 cache-unified;
111 cache-level = <2>;
112 arm,tag-latency = <4 2 3>;
113 arm,data-latency = <4 2 3>;
114 };
115
116 pmu {
117 compatible = "arm,cortex-a9-pmu";
13088c23 118 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 119 };
120
121 aips1: aips-bus@02000000 {
122 compatible = "fsl,aips-bus", "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 reg = <0x02000000 0x100000>;
126 ranges;
127
128 spba: spba-bus@02000000 {
129 compatible = "fsl,spba-bus", "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 reg = <0x02000000 0x40000>;
133 ranges;
134
135 spdif: spdif@02004000 {
136 reg = <0x02004000 0x4000>;
13088c23 137 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 138 };
139
140 ecspi1: ecspi@02008000 {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
144 reg = <0x02008000 0x4000>;
13088c23 145 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 146 clocks = <&clks IMX6SL_CLK_ECSPI1>,
147 <&clks IMX6SL_CLK_ECSPI1>;
148 clock-names = "ipg", "per";
149 status = "disabled";
150 };
151
152 ecspi2: ecspi@0200c000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
156 reg = <0x0200c000 0x4000>;
13088c23 157 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 158 clocks = <&clks IMX6SL_CLK_ECSPI2>,
159 <&clks IMX6SL_CLK_ECSPI2>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162 };
163
164 ecspi3: ecspi@02010000 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
168 reg = <0x02010000 0x4000>;
13088c23 169 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 170 clocks = <&clks IMX6SL_CLK_ECSPI3>,
171 <&clks IMX6SL_CLK_ECSPI3>;
172 clock-names = "ipg", "per";
173 status = "disabled";
174 };
175
176 ecspi4: ecspi@02014000 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
180 reg = <0x02014000 0x4000>;
13088c23 181 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 182 clocks = <&clks IMX6SL_CLK_ECSPI4>,
183 <&clks IMX6SL_CLK_ECSPI4>;
184 clock-names = "ipg", "per";
185 status = "disabled";
186 };
187
188 uart5: serial@02018000 {
6eb85f91
HS		 189 compatible = "fsl,imx6sl-uart",
190 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 191 reg = <0x02018000 0x4000>;
13088c23 192 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 193 clocks = <&clks IMX6SL_CLK_UART>,
194 <&clks IMX6SL_CLK_UART_SERIAL>;
195 clock-names = "ipg", "per";
72a5cebf
HS		 196 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
197 dma-names = "rx", "tx";
e29fe21c
SG		 198 status = "disabled";
199 };
200
201 uart1: serial@02020000 {
6eb85f91
HS		 202 compatible = "fsl,imx6sl-uart",
203 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 204 reg = <0x02020000 0x4000>;
13088c23 205 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 206 clocks = <&clks IMX6SL_CLK_UART>,
207 <&clks IMX6SL_CLK_UART_SERIAL>;
208 clock-names = "ipg", "per";
72a5cebf
HS		 209 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
210 dma-names = "rx", "tx";
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SG		 211 status = "disabled";
212 };
213
214 uart2: serial@02024000 {
6eb85f91
HS		 215 compatible = "fsl,imx6sl-uart",
216 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 217 reg = <0x02024000 0x4000>;
13088c23 218 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
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SG		 219 clocks = <&clks IMX6SL_CLK_UART>,
220 <&clks IMX6SL_CLK_UART_SERIAL>;
221 clock-names = "ipg", "per";
72a5cebf
HS		 222 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
223 dma-names = "rx", "tx";
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SG		 224 status = "disabled";
225 };
226
227 ssi1: ssi@02028000 {
228 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
229 reg = <0x02028000 0x4000>;
13088c23 230 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 231 clocks = <&clks IMX6SL_CLK_SSI1>;
5da826ab
SG		 232 dmas = <&sdma 37 1 0>,
233 <&sdma 38 1 0>;
234 dma-names = "rx", "tx";
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SG		 235 fsl,fifo-depth = <15>;
236 status = "disabled";
237 };
238
239 ssi2: ssi@0202c000 {
240 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
241 reg = <0x0202c000 0x4000>;
13088c23 242 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 243 clocks = <&clks IMX6SL_CLK_SSI2>;
5da826ab
SG		 244 dmas = <&sdma 41 1 0>,
245 <&sdma 42 1 0>;
246 dma-names = "rx", "tx";
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SG		 247 fsl,fifo-depth = <15>;
248 status = "disabled";
249 };
250
251 ssi3: ssi@02030000 {
252 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
253 reg = <0x02030000 0x4000>;
13088c23 254 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 255 clocks = <&clks IMX6SL_CLK_SSI3>;
5da826ab
SG		 256 dmas = <&sdma 45 1 0>,
257 <&sdma 46 1 0>;
258 dma-names = "rx", "tx";
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SG		 259 fsl,fifo-depth = <15>;
260 status = "disabled";
261 };
262
263 uart3: serial@02034000 {
6eb85f91
HS		 264 compatible = "fsl,imx6sl-uart",
265 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 266 reg = <0x02034000 0x4000>;
13088c23 267 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 268 clocks = <&clks IMX6SL_CLK_UART>,
269 <&clks IMX6SL_CLK_UART_SERIAL>;
270 clock-names = "ipg", "per";
72a5cebf
HS		 271 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
272 dma-names = "rx", "tx";
e29fe21c
SG		 273 status = "disabled";
274 };
275
276 uart4: serial@02038000 {
6eb85f91
HS		 277 compatible = "fsl,imx6sl-uart",
278 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 279 reg = <0x02038000 0x4000>;
13088c23 280 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 281 clocks = <&clks IMX6SL_CLK_UART>,
282 <&clks IMX6SL_CLK_UART_SERIAL>;
283 clock-names = "ipg", "per";
72a5cebf
HS		 284 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
285 dma-names = "rx", "tx";
e29fe21c
SG		 286 status = "disabled";
287 };
288 };
289
290 pwm1: pwm@02080000 {
291 #pwm-cells = <2>;
292 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
293 reg = <0x02080000 0x4000>;
13088c23 294 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 295 clocks = <&clks IMX6SL_CLK_PWM1>,
296 <&clks IMX6SL_CLK_PWM1>;
297 clock-names = "ipg", "per";
298 };
299
300 pwm2: pwm@02084000 {
301 #pwm-cells = <2>;
302 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
303 reg = <0x02084000 0x4000>;
13088c23 304 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 305 clocks = <&clks IMX6SL_CLK_PWM2>,
306 <&clks IMX6SL_CLK_PWM2>;
307 clock-names = "ipg", "per";
308 };
309
310 pwm3: pwm@02088000 {
311 #pwm-cells = <2>;
312 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
313 reg = <0x02088000 0x4000>;
13088c23 314 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 315 clocks = <&clks IMX6SL_CLK_PWM3>,
316 <&clks IMX6SL_CLK_PWM3>;
317 clock-names = "ipg", "per";
318 };
319
320 pwm4: pwm@0208c000 {
321 #pwm-cells = <2>;
322 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
323 reg = <0x0208c000 0x4000>;
13088c23 324 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 325 clocks = <&clks IMX6SL_CLK_PWM4>,
326 <&clks IMX6SL_CLK_PWM4>;
327 clock-names = "ipg", "per";
328 };
329
330 gpt: gpt@02098000 {
331 compatible = "fsl,imx6sl-gpt";
332 reg = <0x02098000 0x4000>;
13088c23 333 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 334 clocks = <&clks IMX6SL_CLK_GPT>,
335 <&clks IMX6SL_CLK_GPT_SERIAL>;
336 clock-names = "ipg", "per";
337 };
338
339 gpio1: gpio@0209c000 {
340 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
341 reg = <0x0209c000 0x4000>;
13088c23
TK		 342 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
343 <0 67 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
349
350 gpio2: gpio@020a0000 {
351 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
352 reg = <0x020a0000 0x4000>;
13088c23
TK		 353 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
354 <0 69 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 355 gpio-controller;
356 #gpio-cells = <2>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
359 };
360
361 gpio3: gpio@020a4000 {
362 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
363 reg = <0x020a4000 0x4000>;
13088c23
TK		 364 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
365 <0 71 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 };
371
372 gpio4: gpio@020a8000 {
373 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
374 reg = <0x020a8000 0x4000>;
13088c23
TK		 375 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
376 <0 73 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 377 gpio-controller;
378 #gpio-cells = <2>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
381 };
382
383 gpio5: gpio@020ac000 {
384 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
385 reg = <0x020ac000 0x4000>;
13088c23
TK		 386 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
387 <0 75 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 388 gpio-controller;
389 #gpio-cells = <2>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
392 };
393
394 kpp: kpp@020b8000 {
4291b645 395 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
e29fe21c 396 reg = <0x020b8000 0x4000>;
13088c23 397 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
4291b645 398 clocks = <&clks IMX6SL_CLK_DUMMY>;
e29fe21c
SG		 399 };
400
401 wdog1: wdog@020bc000 {
402 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
403 reg = <0x020bc000 0x4000>;
13088c23 404 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 405 clocks = <&clks IMX6SL_CLK_DUMMY>;
406 };
407
408 wdog2: wdog@020c0000 {
409 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
410 reg = <0x020c0000 0x4000>;
13088c23 411 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 412 clocks = <&clks IMX6SL_CLK_DUMMY>;
413 status = "disabled";
414 };
415
416 clks: ccm@020c4000 {
417 compatible = "fsl,imx6sl-ccm";
418 reg = <0x020c4000 0x4000>;
13088c23
TK		 419 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
420 <0 88 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 421 #clock-cells = <1>;
422 };
423
424 anatop: anatop@020c8000 {
d8ce823f
SG		 425 compatible = "fsl,imx6sl-anatop",
426 "fsl,imx6q-anatop",
427 "syscon", "simple-bus";
e29fe21c 428 reg = <0x020c8000 0x1000>;
13088c23
TK		 429 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
430 <0 54 IRQ_TYPE_LEVEL_HIGH>,
431 <0 127 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 432
433 regulator-1p1@110 {
434 compatible = "fsl,anatop-regulator";
435 regulator-name = "vdd1p1";
436 regulator-min-microvolt = <800000>;
437 regulator-max-microvolt = <1375000>;
438 regulator-always-on;
439 anatop-reg-offset = <0x110>;
440 anatop-vol-bit-shift = <8>;
441 anatop-vol-bit-width = <5>;
442 anatop-min-bit-val = <4>;
443 anatop-min-voltage = <800000>;
444 anatop-max-voltage = <1375000>;
445 };
446
447 regulator-3p0@120 {
448 compatible = "fsl,anatop-regulator";
449 regulator-name = "vdd3p0";
450 regulator-min-microvolt = <2800000>;
451 regulator-max-microvolt = <3150000>;
452 regulator-always-on;
453 anatop-reg-offset = <0x120>;
454 anatop-vol-bit-shift = <8>;
455 anatop-vol-bit-width = <5>;
456 anatop-min-bit-val = <0>;
457 anatop-min-voltage = <2625000>;
458 anatop-max-voltage = <3400000>;
459 };
460
461 regulator-2p5@130 {
462 compatible = "fsl,anatop-regulator";
463 regulator-name = "vdd2p5";
464 regulator-min-microvolt = <2100000>;
465 regulator-max-microvolt = <2850000>;
466 regulator-always-on;
467 anatop-reg-offset = <0x130>;
468 anatop-vol-bit-shift = <8>;
469 anatop-vol-bit-width = <5>;
470 anatop-min-bit-val = <0>;
471 anatop-min-voltage = <2100000>;
472 anatop-max-voltage = <2850000>;
473 };
474
475 reg_arm: regulator-vddcore@140 {
476 compatible = "fsl,anatop-regulator";
118c98a6 477 regulator-name = "vddarm";
e29fe21c
SG		 478 regulator-min-microvolt = <725000>;
479 regulator-max-microvolt = <1450000>;
480 regulator-always-on;
481 anatop-reg-offset = <0x140>;
482 anatop-vol-bit-shift = <0>;
483 anatop-vol-bit-width = <5>;
484 anatop-delay-reg-offset = <0x170>;
485 anatop-delay-bit-shift = <24>;
486 anatop-delay-bit-width = <2>;
487 anatop-min-bit-val = <1>;
488 anatop-min-voltage = <725000>;
489 anatop-max-voltage = <1450000>;
490 };
491
492 reg_pu: regulator-vddpu@140 {
493 compatible = "fsl,anatop-regulator";
494 regulator-name = "vddpu";
495 regulator-min-microvolt = <725000>;
496 regulator-max-microvolt = <1450000>;
497 regulator-always-on;
498 anatop-reg-offset = <0x140>;
499 anatop-vol-bit-shift = <9>;
500 anatop-vol-bit-width = <5>;
501 anatop-delay-reg-offset = <0x170>;
502 anatop-delay-bit-shift = <26>;
503 anatop-delay-bit-width = <2>;
504 anatop-min-bit-val = <1>;
505 anatop-min-voltage = <725000>;
506 anatop-max-voltage = <1450000>;
507 };
508
509 reg_soc: regulator-vddsoc@140 {
510 compatible = "fsl,anatop-regulator";
511 regulator-name = "vddsoc";
512 regulator-min-microvolt = <725000>;
513 regulator-max-microvolt = <1450000>;
514 regulator-always-on;
515 anatop-reg-offset = <0x140>;
516 anatop-vol-bit-shift = <18>;
517 anatop-vol-bit-width = <5>;
518 anatop-delay-reg-offset = <0x170>;
519 anatop-delay-bit-shift = <28>;
520 anatop-delay-bit-width = <2>;
521 anatop-min-bit-val = <1>;
522 anatop-min-voltage = <725000>;
523 anatop-max-voltage = <1450000>;
524 };
525 };
526
527 usbphy1: usbphy@020c9000 {
528 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
529 reg = <0x020c9000 0x1000>;
13088c23 530 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 531 clocks = <&clks IMX6SL_CLK_USBPHY1>;
76a38855 532 fsl,anatop = <&anatop>;
e29fe21c
SG		 533 };
534
535 usbphy2: usbphy@020ca000 {
536 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
537 reg = <0x020ca000 0x1000>;
13088c23 538 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 539 clocks = <&clks IMX6SL_CLK_USBPHY2>;
76a38855 540 fsl,anatop = <&anatop>;
e29fe21c
SG		 541 };
542
543 snvs@020cc000 {
544 compatible = "fsl,sec-v4.0-mon", "simple-bus";
545 #address-cells = <1>;
546 #size-cells = <1>;
547 ranges = <0 0x020cc000 0x4000>;
548
549 snvs-rtc-lp@34 {
550 compatible = "fsl,sec-v4.0-mon-rtc-lp";
551 reg = <0x34 0x58>;
13088c23
TK		 552 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
553 <0 20 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 554 };
555 };
556
557 epit1: epit@020d0000 {
558 reg = <0x020d0000 0x4000>;
13088c23 559 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 560 };
561
562 epit2: epit@020d4000 {
563 reg = <0x020d4000 0x4000>;
13088c23 564 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 565 };
566
567 src: src@020d8000 {
568 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
569 reg = <0x020d8000 0x4000>;
13088c23
TK		 570 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
571 <0 96 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 572 #reset-cells = <1>;
573 };
574
575 gpc: gpc@020dc000 {
576 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
577 reg = <0x020dc000 0x4000>;
13088c23 578 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 579 };
580
e03d10f9 581 gpr: iomuxc-gpr@020e0000 {
5f7adc97
SG		 582 compatible = "fsl,imx6sl-iomuxc-gpr",
583 "fsl,imx6q-iomuxc-gpr", "syscon";
e03d10f9
FD		 584 reg = <0x020e0000 0x38>;
585 };
e29fe21c
SG		 586
587 iomuxc: iomuxc@020e0000 {
588 compatible = "fsl,imx6sl-iomuxc";
589 reg = <0x020e0000 0x4000>;
e29fe21c
SG		 590 };
591
592 csi: csi@020e4000 {
593 reg = <0x020e4000 0x4000>;
13088c23 594 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 595 };
596
597 spdc: spdc@020e8000 {
598 reg = <0x020e8000 0x4000>;
13088c23 599 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 600 };
601
602 sdma: sdma@020ec000 {
603 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
604 reg = <0x020ec000 0x4000>;
13088c23 605 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 606 clocks = <&clks IMX6SL_CLK_SDMA>,
607 <&clks IMX6SL_CLK_SDMA>;
608 clock-names = "ipg", "ahb";
fb72bb21 609 #dma-cells = <3>;
44a26877
SG		 610 /* imx6sl reuses imx6q sdma firmware */
611 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
e29fe21c
SG		 612 };
613
614 pxp: pxp@020f0000 {
615 reg = <0x020f0000 0x4000>;
13088c23 616 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 617 };
618
619 epdc: epdc@020f4000 {
620 reg = <0x020f4000 0x4000>;
13088c23 621 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 622 };
623
624 lcdif: lcdif@020f8000 {
625 reg = <0x020f8000 0x4000>;
13088c23 626 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 627 };
628
629 dcp: dcp@020fc000 {
630 reg = <0x020fc000 0x4000>;
13088c23 631 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 632 };
633 };
634
635 aips2: aips-bus@02100000 {
636 compatible = "fsl,aips-bus", "simple-bus";
637 #address-cells = <1>;
638 #size-cells = <1>;
639 reg = <0x02100000 0x100000>;
640 ranges;
641
642 usbotg1: usb@02184000 {
643 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
644 reg = <0x02184000 0x200>;
13088c23 645 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 646 clocks = <&clks IMX6SL_CLK_USBOH3>;
647 fsl,usbphy = <&usbphy1>;
648 fsl,usbmisc = <&usbmisc 0>;
649 status = "disabled";
650 };
651
652 usbotg2: usb@02184200 {
653 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
654 reg = <0x02184200 0x200>;
13088c23 655 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 656 clocks = <&clks IMX6SL_CLK_USBOH3>;
657 fsl,usbphy = <&usbphy2>;
658 fsl,usbmisc = <&usbmisc 1>;
659 status = "disabled";
660 };
661
662 usbh: usb@02184400 {
663 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
664 reg = <0x02184400 0x200>;
13088c23 665 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 666 clocks = <&clks IMX6SL_CLK_USBOH3>;
667 fsl,usbmisc = <&usbmisc 2>;
668 status = "disabled";
669 };
670
671 usbmisc: usbmisc@02184800 {
672 #index-cells = <1>;
673 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
674 reg = <0x02184800 0x200>;
675 clocks = <&clks IMX6SL_CLK_USBOH3>;
676 };
677
678 fec: ethernet@02188000 {
679 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
680 reg = <0x02188000 0x4000>;
13088c23 681 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 682 clocks = <&clks IMX6SL_CLK_ENET_REF>,
683 <&clks IMX6SL_CLK_ENET_REF>;
684 clock-names = "ipg", "ahb";
685 status = "disabled";
686 };
687
688 usdhc1: usdhc@02190000 {
689 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
690 reg = <0x02190000 0x4000>;
13088c23 691 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 692 clocks = <&clks IMX6SL_CLK_USDHC1>,
693 <&clks IMX6SL_CLK_USDHC1>,
694 <&clks IMX6SL_CLK_USDHC1>;
695 clock-names = "ipg", "ahb", "per";
696 bus-width = <4>;
697 status = "disabled";
698 };
699
700 usdhc2: usdhc@02194000 {
701 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
702 reg = <0x02194000 0x4000>;
13088c23 703 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 704 clocks = <&clks IMX6SL_CLK_USDHC2>,
705 <&clks IMX6SL_CLK_USDHC2>,
706 <&clks IMX6SL_CLK_USDHC2>;
707 clock-names = "ipg", "ahb", "per";
708 bus-width = <4>;
709 status = "disabled";
710 };
711
712 usdhc3: usdhc@02198000 {
713 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
714 reg = <0x02198000 0x4000>;
13088c23 715 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 716 clocks = <&clks IMX6SL_CLK_USDHC3>,
717 <&clks IMX6SL_CLK_USDHC3>,
718 <&clks IMX6SL_CLK_USDHC3>;
719 clock-names = "ipg", "ahb", "per";
720 bus-width = <4>;
721 status = "disabled";
722 };
723
724 usdhc4: usdhc@0219c000 {
725 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
726 reg = <0x0219c000 0x4000>;
13088c23 727 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 728 clocks = <&clks IMX6SL_CLK_USDHC4>,
729 <&clks IMX6SL_CLK_USDHC4>,
730 <&clks IMX6SL_CLK_USDHC4>;
731 clock-names = "ipg", "ahb", "per";
732 bus-width = <4>;
733 status = "disabled";
734 };
735
736 i2c1: i2c@021a0000 {
737 #address-cells = <1>;
738 #size-cells = <0>;
739 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
740 reg = <0x021a0000 0x4000>;
13088c23 741 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 742 clocks = <&clks IMX6SL_CLK_I2C1>;
743 status = "disabled";
744 };
745
746 i2c2: i2c@021a4000 {
747 #address-cells = <1>;
748 #size-cells = <0>;
749 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
750 reg = <0x021a4000 0x4000>;
13088c23 751 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 752 clocks = <&clks IMX6SL_CLK_I2C2>;
753 status = "disabled";
754 };
755
756 i2c3: i2c@021a8000 {
757 #address-cells = <1>;
758 #size-cells = <0>;
759 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
760 reg = <0x021a8000 0x4000>;
13088c23 761 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 762 clocks = <&clks IMX6SL_CLK_I2C3>;
763 status = "disabled";
764 };
765
766 mmdc: mmdc@021b0000 {
767 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
768 reg = <0x021b0000 0x4000>;
769 };
770
771 rngb: rngb@021b4000 {
772 reg = <0x021b4000 0x4000>;
13088c23 773 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 774 };
775
776 weim: weim@021b8000 {
777 reg = <0x021b8000 0x4000>;
13088c23 778 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 779 };
780
781 ocotp: ocotp@021bc000 {
782 compatible = "fsl,imx6sl-ocotp";
783 reg = <0x021bc000 0x4000>;
784 };
785
786 audmux: audmux@021d8000 {
787 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
788 reg = <0x021d8000 0x4000>;
789 status = "disabled";
790 };
791 };
792 };
793};
Linux kernel - Deliverables
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