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b1d17f68 SG |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <dt-bindings/clock/imx6sx-clock.h> | |
10 | #include <dt-bindings/gpio/gpio.h> | |
93db055d | 11 | #include <dt-bindings/input/input.h> |
b1d17f68 SG |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
13 | #include "imx6sx-pinfunc.h" | |
14 | #include "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | aliases { | |
18 | can0 = &flexcan1; | |
19 | can1 = &flexcan2; | |
20 | ethernet0 = &fec1; | |
21 | ethernet1 = &fec2; | |
22 | gpio0 = &gpio1; | |
23 | gpio1 = &gpio2; | |
24 | gpio2 = &gpio3; | |
25 | gpio3 = &gpio4; | |
26 | gpio4 = &gpio5; | |
27 | gpio5 = &gpio6; | |
28 | gpio6 = &gpio7; | |
29 | i2c0 = &i2c1; | |
30 | i2c1 = &i2c2; | |
31 | i2c2 = &i2c3; | |
32 | i2c3 = &i2c4; | |
33 | mmc0 = &usdhc1; | |
34 | mmc1 = &usdhc2; | |
35 | mmc2 = &usdhc3; | |
36 | mmc3 = &usdhc4; | |
37 | serial0 = &uart1; | |
38 | serial1 = &uart2; | |
39 | serial2 = &uart3; | |
40 | serial3 = &uart4; | |
41 | serial4 = &uart5; | |
42 | serial5 = &uart6; | |
43 | spi0 = &ecspi1; | |
44 | spi1 = &ecspi2; | |
45 | spi2 = &ecspi3; | |
46 | spi3 = &ecspi4; | |
47 | spi4 = &ecspi5; | |
48 | usbphy0 = &usbphy1; | |
49 | usbphy1 = &usbphy2; | |
50 | }; | |
51 | ||
52 | cpus { | |
53 | #address-cells = <1>; | |
54 | #size-cells = <0>; | |
55 | ||
56 | cpu0: cpu@0 { | |
57 | compatible = "arm,cortex-a9"; | |
58 | device_type = "cpu"; | |
59 | reg = <0>; | |
60 | next-level-cache = <&L2>; | |
61 | operating-points = < | |
62 | /* kHz uV */ | |
63 | 996000 1250000 | |
64 | 792000 1175000 | |
65 | 396000 1075000 | |
fe4266ba | 66 | 198000 975000 |
b1d17f68 SG |
67 | >; |
68 | fsl,soc-operating-points = < | |
69 | /* ARM kHz SOC uV */ | |
70 | 996000 1175000 | |
71 | 792000 1175000 | |
72 | 396000 1175000 | |
fe4266ba | 73 | 198000 1175000 |
b1d17f68 SG |
74 | >; |
75 | clock-latency = <61036>; /* two CLK32 periods */ | |
76 | clocks = <&clks IMX6SX_CLK_ARM>, | |
77 | <&clks IMX6SX_CLK_PLL2_PFD2>, | |
78 | <&clks IMX6SX_CLK_STEP>, | |
79 | <&clks IMX6SX_CLK_PLL1_SW>, | |
80 | <&clks IMX6SX_CLK_PLL1_SYS>; | |
81 | clock-names = "arm", "pll2_pfd2_396m", "step", | |
82 | "pll1_sw", "pll1_sys"; | |
83 | arm-supply = <®_arm>; | |
84 | soc-supply = <®_soc>; | |
85 | }; | |
86 | }; | |
87 | ||
88 | intc: interrupt-controller@00a01000 { | |
89 | compatible = "arm,cortex-a9-gic"; | |
90 | #interrupt-cells = <3>; | |
91 | interrupt-controller; | |
92 | reg = <0x00a01000 0x1000>, | |
93 | <0x00a00100 0x100>; | |
b923ff6a | 94 | interrupt-parent = <&intc>; |
b1d17f68 SG |
95 | }; |
96 | ||
97 | clocks { | |
98 | #address-cells = <1>; | |
99 | #size-cells = <0>; | |
100 | ||
101 | ckil: clock@0 { | |
102 | compatible = "fixed-clock"; | |
103 | reg = <0>; | |
104 | #clock-cells = <0>; | |
105 | clock-frequency = <32768>; | |
106 | clock-output-names = "ckil"; | |
107 | }; | |
108 | ||
109 | osc: clock@1 { | |
110 | compatible = "fixed-clock"; | |
111 | reg = <1>; | |
112 | #clock-cells = <0>; | |
113 | clock-frequency = <24000000>; | |
114 | clock-output-names = "osc"; | |
115 | }; | |
116 | ||
117 | ipp_di0: clock@2 { | |
118 | compatible = "fixed-clock"; | |
119 | reg = <2>; | |
120 | #clock-cells = <0>; | |
121 | clock-frequency = <0>; | |
122 | clock-output-names = "ipp_di0"; | |
123 | }; | |
124 | ||
125 | ipp_di1: clock@3 { | |
126 | compatible = "fixed-clock"; | |
127 | reg = <3>; | |
128 | #clock-cells = <0>; | |
129 | clock-frequency = <0>; | |
130 | clock-output-names = "ipp_di1"; | |
131 | }; | |
132 | }; | |
133 | ||
134 | soc { | |
135 | #address-cells = <1>; | |
136 | #size-cells = <1>; | |
137 | compatible = "simple-bus"; | |
b923ff6a | 138 | interrupt-parent = <&gpc>; |
b1d17f68 SG |
139 | ranges; |
140 | ||
141 | pmu { | |
142 | compatible = "arm,cortex-a9-pmu"; | |
143 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
144 | }; | |
145 | ||
146 | ocram: sram@00900000 { | |
147 | compatible = "mmio-sram"; | |
148 | reg = <0x00900000 0x20000>; | |
149 | clocks = <&clks IMX6SX_CLK_OCRAM>; | |
150 | }; | |
151 | ||
152 | L2: l2-cache@00a02000 { | |
153 | compatible = "arm,pl310-cache"; | |
154 | reg = <0x00a02000 0x1000>; | |
155 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
156 | cache-unified; | |
157 | cache-level = <2>; | |
158 | arm,tag-latency = <4 2 3>; | |
159 | arm,data-latency = <4 2 3>; | |
160 | }; | |
161 | ||
162 | dma_apbh: dma-apbh@01804000 { | |
163 | compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; | |
164 | reg = <0x01804000 0x2000>; | |
165 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
166 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
167 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
168 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
169 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; | |
170 | #dma-cells = <1>; | |
171 | dma-channels = <4>; | |
172 | clocks = <&clks IMX6SX_CLK_APBH_DMA>; | |
173 | }; | |
174 | ||
175 | gpmi: gpmi-nand@01806000{ | |
176 | compatible = "fsl,imx6sx-gpmi-nand"; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <1>; | |
179 | reg = <0x01806000 0x2000>, <0x01808000 0x4000>; | |
180 | reg-names = "gpmi-nand", "bch"; | |
181 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
182 | interrupt-names = "bch"; | |
183 | clocks = <&clks IMX6SX_CLK_GPMI_IO>, | |
184 | <&clks IMX6SX_CLK_GPMI_APB>, | |
185 | <&clks IMX6SX_CLK_GPMI_BCH>, | |
186 | <&clks IMX6SX_CLK_GPMI_BCH_APB>, | |
187 | <&clks IMX6SX_CLK_PER1_BCH>; | |
188 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
189 | "gpmi_bch_apb", "per1_bch"; | |
190 | dmas = <&dma_apbh 0>; | |
191 | dma-names = "rx-tx"; | |
192 | status = "disabled"; | |
193 | }; | |
194 | ||
195 | aips1: aips-bus@02000000 { | |
196 | compatible = "fsl,aips-bus", "simple-bus"; | |
197 | #address-cells = <1>; | |
198 | #size-cells = <1>; | |
199 | reg = <0x02000000 0x100000>; | |
200 | ranges; | |
201 | ||
202 | spba-bus@02000000 { | |
203 | compatible = "fsl,spba-bus", "simple-bus"; | |
204 | #address-cells = <1>; | |
205 | #size-cells = <1>; | |
206 | reg = <0x02000000 0x40000>; | |
207 | ranges; | |
208 | ||
209 | spdif: spdif@02004000 { | |
210 | compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; | |
211 | reg = <0x02004000 0x4000>; | |
212 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
213 | dmas = <&sdma 14 18 0>, | |
214 | <&sdma 15 18 0>; | |
215 | dma-names = "rx", "tx"; | |
833f2cbf | 216 | clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, |
b1d17f68 SG |
217 | <&clks IMX6SX_CLK_OSC>, |
218 | <&clks IMX6SX_CLK_SPDIF>, | |
219 | <&clks 0>, <&clks 0>, <&clks 0>, | |
220 | <&clks IMX6SX_CLK_IPG>, | |
221 | <&clks 0>, <&clks 0>, | |
222 | <&clks IMX6SX_CLK_SPBA>; | |
223 | clock-names = "core", "rxtx0", | |
224 | "rxtx1", "rxtx2", | |
225 | "rxtx3", "rxtx4", | |
226 | "rxtx5", "rxtx6", | |
09d3059a | 227 | "rxtx7", "spba"; |
b1d17f68 SG |
228 | status = "disabled"; |
229 | }; | |
230 | ||
231 | ecspi1: ecspi@02008000 { | |
232 | #address-cells = <1>; | |
233 | #size-cells = <0>; | |
234 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
235 | reg = <0x02008000 0x4000>; | |
236 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
237 | clocks = <&clks IMX6SX_CLK_ECSPI1>, | |
238 | <&clks IMX6SX_CLK_ECSPI1>; | |
239 | clock-names = "ipg", "per"; | |
240 | status = "disabled"; | |
241 | }; | |
242 | ||
243 | ecspi2: ecspi@0200c000 { | |
244 | #address-cells = <1>; | |
245 | #size-cells = <0>; | |
246 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
247 | reg = <0x0200c000 0x4000>; | |
248 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
249 | clocks = <&clks IMX6SX_CLK_ECSPI2>, | |
250 | <&clks IMX6SX_CLK_ECSPI2>; | |
251 | clock-names = "ipg", "per"; | |
252 | status = "disabled"; | |
253 | }; | |
254 | ||
255 | ecspi3: ecspi@02010000 { | |
256 | #address-cells = <1>; | |
257 | #size-cells = <0>; | |
258 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
259 | reg = <0x02010000 0x4000>; | |
260 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
261 | clocks = <&clks IMX6SX_CLK_ECSPI3>, | |
262 | <&clks IMX6SX_CLK_ECSPI3>; | |
263 | clock-names = "ipg", "per"; | |
264 | status = "disabled"; | |
265 | }; | |
266 | ||
267 | ecspi4: ecspi@02014000 { | |
268 | #address-cells = <1>; | |
269 | #size-cells = <0>; | |
270 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
271 | reg = <0x02014000 0x4000>; | |
272 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
273 | clocks = <&clks IMX6SX_CLK_ECSPI4>, | |
274 | <&clks IMX6SX_CLK_ECSPI4>; | |
275 | clock-names = "ipg", "per"; | |
276 | status = "disabled"; | |
277 | }; | |
278 | ||
279 | uart1: serial@02020000 { | |
280 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
281 | reg = <0x02020000 0x4000>; | |
282 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
283 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
284 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
285 | clock-names = "ipg", "per"; | |
286 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; | |
287 | dma-names = "rx", "tx"; | |
288 | status = "disabled"; | |
289 | }; | |
290 | ||
291 | esai: esai@02024000 { | |
292 | reg = <0x02024000 0x4000>; | |
293 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
294 | clocks = <&clks IMX6SX_CLK_ESAI_IPG>, | |
295 | <&clks IMX6SX_CLK_ESAI_MEM>, | |
296 | <&clks IMX6SX_CLK_ESAI_EXTAL>, | |
297 | <&clks IMX6SX_CLK_ESAI_IPG>, | |
298 | <&clks IMX6SX_CLK_SPBA>; | |
299 | clock-names = "core", "mem", "extal", | |
09d3059a | 300 | "fsys", "spba"; |
b1d17f68 SG |
301 | status = "disabled"; |
302 | }; | |
303 | ||
304 | ssi1: ssi@02028000 { | |
6ff7f51e | 305 | #sound-dai-cells = <0>; |
4c03527e | 306 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
b1d17f68 SG |
307 | reg = <0x02028000 0x4000>; |
308 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
309 | clocks = <&clks IMX6SX_CLK_SSI1_IPG>, | |
310 | <&clks IMX6SX_CLK_SSI1>; | |
311 | clock-names = "ipg", "baud"; | |
312 | dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; | |
313 | dma-names = "rx", "tx"; | |
3a462a62 | 314 | fsl,fifo-depth = <15>; |
b1d17f68 SG |
315 | status = "disabled"; |
316 | }; | |
317 | ||
318 | ssi2: ssi@0202c000 { | |
6ff7f51e | 319 | #sound-dai-cells = <0>; |
4c03527e | 320 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
b1d17f68 SG |
321 | reg = <0x0202c000 0x4000>; |
322 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
323 | clocks = <&clks IMX6SX_CLK_SSI2_IPG>, | |
324 | <&clks IMX6SX_CLK_SSI2>; | |
325 | clock-names = "ipg", "baud"; | |
326 | dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; | |
327 | dma-names = "rx", "tx"; | |
3a462a62 | 328 | fsl,fifo-depth = <15>; |
b1d17f68 SG |
329 | status = "disabled"; |
330 | }; | |
331 | ||
332 | ssi3: ssi@02030000 { | |
6ff7f51e | 333 | #sound-dai-cells = <0>; |
4c03527e | 334 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
b1d17f68 SG |
335 | reg = <0x02030000 0x4000>; |
336 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
337 | clocks = <&clks IMX6SX_CLK_SSI3_IPG>, | |
338 | <&clks IMX6SX_CLK_SSI3>; | |
339 | clock-names = "ipg", "baud"; | |
340 | dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; | |
341 | dma-names = "rx", "tx"; | |
3a462a62 | 342 | fsl,fifo-depth = <15>; |
b1d17f68 SG |
343 | status = "disabled"; |
344 | }; | |
345 | ||
346 | asrc: asrc@02034000 { | |
347 | reg = <0x02034000 0x4000>; | |
348 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; | |
349 | clocks = <&clks IMX6SX_CLK_ASRC_MEM>, | |
350 | <&clks IMX6SX_CLK_ASRC_IPG>, | |
351 | <&clks IMX6SX_CLK_SPDIF>, | |
352 | <&clks IMX6SX_CLK_SPBA>; | |
09d3059a | 353 | clock-names = "mem", "ipg", "asrck", "spba"; |
b1d17f68 SG |
354 | dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, |
355 | <&sdma 19 20 1>, <&sdma 20 20 1>, | |
356 | <&sdma 21 20 1>, <&sdma 22 20 1>; | |
357 | dma-names = "rxa", "rxb", "rxc", | |
358 | "txa", "txb", "txc"; | |
359 | status = "okay"; | |
360 | }; | |
361 | }; | |
362 | ||
363 | pwm1: pwm@02080000 { | |
364 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
365 | reg = <0x02080000 0x4000>; | |
366 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
367 | clocks = <&clks IMX6SX_CLK_PWM1>, | |
368 | <&clks IMX6SX_CLK_PWM1>; | |
369 | clock-names = "ipg", "per"; | |
370 | #pwm-cells = <2>; | |
371 | }; | |
372 | ||
373 | pwm2: pwm@02084000 { | |
374 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
375 | reg = <0x02084000 0x4000>; | |
376 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
377 | clocks = <&clks IMX6SX_CLK_PWM2>, | |
378 | <&clks IMX6SX_CLK_PWM2>; | |
379 | clock-names = "ipg", "per"; | |
380 | #pwm-cells = <2>; | |
381 | }; | |
382 | ||
383 | pwm3: pwm@02088000 { | |
384 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
385 | reg = <0x02088000 0x4000>; | |
386 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
387 | clocks = <&clks IMX6SX_CLK_PWM3>, | |
388 | <&clks IMX6SX_CLK_PWM3>; | |
389 | clock-names = "ipg", "per"; | |
390 | #pwm-cells = <2>; | |
391 | }; | |
392 | ||
393 | pwm4: pwm@0208c000 { | |
394 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
395 | reg = <0x0208c000 0x4000>; | |
396 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
397 | clocks = <&clks IMX6SX_CLK_PWM4>, | |
398 | <&clks IMX6SX_CLK_PWM4>; | |
399 | clock-names = "ipg", "per"; | |
400 | #pwm-cells = <2>; | |
401 | }; | |
402 | ||
403 | flexcan1: can@02090000 { | |
404 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; | |
405 | reg = <0x02090000 0x4000>; | |
406 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
407 | clocks = <&clks IMX6SX_CLK_CAN1_IPG>, | |
408 | <&clks IMX6SX_CLK_CAN1_SERIAL>; | |
409 | clock-names = "ipg", "per"; | |
410 | status = "disabled"; | |
411 | }; | |
412 | ||
413 | flexcan2: can@02094000 { | |
414 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; | |
415 | reg = <0x02094000 0x4000>; | |
416 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
417 | clocks = <&clks IMX6SX_CLK_CAN2_IPG>, | |
418 | <&clks IMX6SX_CLK_CAN2_SERIAL>; | |
419 | clock-names = "ipg", "per"; | |
420 | status = "disabled"; | |
421 | }; | |
422 | ||
423 | gpt: gpt@02098000 { | |
424 | compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; | |
425 | reg = <0x02098000 0x4000>; | |
426 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
427 | clocks = <&clks IMX6SX_CLK_GPT_BUS>, | |
2b2244a3 | 428 | <&clks IMX6SX_CLK_GPT_3M>; |
b1d17f68 SG |
429 | clock-names = "ipg", "per"; |
430 | }; | |
431 | ||
432 | gpio1: gpio@0209c000 { | |
433 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
434 | reg = <0x0209c000 0x4000>; | |
435 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
436 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
437 | gpio-controller; | |
438 | #gpio-cells = <2>; | |
439 | interrupt-controller; | |
440 | #interrupt-cells = <2>; | |
441 | }; | |
442 | ||
443 | gpio2: gpio@020a0000 { | |
444 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
445 | reg = <0x020a0000 0x4000>; | |
446 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
447 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
448 | gpio-controller; | |
449 | #gpio-cells = <2>; | |
450 | interrupt-controller; | |
451 | #interrupt-cells = <2>; | |
452 | }; | |
453 | ||
454 | gpio3: gpio@020a4000 { | |
455 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
456 | reg = <0x020a4000 0x4000>; | |
457 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
458 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
459 | gpio-controller; | |
460 | #gpio-cells = <2>; | |
461 | interrupt-controller; | |
462 | #interrupt-cells = <2>; | |
463 | }; | |
464 | ||
465 | gpio4: gpio@020a8000 { | |
466 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
467 | reg = <0x020a8000 0x4000>; | |
468 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
469 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
470 | gpio-controller; | |
471 | #gpio-cells = <2>; | |
472 | interrupt-controller; | |
473 | #interrupt-cells = <2>; | |
474 | }; | |
475 | ||
476 | gpio5: gpio@020ac000 { | |
477 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
478 | reg = <0x020ac000 0x4000>; | |
479 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
480 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
481 | gpio-controller; | |
482 | #gpio-cells = <2>; | |
483 | interrupt-controller; | |
484 | #interrupt-cells = <2>; | |
485 | }; | |
486 | ||
487 | gpio6: gpio@020b0000 { | |
488 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
489 | reg = <0x020b0000 0x4000>; | |
490 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
491 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
492 | gpio-controller; | |
493 | #gpio-cells = <2>; | |
494 | interrupt-controller; | |
495 | #interrupt-cells = <2>; | |
496 | }; | |
497 | ||
498 | gpio7: gpio@020b4000 { | |
499 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
500 | reg = <0x020b4000 0x4000>; | |
501 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, | |
502 | <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
503 | gpio-controller; | |
504 | #gpio-cells = <2>; | |
505 | interrupt-controller; | |
506 | #interrupt-cells = <2>; | |
507 | }; | |
508 | ||
509 | kpp: kpp@020b8000 { | |
510 | compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; | |
511 | reg = <0x020b8000 0x4000>; | |
512 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
513 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
514 | status = "disabled"; | |
515 | }; | |
516 | ||
517 | wdog1: wdog@020bc000 { | |
518 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; | |
519 | reg = <0x020bc000 0x4000>; | |
520 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
521 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
522 | }; | |
523 | ||
524 | wdog2: wdog@020c0000 { | |
525 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; | |
526 | reg = <0x020c0000 0x4000>; | |
527 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
528 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
529 | status = "disabled"; | |
530 | }; | |
531 | ||
532 | clks: ccm@020c4000 { | |
533 | compatible = "fsl,imx6sx-ccm"; | |
534 | reg = <0x020c4000 0x4000>; | |
535 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
536 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
537 | #clock-cells = <1>; | |
538 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; | |
539 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; | |
540 | }; | |
541 | ||
542 | anatop: anatop@020c8000 { | |
543 | compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", | |
544 | "syscon", "simple-bus"; | |
545 | reg = <0x020c8000 0x1000>; | |
546 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
547 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
548 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
549 | ||
298701ec | 550 | regulator-1p1 { |
b1d17f68 SG |
551 | compatible = "fsl,anatop-regulator"; |
552 | regulator-name = "vdd1p1"; | |
553 | regulator-min-microvolt = <800000>; | |
554 | regulator-max-microvolt = <1375000>; | |
555 | regulator-always-on; | |
556 | anatop-reg-offset = <0x110>; | |
557 | anatop-vol-bit-shift = <8>; | |
558 | anatop-vol-bit-width = <5>; | |
559 | anatop-min-bit-val = <4>; | |
560 | anatop-min-voltage = <800000>; | |
561 | anatop-max-voltage = <1375000>; | |
562 | }; | |
563 | ||
298701ec | 564 | regulator-3p0 { |
b1d17f68 SG |
565 | compatible = "fsl,anatop-regulator"; |
566 | regulator-name = "vdd3p0"; | |
567 | regulator-min-microvolt = <2800000>; | |
568 | regulator-max-microvolt = <3150000>; | |
569 | regulator-always-on; | |
570 | anatop-reg-offset = <0x120>; | |
571 | anatop-vol-bit-shift = <8>; | |
572 | anatop-vol-bit-width = <5>; | |
573 | anatop-min-bit-val = <0>; | |
574 | anatop-min-voltage = <2625000>; | |
575 | anatop-max-voltage = <3400000>; | |
576 | }; | |
577 | ||
298701ec | 578 | regulator-2p5 { |
b1d17f68 SG |
579 | compatible = "fsl,anatop-regulator"; |
580 | regulator-name = "vdd2p5"; | |
581 | regulator-min-microvolt = <2100000>; | |
582 | regulator-max-microvolt = <2875000>; | |
583 | regulator-always-on; | |
584 | anatop-reg-offset = <0x130>; | |
585 | anatop-vol-bit-shift = <8>; | |
586 | anatop-vol-bit-width = <5>; | |
587 | anatop-min-bit-val = <0>; | |
588 | anatop-min-voltage = <2100000>; | |
589 | anatop-max-voltage = <2875000>; | |
590 | }; | |
591 | ||
298701ec | 592 | reg_arm: regulator-vddcore { |
b1d17f68 | 593 | compatible = "fsl,anatop-regulator"; |
f78a5975 | 594 | regulator-name = "vddarm"; |
b1d17f68 SG |
595 | regulator-min-microvolt = <725000>; |
596 | regulator-max-microvolt = <1450000>; | |
597 | regulator-always-on; | |
598 | anatop-reg-offset = <0x140>; | |
599 | anatop-vol-bit-shift = <0>; | |
600 | anatop-vol-bit-width = <5>; | |
601 | anatop-delay-reg-offset = <0x170>; | |
602 | anatop-delay-bit-shift = <24>; | |
603 | anatop-delay-bit-width = <2>; | |
604 | anatop-min-bit-val = <1>; | |
605 | anatop-min-voltage = <725000>; | |
606 | anatop-max-voltage = <1450000>; | |
607 | }; | |
608 | ||
298701ec | 609 | reg_pcie: regulator-vddpcie { |
b1d17f68 SG |
610 | compatible = "fsl,anatop-regulator"; |
611 | regulator-name = "vddpcie"; | |
612 | regulator-min-microvolt = <725000>; | |
613 | regulator-max-microvolt = <1450000>; | |
614 | anatop-reg-offset = <0x140>; | |
615 | anatop-vol-bit-shift = <9>; | |
616 | anatop-vol-bit-width = <5>; | |
617 | anatop-delay-reg-offset = <0x170>; | |
618 | anatop-delay-bit-shift = <26>; | |
619 | anatop-delay-bit-width = <2>; | |
620 | anatop-min-bit-val = <1>; | |
621 | anatop-min-voltage = <725000>; | |
622 | anatop-max-voltage = <1450000>; | |
623 | }; | |
624 | ||
298701ec | 625 | reg_soc: regulator-vddsoc { |
b1d17f68 SG |
626 | compatible = "fsl,anatop-regulator"; |
627 | regulator-name = "vddsoc"; | |
628 | regulator-min-microvolt = <725000>; | |
629 | regulator-max-microvolt = <1450000>; | |
630 | regulator-always-on; | |
631 | anatop-reg-offset = <0x140>; | |
632 | anatop-vol-bit-shift = <18>; | |
633 | anatop-vol-bit-width = <5>; | |
634 | anatop-delay-reg-offset = <0x170>; | |
635 | anatop-delay-bit-shift = <28>; | |
636 | anatop-delay-bit-width = <2>; | |
637 | anatop-min-bit-val = <1>; | |
638 | anatop-min-voltage = <725000>; | |
639 | anatop-max-voltage = <1450000>; | |
640 | }; | |
641 | }; | |
642 | ||
643 | tempmon: tempmon { | |
644 | compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; | |
645 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
646 | fsl,tempmon = <&anatop>; | |
647 | fsl,tempmon-data = <&ocotp>; | |
648 | clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; | |
649 | }; | |
650 | ||
651 | usbphy1: usbphy@020c9000 { | |
652 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; | |
653 | reg = <0x020c9000 0x1000>; | |
654 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
655 | clocks = <&clks IMX6SX_CLK_USBPHY1>; | |
656 | fsl,anatop = <&anatop>; | |
657 | }; | |
658 | ||
659 | usbphy2: usbphy@020ca000 { | |
660 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; | |
661 | reg = <0x020ca000 0x1000>; | |
662 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
663 | clocks = <&clks IMX6SX_CLK_USBPHY2>; | |
664 | fsl,anatop = <&anatop>; | |
665 | }; | |
666 | ||
667 | snvs: snvs@020cc000 { | |
95d739b5 FL |
668 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; |
669 | reg = <0x020cc000 0x4000>; | |
b1d17f68 | 670 | |
95d739b5 | 671 | snvs_rtc: snvs-rtc-lp { |
b1d17f68 | 672 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
95d739b5 FL |
673 | regmap = <&snvs>; |
674 | offset = <0x34>; | |
b1d17f68 SG |
675 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
676 | }; | |
422b0676 | 677 | |
95d739b5 FL |
678 | snvs_poweroff: snvs-poweroff { |
679 | compatible = "syscon-poweroff"; | |
680 | regmap = <&snvs>; | |
681 | offset = <0x38>; | |
682 | mask = <0x60>; | |
422b0676 RG |
683 | status = "disabled"; |
684 | }; | |
93db055d FL |
685 | |
686 | snvs_pwrkey: snvs-powerkey { | |
687 | compatible = "fsl,sec-v4.0-pwrkey"; | |
688 | regmap = <&snvs>; | |
689 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
690 | linux,keycode = <KEY_POWER>; | |
461aa6d7 | 691 | wakeup-source; |
93db055d | 692 | }; |
b1d17f68 SG |
693 | }; |
694 | ||
695 | epit1: epit@020d0000 { | |
696 | reg = <0x020d0000 0x4000>; | |
697 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
698 | }; | |
699 | ||
700 | epit2: epit@020d4000 { | |
701 | reg = <0x020d4000 0x4000>; | |
702 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
703 | }; | |
704 | ||
705 | src: src@020d8000 { | |
706 | compatible = "fsl,imx6sx-src", "fsl,imx51-src"; | |
707 | reg = <0x020d8000 0x4000>; | |
708 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
709 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
710 | #reset-cells = <1>; | |
711 | }; | |
712 | ||
713 | gpc: gpc@020dc000 { | |
714 | compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; | |
715 | reg = <0x020dc000 0x4000>; | |
b923ff6a MZ |
716 | interrupt-controller; |
717 | #interrupt-cells = <3>; | |
b1d17f68 | 718 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
b923ff6a | 719 | interrupt-parent = <&intc>; |
b1d17f68 SG |
720 | }; |
721 | ||
722 | iomuxc: iomuxc@020e0000 { | |
723 | compatible = "fsl,imx6sx-iomuxc"; | |
724 | reg = <0x020e0000 0x4000>; | |
725 | }; | |
726 | ||
727 | gpr: iomuxc-gpr@020e4000 { | |
77e0d1cc AH |
728 | compatible = "fsl,imx6sx-iomuxc-gpr", |
729 | "fsl,imx6q-iomuxc-gpr", "syscon"; | |
b1d17f68 SG |
730 | reg = <0x020e4000 0x4000>; |
731 | }; | |
732 | ||
733 | sdma: sdma@020ec000 { | |
811e7685 | 734 | compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; |
b1d17f68 SG |
735 | reg = <0x020ec000 0x4000>; |
736 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
737 | clocks = <&clks IMX6SX_CLK_SDMA>, | |
738 | <&clks IMX6SX_CLK_SDMA>; | |
739 | clock-names = "ipg", "ahb"; | |
740 | #dma-cells = <3>; | |
aeb88538 FE |
741 | /* imx6sx reuses imx6q sdma firmware */ |
742 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; | |
b1d17f68 SG |
743 | }; |
744 | }; | |
745 | ||
746 | aips2: aips-bus@02100000 { | |
747 | compatible = "fsl,aips-bus", "simple-bus"; | |
748 | #address-cells = <1>; | |
749 | #size-cells = <1>; | |
750 | reg = <0x02100000 0x100000>; | |
751 | ranges; | |
752 | ||
b15e9ea5 VM |
753 | crypto: caam@2100000 { |
754 | compatible = "fsl,sec-v4.0"; | |
755 | fsl,sec-era = <4>; | |
756 | #address-cells = <1>; | |
757 | #size-cells = <1>; | |
758 | reg = <0x2100000 0x10000>; | |
759 | ranges = <0 0x2100000 0x10000>; | |
760 | interrupt-parent = <&intc>; | |
761 | clocks = <&clks IMX6SX_CLK_CAAM_MEM>, | |
762 | <&clks IMX6SX_CLK_CAAM_ACLK>, | |
763 | <&clks IMX6SX_CLK_CAAM_IPG>, | |
764 | <&clks IMX6SX_CLK_EIM_SLOW>; | |
765 | clock-names = "mem", "aclk", "ipg", "emi_slow"; | |
766 | ||
767 | sec_jr0: jr0@1000 { | |
768 | compatible = "fsl,sec-v4.0-job-ring"; | |
769 | reg = <0x1000 0x1000>; | |
770 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
771 | }; | |
772 | ||
773 | sec_jr1: jr1@2000 { | |
774 | compatible = "fsl,sec-v4.0-job-ring"; | |
775 | reg = <0x2000 0x1000>; | |
776 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
777 | }; | |
778 | }; | |
779 | ||
b1d17f68 SG |
780 | usbotg1: usb@02184000 { |
781 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; | |
782 | reg = <0x02184000 0x200>; | |
783 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
784 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
785 | fsl,usbphy = <&usbphy1>; | |
786 | fsl,usbmisc = <&usbmisc 0>; | |
787 | fsl,anatop = <&anatop>; | |
9493bf54 | 788 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
789 | tx-burst-size-dword = <0x10>; |
790 | rx-burst-size-dword = <0x10>; | |
b1d17f68 SG |
791 | status = "disabled"; |
792 | }; | |
793 | ||
794 | usbotg2: usb@02184200 { | |
795 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; | |
796 | reg = <0x02184200 0x200>; | |
797 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
798 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
799 | fsl,usbphy = <&usbphy2>; | |
800 | fsl,usbmisc = <&usbmisc 1>; | |
9493bf54 | 801 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
802 | tx-burst-size-dword = <0x10>; |
803 | rx-burst-size-dword = <0x10>; | |
b1d17f68 SG |
804 | status = "disabled"; |
805 | }; | |
806 | ||
807 | usbh: usb@02184400 { | |
808 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; | |
809 | reg = <0x02184400 0x200>; | |
810 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
811 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
812 | fsl,usbmisc = <&usbmisc 2>; | |
813 | phy_type = "hsic"; | |
814 | fsl,anatop = <&anatop>; | |
3ec481ed | 815 | dr_mode = "host"; |
9493bf54 | 816 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
817 | tx-burst-size-dword = <0x10>; |
818 | rx-burst-size-dword = <0x10>; | |
b1d17f68 SG |
819 | status = "disabled"; |
820 | }; | |
821 | ||
822 | usbmisc: usbmisc@02184800 { | |
823 | #index-cells = <1>; | |
b29f4fa1 | 824 | compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; |
b1d17f68 SG |
825 | reg = <0x02184800 0x200>; |
826 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
827 | }; | |
828 | ||
829 | fec1: ethernet@02188000 { | |
830 | compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; | |
831 | reg = <0x02188000 0x4000>; | |
832 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
833 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
834 | clocks = <&clks IMX6SX_CLK_ENET>, | |
835 | <&clks IMX6SX_CLK_ENET_AHB>, | |
836 | <&clks IMX6SX_CLK_ENET_PTP>, | |
837 | <&clks IMX6SX_CLK_ENET_REF>, | |
838 | <&clks IMX6SX_CLK_ENET_PTP>; | |
839 | clock-names = "ipg", "ahb", "ptp", | |
840 | "enet_clk_ref", "enet_out"; | |
0afdfe95 FL |
841 | fsl,num-tx-queues=<3>; |
842 | fsl,num-rx-queues=<3>; | |
b1d17f68 SG |
843 | status = "disabled"; |
844 | }; | |
845 | ||
846 | mlb: mlb@0218c000 { | |
847 | reg = <0x0218c000 0x4000>; | |
848 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
849 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
850 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
851 | clocks = <&clks IMX6SX_CLK_MLB>; | |
852 | status = "disabled"; | |
853 | }; | |
854 | ||
855 | usdhc1: usdhc@02190000 { | |
856 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
857 | reg = <0x02190000 0x4000>; | |
858 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
859 | clocks = <&clks IMX6SX_CLK_USDHC1>, | |
860 | <&clks IMX6SX_CLK_USDHC1>, | |
861 | <&clks IMX6SX_CLK_USDHC1>; | |
862 | clock-names = "ipg", "ahb", "per"; | |
863 | bus-width = <4>; | |
864 | status = "disabled"; | |
865 | }; | |
866 | ||
867 | usdhc2: usdhc@02194000 { | |
868 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
869 | reg = <0x02194000 0x4000>; | |
870 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
871 | clocks = <&clks IMX6SX_CLK_USDHC2>, | |
872 | <&clks IMX6SX_CLK_USDHC2>, | |
873 | <&clks IMX6SX_CLK_USDHC2>; | |
874 | clock-names = "ipg", "ahb", "per"; | |
875 | bus-width = <4>; | |
876 | status = "disabled"; | |
877 | }; | |
878 | ||
879 | usdhc3: usdhc@02198000 { | |
880 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
881 | reg = <0x02198000 0x4000>; | |
882 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
883 | clocks = <&clks IMX6SX_CLK_USDHC3>, | |
884 | <&clks IMX6SX_CLK_USDHC3>, | |
885 | <&clks IMX6SX_CLK_USDHC3>; | |
886 | clock-names = "ipg", "ahb", "per"; | |
887 | bus-width = <4>; | |
888 | status = "disabled"; | |
889 | }; | |
890 | ||
891 | usdhc4: usdhc@0219c000 { | |
892 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
893 | reg = <0x0219c000 0x4000>; | |
894 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
895 | clocks = <&clks IMX6SX_CLK_USDHC4>, | |
896 | <&clks IMX6SX_CLK_USDHC4>, | |
897 | <&clks IMX6SX_CLK_USDHC4>; | |
898 | clock-names = "ipg", "ahb", "per"; | |
899 | bus-width = <4>; | |
900 | status = "disabled"; | |
901 | }; | |
902 | ||
903 | i2c1: i2c@021a0000 { | |
904 | #address-cells = <1>; | |
905 | #size-cells = <0>; | |
906 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
907 | reg = <0x021a0000 0x4000>; | |
908 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
909 | clocks = <&clks IMX6SX_CLK_I2C1>; | |
910 | status = "disabled"; | |
911 | }; | |
912 | ||
913 | i2c2: i2c@021a4000 { | |
914 | #address-cells = <1>; | |
915 | #size-cells = <0>; | |
916 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
917 | reg = <0x021a4000 0x4000>; | |
918 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
919 | clocks = <&clks IMX6SX_CLK_I2C2>; | |
920 | status = "disabled"; | |
921 | }; | |
922 | ||
923 | i2c3: i2c@021a8000 { | |
924 | #address-cells = <1>; | |
925 | #size-cells = <0>; | |
926 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
927 | reg = <0x021a8000 0x4000>; | |
928 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
929 | clocks = <&clks IMX6SX_CLK_I2C3>; | |
930 | status = "disabled"; | |
931 | }; | |
932 | ||
933 | mmdc: mmdc@021b0000 { | |
934 | compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; | |
935 | reg = <0x021b0000 0x4000>; | |
936 | }; | |
937 | ||
938 | fec2: ethernet@021b4000 { | |
9863aba5 | 939 | compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; |
b1d17f68 SG |
940 | reg = <0x021b4000 0x4000>; |
941 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
942 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
943 | clocks = <&clks IMX6SX_CLK_ENET>, | |
944 | <&clks IMX6SX_CLK_ENET_AHB>, | |
945 | <&clks IMX6SX_CLK_ENET_PTP>, | |
946 | <&clks IMX6SX_CLK_ENET2_REF_125M>, | |
947 | <&clks IMX6SX_CLK_ENET_PTP>; | |
948 | clock-names = "ipg", "ahb", "ptp", | |
949 | "enet_clk_ref", "enet_out"; | |
950 | status = "disabled"; | |
951 | }; | |
952 | ||
953 | weim: weim@021b8000 { | |
954 | compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; | |
955 | reg = <0x021b8000 0x4000>; | |
956 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
957 | clocks = <&clks IMX6SX_CLK_EIM_SLOW>; | |
958 | }; | |
959 | ||
960 | ocotp: ocotp@021bc000 { | |
961 | compatible = "fsl,imx6sx-ocotp", "syscon"; | |
962 | reg = <0x021bc000 0x4000>; | |
963 | clocks = <&clks IMX6SX_CLK_OCOTP>; | |
964 | }; | |
965 | ||
966 | sai1: sai@021d4000 { | |
967 | compatible = "fsl,imx6sx-sai"; | |
968 | reg = <0x021d4000 0x4000>; | |
969 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
970 | clocks = <&clks IMX6SX_CLK_SAI1_IPG>, | |
971 | <&clks IMX6SX_CLK_SAI1>, | |
972 | <&clks 0>, <&clks 0>; | |
973 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
974 | dma-names = "rx", "tx"; | |
78f31b0b | 975 | dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; |
b1d17f68 SG |
976 | status = "disabled"; |
977 | }; | |
978 | ||
979 | audmux: audmux@021d8000 { | |
980 | compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; | |
981 | reg = <0x021d8000 0x4000>; | |
982 | status = "disabled"; | |
983 | }; | |
984 | ||
985 | sai2: sai@021dc000 { | |
986 | compatible = "fsl,imx6sx-sai"; | |
987 | reg = <0x021dc000 0x4000>; | |
988 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
989 | clocks = <&clks IMX6SX_CLK_SAI2_IPG>, | |
990 | <&clks IMX6SX_CLK_SAI2>, | |
991 | <&clks 0>, <&clks 0>; | |
992 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
993 | dma-names = "rx", "tx"; | |
78f31b0b | 994 | dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; |
b1d17f68 SG |
995 | status = "disabled"; |
996 | }; | |
997 | ||
998 | qspi1: qspi@021e0000 { | |
999 | #address-cells = <1>; | |
1000 | #size-cells = <0>; | |
1001 | compatible = "fsl,imx6sx-qspi"; | |
1002 | reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; | |
1003 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
1004 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
1005 | clocks = <&clks IMX6SX_CLK_QSPI1>, | |
1006 | <&clks IMX6SX_CLK_QSPI1>; | |
1007 | clock-names = "qspi_en", "qspi"; | |
1008 | status = "disabled"; | |
1009 | }; | |
1010 | ||
1011 | qspi2: qspi@021e4000 { | |
1012 | #address-cells = <1>; | |
1013 | #size-cells = <0>; | |
1014 | compatible = "fsl,imx6sx-qspi"; | |
1015 | reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; | |
1016 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
1017 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
1018 | clocks = <&clks IMX6SX_CLK_QSPI2>, | |
1019 | <&clks IMX6SX_CLK_QSPI2>; | |
1020 | clock-names = "qspi_en", "qspi"; | |
1021 | status = "disabled"; | |
1022 | }; | |
1023 | ||
1024 | uart2: serial@021e8000 { | |
1025 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
1026 | reg = <0x021e8000 0x4000>; | |
1027 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
1028 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
1029 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
1030 | clock-names = "ipg", "per"; | |
1031 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; | |
1032 | dma-names = "rx", "tx"; | |
1033 | status = "disabled"; | |
1034 | }; | |
1035 | ||
1036 | uart3: serial@021ec000 { | |
1037 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
1038 | reg = <0x021ec000 0x4000>; | |
1039 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
1040 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
1041 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
1042 | clock-names = "ipg", "per"; | |
1043 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; | |
1044 | dma-names = "rx", "tx"; | |
1045 | status = "disabled"; | |
1046 | }; | |
1047 | ||
1048 | uart4: serial@021f0000 { | |
1049 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
1050 | reg = <0x021f0000 0x4000>; | |
1051 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
1052 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
1053 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
1054 | clock-names = "ipg", "per"; | |
1055 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; | |
1056 | dma-names = "rx", "tx"; | |
1057 | status = "disabled"; | |
1058 | }; | |
1059 | ||
1060 | uart5: serial@021f4000 { | |
1061 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
1062 | reg = <0x021f4000 0x4000>; | |
1063 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
1064 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
1065 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
1066 | clock-names = "ipg", "per"; | |
1067 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; | |
1068 | dma-names = "rx", "tx"; | |
1069 | status = "disabled"; | |
1070 | }; | |
1071 | ||
1072 | i2c4: i2c@021f8000 { | |
1073 | #address-cells = <1>; | |
1074 | #size-cells = <0>; | |
1075 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
1076 | reg = <0x021f8000 0x4000>; | |
1077 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
1078 | clocks = <&clks IMX6SX_CLK_I2C4>; | |
1079 | status = "disabled"; | |
1080 | }; | |
1081 | }; | |
1082 | ||
1083 | aips3: aips-bus@02200000 { | |
1084 | compatible = "fsl,aips-bus", "simple-bus"; | |
1085 | #address-cells = <1>; | |
1086 | #size-cells = <1>; | |
1087 | reg = <0x02200000 0x100000>; | |
1088 | ranges; | |
1089 | ||
1090 | spba-bus@02200000 { | |
1091 | compatible = "fsl,spba-bus", "simple-bus"; | |
1092 | #address-cells = <1>; | |
1093 | #size-cells = <1>; | |
1094 | reg = <0x02240000 0x40000>; | |
1095 | ranges; | |
1096 | ||
1097 | csi1: csi@02214000 { | |
1098 | reg = <0x02214000 0x4000>; | |
1099 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
1100 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, | |
1101 | <&clks IMX6SX_CLK_CSI>, | |
1102 | <&clks IMX6SX_CLK_DCIC1>; | |
1103 | clock-names = "disp-axi", "csi_mclk", "dcic"; | |
1104 | status = "disabled"; | |
1105 | }; | |
1106 | ||
1107 | pxp: pxp@02218000 { | |
1108 | reg = <0x02218000 0x4000>; | |
1109 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
1110 | clocks = <&clks IMX6SX_CLK_PXP_AXI>, | |
1111 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1112 | clock-names = "pxp-axi", "disp-axi"; | |
1113 | status = "disabled"; | |
1114 | }; | |
1115 | ||
1116 | csi2: csi@0221c000 { | |
1117 | reg = <0x0221c000 0x4000>; | |
1118 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
1119 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, | |
1120 | <&clks IMX6SX_CLK_CSI>, | |
1121 | <&clks IMX6SX_CLK_DCIC2>; | |
1122 | clock-names = "disp-axi", "csi_mclk", "dcic"; | |
1123 | status = "disabled"; | |
1124 | }; | |
1125 | ||
1126 | lcdif1: lcdif@02220000 { | |
8c78c407 | 1127 | compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; |
b1d17f68 SG |
1128 | reg = <0x02220000 0x4000>; |
1129 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
1130 | clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, | |
1131 | <&clks IMX6SX_CLK_LCDIF_APB>, | |
1132 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1133 | clock-names = "pix", "axi", "disp_axi"; | |
1134 | status = "disabled"; | |
1135 | }; | |
1136 | ||
1137 | lcdif2: lcdif@02224000 { | |
8c78c407 | 1138 | compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; |
b1d17f68 SG |
1139 | reg = <0x02224000 0x4000>; |
1140 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
1141 | clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, | |
1142 | <&clks IMX6SX_CLK_LCDIF_APB>, | |
1143 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1144 | clock-names = "pix", "axi", "disp_axi"; | |
1145 | status = "disabled"; | |
1146 | }; | |
1147 | ||
1148 | vadc: vadc@02228000 { | |
1149 | reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; | |
1150 | reg-names = "vadc-vafe", "vadc-vdec"; | |
1151 | clocks = <&clks IMX6SX_CLK_VADC>, | |
1152 | <&clks IMX6SX_CLK_CSI>; | |
1153 | clock-names = "vadc", "csi"; | |
1154 | status = "disabled"; | |
1155 | }; | |
1156 | }; | |
1157 | ||
1158 | adc1: adc@02280000 { | |
1159 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; | |
1160 | reg = <0x02280000 0x4000>; | |
1161 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
1162 | clocks = <&clks IMX6SX_CLK_IPG>; | |
1163 | clock-names = "adc"; | |
eb45ff74 FE |
1164 | fsl,adck-max-frequency = <30000000>, <40000000>, |
1165 | <20000000>; | |
b1d17f68 SG |
1166 | status = "disabled"; |
1167 | }; | |
1168 | ||
1169 | adc2: adc@02284000 { | |
1170 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; | |
1171 | reg = <0x02284000 0x4000>; | |
1172 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1173 | clocks = <&clks IMX6SX_CLK_IPG>; | |
1174 | clock-names = "adc"; | |
eb45ff74 FE |
1175 | fsl,adck-max-frequency = <30000000>, <40000000>, |
1176 | <20000000>; | |
b1d17f68 SG |
1177 | status = "disabled"; |
1178 | }; | |
1179 | ||
1180 | wdog3: wdog@02288000 { | |
1181 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; | |
1182 | reg = <0x02288000 0x4000>; | |
1183 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
1184 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
1185 | status = "disabled"; | |
1186 | }; | |
1187 | ||
1188 | ecspi5: ecspi@0228c000 { | |
1189 | #address-cells = <1>; | |
1190 | #size-cells = <0>; | |
1191 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
1192 | reg = <0x0228c000 0x4000>; | |
1193 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
1194 | clocks = <&clks IMX6SX_CLK_ECSPI5>, | |
1195 | <&clks IMX6SX_CLK_ECSPI5>; | |
1196 | clock-names = "ipg", "per"; | |
1197 | status = "disabled"; | |
1198 | }; | |
1199 | ||
1200 | uart6: serial@022a0000 { | |
1201 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
1202 | reg = <0x022a0000 0x4000>; | |
1203 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
1204 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
1205 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
1206 | clock-names = "ipg", "per"; | |
1207 | dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; | |
1208 | dma-names = "rx", "tx"; | |
1209 | status = "disabled"; | |
1210 | }; | |
1211 | ||
1212 | pwm5: pwm@022a4000 { | |
1213 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1214 | reg = <0x022a4000 0x4000>; | |
1215 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
1216 | clocks = <&clks IMX6SX_CLK_PWM5>, | |
1217 | <&clks IMX6SX_CLK_PWM5>; | |
1218 | clock-names = "ipg", "per"; | |
1219 | #pwm-cells = <2>; | |
1220 | }; | |
1221 | ||
1222 | pwm6: pwm@022a8000 { | |
1223 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1224 | reg = <0x022a8000 0x4000>; | |
1225 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
1226 | clocks = <&clks IMX6SX_CLK_PWM6>, | |
1227 | <&clks IMX6SX_CLK_PWM6>; | |
1228 | clock-names = "ipg", "per"; | |
1229 | #pwm-cells = <2>; | |
1230 | }; | |
1231 | ||
1232 | pwm7: pwm@022ac000 { | |
1233 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1234 | reg = <0x022ac000 0x4000>; | |
1235 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
1236 | clocks = <&clks IMX6SX_CLK_PWM7>, | |
1237 | <&clks IMX6SX_CLK_PWM7>; | |
1238 | clock-names = "ipg", "per"; | |
1239 | #pwm-cells = <2>; | |
1240 | }; | |
1241 | ||
1242 | pwm8: pwm@0022b0000 { | |
1243 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1244 | reg = <0x0022b0000 0x4000>; | |
1245 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
1246 | clocks = <&clks IMX6SX_CLK_PWM8>, | |
1247 | <&clks IMX6SX_CLK_PWM8>; | |
1248 | clock-names = "ipg", "per"; | |
1249 | #pwm-cells = <2>; | |
1250 | }; | |
1251 | }; | |
1252 | ||
1253 | pcie: pcie@0x08000000 { | |
1254 | compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; | |
1255 | reg = <0x08ffc000 0x4000>; /* DBI */ | |
1256 | #address-cells = <3>; | |
1257 | #size-cells = <2>; | |
1258 | device_type = "pci"; | |
1259 | /* configuration space */ | |
1260 | ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 | |
1261 | /* downstream I/O */ | |
1262 | 0x81000000 0 0 0x08f80000 0 0x00010000 | |
1263 | /* non-prefetchable memory */ | |
1264 | 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; | |
1265 | num-lanes = <1>; | |
1266 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; | |
1267 | clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, | |
1268 | <&clks IMX6SX_CLK_PCIE_AXI>, | |
1269 | <&clks IMX6SX_CLK_LVDS1_OUT>, | |
1270 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1271 | clock-names = "pcie_ref_125m", "pcie_axi", | |
1272 | "lvds_gate", "display_axi"; | |
1273 | status = "disabled"; | |
1274 | }; | |
1275 | }; | |
1276 | }; |