[deliverable/linux.git] / arch / arm / boot / dts / imx7d-sdb.dts

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx7d.dtsi"

/ {
	model = "Freescale i.MX7 SabreSD Board";
	compatible = "fsl,imx7d-sdb", "fsl,imx7d";

	memory {
		reg = <0x80000000 0x80000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usb_otg1_vbus: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg2_vbus: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "usb_otg2_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_can2_3v3: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "can2-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
		};

		reg_vref_1v8: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "vref-1v8";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
	};
};

&adc1 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&adc2 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&cpu0 {
	arm-supply = <&sw1a_reg>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pfuze3000@08 {
		compatible = "fsl,pfuze3000";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1a {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			/* use sw1c_reg to align with pfuze100/pfuze200 */
			sw1c_reg: sw1b {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vldo1 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen2_reg: vldo2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vccsd {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen4_reg: v33 {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vldo3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vldo4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	codec: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		clock-names = "mclk";
		wlf,shared-lrclk;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
	enable-sdio-wakeup;
	keep-power-in-suspend;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	fsl,tuning-step = <2>;
	non-removable;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx7d-sdb {
		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
				MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x1
				MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x1
				MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x1
				MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x1
				MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x1
				MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x1
				MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x1
				MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x1
				MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x1
				MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x1
				MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x1
				MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x1
			>;
		};

		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14
				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x34  /* bt reg on */
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
				MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
				MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
				MX7D_PAD_I2C3_SCL__I2C3_SCL		0x4000007f
			>;
		};

		pinctrl_i2c4: i2c4grp {
			fsl,pins = <
				MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
				MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL		0x4000007f
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
			>;
		};

		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX	0x79
				MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX	0x79
				MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS	0x79
				MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS	0x79
			>;
		};

		pinctrl_uart6: uart6grp {
			fsl,pins = <
				MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX	0x79
				MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX	0x79
				MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS	0x79
				MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS	0x79
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX7D_PAD_SD1_CMD__SD1_CMD		0x59
				MX7D_PAD_SD1_CLK__SD1_CLK		0x19
				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX7D_PAD_SD2_CMD__SD2_CMD		0x59
				MX7D_PAD_SD2_CLK__SD2_CLK		0x19
				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
				MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x59 /* WL_REG_ON */
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
			fsl,pins = <
				MX7D_PAD_SD2_CMD__SD2_CMD		0x5a
				MX7D_PAD_SD2_CLK__SD2_CLK		0x1a
				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5a
				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5a
				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5a
				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5a
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
			fsl,pins = <
				MX7D_PAD_SD2_CMD__SD2_CMD		0x5b
				MX7D_PAD_SD2_CLK__SD2_CLK		0x1b
				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5b
				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5b
				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5b
				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5b
			>;
		};


		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX7D_PAD_SD3_CMD__SD3_CMD		0x59
				MX7D_PAD_SD3_CLK__SD3_CLK		0x19
				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x19
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
			fsl,pins = <
				MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
				MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1a
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
			fsl,pins = <
				MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
				MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1b
			>;
		};

	};
};
Commit	Line	Data
5db106bc FL	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor, Inc.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/dts-v1/;
	44
	45	#include <dt-bindings/input/input.h>
	46	#include "imx7d.dtsi"
	47
	48	/ {
	49	model = "Freescale i.MX7 SabreSD Board";
	50	compatible = "fsl,imx7d-sdb", "fsl,imx7d";
	51
	52	memory {
	53	reg = <0x80000000 0x80000000>;
	54	};
	55
	56	regulators {
	57	compatible = "simple-bus";
	58	#address-cells = <1>;
	59	#size-cells = <0>;
	60
	61	reg_usb_otg1_vbus: regulator@0 {
	62	compatible = "regulator-fixed";
	63	reg = <0>;
	64	regulator-name = "usb_otg1_vbus";
65	regulator-min-microvolt = <5000000>;
66	regulator-max-microvolt = <5000000>;
67	gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
68	enable-active-high;
69	};
70
71	reg_usb_otg2_vbus: regulator@1 {
72	compatible = "regulator-fixed";
73	reg = <1>;
74	regulator-name = "usb_otg2_vbus";
75	regulator-min-microvolt = <5000000>;
76	regulator-max-microvolt = <5000000>;
77	gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
78	enable-active-high;
79	};
80
81	reg_can2_3v3: regulator@2 {
82	compatible = "regulator-fixed";
83	reg = <2>;
84	regulator-name = "can2-3v3";
85	regulator-min-microvolt = <3300000>;
86	regulator-max-microvolt = <3300000>;
87	gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
88	};
89
90	reg_vref_1v8: regulator@3 {
91	compatible = "regulator-fixed";
92	reg = <3>;
93	regulator-name = "vref-1v8";
94	regulator-min-microvolt = <1800000>;
95	regulator-max-microvolt = <1800000>;
96	};
97	};
98	};
99
64b83432 HC	100	&adc1 {
	101	vref-supply = <&reg_vref_1v8>;
	102	status = "okay";
	103	};
	104
	105	&adc2 {
	106	vref-supply = <&reg_vref_1v8>;
	107	status = "okay";
	108	};
	109
5db106bc FL	110	&cpu0 {
	111	arm-supply = <&sw1a_reg>;
	112	};
	113
47bcc8c0 FD	114	&fec1 {
	115	pinctrl-names = "default";
	116	pinctrl-0 = <&pinctrl_enet1>;
	117	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
	118	<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	119	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	120	assigned-clock-rates = <0>, <100000000>;
	121	phy-mode = "rgmii";
	122	phy-handle = <&ethphy0>;
	123	fsl,magic-packet;
	124	status = "okay";
	125
	126	mdio {
	127	#address-cells = <1>;
	128	#size-cells = <0>;
	129
	130	ethphy0: ethernet-phy@0 {
	131	reg = <0>;
	132	};
	133
	134	ethphy1: ethernet-phy@1 {
	135	reg = <1>;
	136	};
	137	};
	138	};
	139
	140	&fec2 {
	141	pinctrl-names = "default";
	142	pinctrl-0 = <&pinctrl_enet2>;
	143	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
	144	<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
	145	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	146	assigned-clock-rates = <0>, <100000000>;
	147	phy-mode = "rgmii";
	148	phy-handle = <&ethphy1>;
	149	fsl,magic-packet;
	150	status = "okay";
	151	};
	152
5db106bc FL	153	&i2c1 {
	154	pinctrl-names = "default";
	155	pinctrl-0 = <&pinctrl_i2c1>;
	156	status = "okay";
	157
	158	pmic: pfuze3000@08 {
	159	compatible = "fsl,pfuze3000";
	160	reg = <0x08>;
	161
	162	regulators {
	163	sw1a_reg: sw1a {
	164	regulator-min-microvolt = <700000>;
	165	regulator-max-microvolt = <1475000>;
	166	regulator-boot-on;
	167	regulator-always-on;
	168	regulator-ramp-delay = <6250>;
	169	};
	170
	171	/* use sw1c_reg to align with pfuze100/pfuze200 */
	172	sw1c_reg: sw1b {
	173	regulator-min-microvolt = <700000>;
	174	regulator-max-microvolt = <1475000>;
	175	regulator-boot-on;
	176	regulator-always-on;
	177	regulator-ramp-delay = <6250>;
	178	};
	179
	180	sw2_reg: sw2 {
	181	regulator-min-microvolt = <1500000>;
	182	regulator-max-microvolt = <1850000>;
	183	regulator-boot-on;
	184	regulator-always-on;
	185	};
	186
	187	sw3a_reg: sw3 {
	188	regulator-min-microvolt = <900000>;
	189	regulator-max-microvolt = <1650000>;
	190	regulator-boot-on;
	191	regulator-always-on;
	192	};
	193
	194	swbst_reg: swbst {
	195	regulator-min-microvolt = <5000000>;
	196	regulator-max-microvolt = <5150000>;
	197	};
	198
	199	snvs_reg: vsnvs {
	200	regulator-min-microvolt = <1000000>;
	201	regulator-max-microvolt = <3000000>;
	202	regulator-boot-on;
	203	regulator-always-on;
	204	};
	205
	206	vref_reg: vrefddr {
	207	regulator-boot-on;
	208	regulator-always-on;
	209	};
	210
	211	vgen1_reg: vldo1 {
	212	regulator-min-microvolt = <1800000>;
	213	regulator-max-microvolt = <3300000>;
	214	regulator-always-on;
	215	};
	216
217	vgen2_reg: vldo2 {
218	regulator-min-microvolt = <800000>;
219	regulator-max-microvolt = <1550000>;
220	};
221
222	vgen3_reg: vccsd {
223	regulator-min-microvolt = <2850000>;
224	regulator-max-microvolt = <3300000>;
225	regulator-always-on;
226	};
227
228	vgen4_reg: v33 {
229	regulator-min-microvolt = <2850000>;
230	regulator-max-microvolt = <3300000>;
231	regulator-always-on;
232	};
233
234	vgen5_reg: vldo3 {
235	regulator-min-microvolt = <1800000>;
236	regulator-max-microvolt = <3300000>;
237	regulator-always-on;
238	};
239
240	vgen6_reg: vldo4 {
241	regulator-min-microvolt = <1800000>;
242	regulator-max-microvolt = <3300000>;
243	regulator-always-on;
244	};
245	};
246	};
247	};
248
249	&i2c2 {
250	pinctrl-names = "default";
251	pinctrl-0 = <&pinctrl_i2c2>;
252	status = "okay";
253	};
254
255	&i2c3 {
256	pinctrl-names = "default";
257	pinctrl-0 = <&pinctrl_i2c3>;
258	status = "okay";
259	};
260
261	&i2c4 {
262	pinctrl-names = "default";
263	pinctrl-0 = <&pinctrl_i2c4>;
264	status = "okay";
265
266	codec: wm8960@1a {
267	compatible = "wlf,wm8960";
268	reg = <0x1a>;
269	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
270	clock-names = "mclk";
271	wlf,shared-lrclk;
272	};
273	};
274
275	&uart1 {
276	pinctrl-names = "default";
277	pinctrl-0 = <&pinctrl_uart1>;
278	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
280	status = "okay";
281	};
282
a81fd34d FE	283	&usbotg1 {
	284	vbus-supply = <&reg_usb_otg1_vbus>;
	285	status = "okay";
	286	};
	287
	288	&usbotg2 {
	289	vbus-supply = <&reg_usb_otg2_vbus>;
	290	dr_mode = "host";
	291	status = "okay";
	292	};
	293
5db106bc FL	294	&usdhc1 {
	295	pinctrl-names = "default";
	296	pinctrl-0 = <&pinctrl_usdhc1>;
1cd55947 DA	297	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
1cd55947 DA	298	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
5db106bc FL	299	enable-sdio-wakeup;
	300	keep-power-in-suspend;
	301	status = "okay";
	302	};
	303
f651d781 HC	304	&usdhc3 {
	305	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	306	pinctrl-0 = <&pinctrl_usdhc3>;
	307	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	308	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	309	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	310	assigned-clock-rates = <400000000>;
	311	bus-width = <8>;
	312	fsl,tuning-step = <2>;
	313	non-removable;
	314	status = "okay";
	315	};
	316
5db106bc FL	317	&iomuxc {
	318	pinctrl-names = "default";
	319	pinctrl-0 = <&pinctrl_hog>;
	320
	321	imx7d-sdb {
47bcc8c0 FD	322	pinctrl_enet1: enet1grp {
	323	fsl,pins = <
	324	MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
	325	MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
	326	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
	327	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
	328	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
	329	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
	330	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
	331	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
	332	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
	333	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
	334	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
	335	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
	336	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
	337	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
	338	>;
	339	};
	340
	341	pinctrl_enet2: enet2grp {
	342	fsl,pins = <
	343	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
	344	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
	345	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
	346	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
	347	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
	348	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
	349	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
	350	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
	351	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
	352	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
	353	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
	354	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
	355	>;
	356	};
	357
5db106bc FL	358	pinctrl_hog: hoggrp {
	359	fsl,pins = <
	360	MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
	361	MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
	362	>;
	363	};
	364
	365	pinctrl_i2c1: i2c1grp {
	366	fsl,pins = <
	367	MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
	368	MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
	369	>;
	370	};
	371
	372	pinctrl_i2c2: i2c2grp {
	373	fsl,pins = <
	374	MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
	375	MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
	376	>;
	377	};
	378
	379	pinctrl_i2c3: i2c3grp {
	380	fsl,pins = <
	381	MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
	382	MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
	383	>;
	384	};
	385
	386	pinctrl_i2c4: i2c4grp {
	387	fsl,pins = <
	388	MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
	389	MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
	390	>;
	391	};
	392
5db106bc FL	393	pinctrl_uart1: uart1grp {
	394	fsl,pins = <
	395	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
	396	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
	397	>;
	398	};
	399
	400	pinctrl_uart5: uart5grp {
	401	fsl,pins = <
	402	MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
	403	MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
	404	MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
	405	MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
	406	>;
	407	};
	408
	409	pinctrl_uart6: uart6grp {
	410	fsl,pins = <
	411	MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
	412	MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
	413	MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
	414	MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
	415	>;
	416	};
	417
	418	pinctrl_usdhc1: usdhc1grp {
	419	fsl,pins = <
	420	MX7D_PAD_SD1_CMD__SD1_CMD 0x59
	421	MX7D_PAD_SD1_CLK__SD1_CLK 0x19
	422	MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
	423	MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
	424	MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
	425	MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
	426	MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
	427	MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
	428	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
	429	>;
	430	};
	431
	432	pinctrl_usdhc2: usdhc2grp {
	433	fsl,pins = <
	434	MX7D_PAD_SD2_CMD__SD2_CMD 0x59
	435	MX7D_PAD_SD2_CLK__SD2_CLK 0x19
	436	MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
	437	MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
	438	MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
	439	MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
	440	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
	441	>;
	442	};
	443
	444	pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
	445	fsl,pins = <
	446	MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
	447	MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
	448	MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
	449	MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
	450	MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
	451	MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
	452	>;
	453	};
	454
	455	pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
	456	fsl,pins = <
457	MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
458	MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
459	MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
460	MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
461	MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
462	MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
463	>;
464	};
465
466
467	pinctrl_usdhc3: usdhc3grp {
468	fsl,pins = <
469	MX7D_PAD_SD3_CMD__SD3_CMD 0x59
470	MX7D_PAD_SD3_CLK__SD3_CLK 0x19
471	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
472	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
473	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
474	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
475	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
476	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
477	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
478	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
479	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
480	>;
481	};
482
483	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
484	fsl,pins = <
485	MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
486	MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
487	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
488	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
489	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
490	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
491	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
492	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
493	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
494	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
495	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
496	>;
497	};
498
499	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
500	fsl,pins = <
501	MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
502	MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
503	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
504	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
505	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
506	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
507	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
508	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
509	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
510	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
511	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
512	>;
513	};
514
515	};
516	};