[deliverable/linux.git] / arch / arm / boot / dts / imx7d.dtsi

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/clock/imx7d-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx7d-pinfunc.h"
#include "skeleton.dtsi"

/ {
	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		serial6 = &uart7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			operating-points = <
				/* KHz	uV */
				996000	1075000
				792000	975000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
				 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
			clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	intc: interrupt-controller@31001000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x31001000 0x1000>,
		      <0x31002000 0x1000>,
		      <0x31004000 0x2000>,
		      <0x31006000 0x2000>;
	};

	ckil: clock-cki {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc: clock-osc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc";
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		aips1: aips-bus@30000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30000000 0x400000>;
			ranges;

			gpio1: gpio@30200000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@30250000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30250000 0x10000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio7: gpio@30260000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30260000 0x10000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpt1: gpt@302d0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x302d0000 0x10000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					 <&clks IMX7D_GPT1_ROOT_CLK>;
				clock-names = "ipg", "per";
			};

			gpt2: gpt@302e0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x302e0000 0x10000>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					 <&clks IMX7D_GPT2_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt3: gpt@302f0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x302f0000 0x10000>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					 <&clks IMX7D_GPT3_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: gpt@30300000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x30300000 0x10000>;
				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					 <&clks IMX7D_GPT4_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			iomuxc: iomuxc@30330000 {
				compatible = "fsl,imx7d-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			ocotp: ocotp-ctrl@30350000 {
				compatible = "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clks IMX7D_CLK_DUMMY>;
				status = "disabled";
			};

			anatop: anatop@30360000 {
				compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
					"syscon", "simple-bus";
				reg = <0x30360000 0x10000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

				reg_1p0d: regulator-vdd1p0d@210 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p0d";
					regulator-min-microvolt = <800000>;
					regulator-max-microvolt = <1200000>;
					anatop-reg-offset = <0x210>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <8>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1200000>;
					anatop-enable-bit = <31>;
				};
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x30370000 0x10000>;

				snvs-rtc-lp@34 {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					reg = <0x34 0x58>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			clks: ccm@30380000 {
				compatible = "fsl,imx7d-ccm";
				reg = <0x30380000 0x10000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>;
				clock-names = "ckil", "osc";
			};

			src: src@30390000 {
				compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};
		};

		aips3: aips-bus@30800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30800000 0x400000>;
			ranges;

			uart1: serial@30860000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30860000 0x10000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART1_ROOT_CLK>,
					<&clks IMX7D_UART1_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@30870000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30870000 0x10000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART2_ROOT_CLK>,
					<&clks IMX7D_UART2_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@30880000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30880000 0x10000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART3_ROOT_CLK>,
					<&clks IMX7D_UART3_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c1: i2c@30a20000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART4_ROOT_CLK>,
					<&clks IMX7D_UART4_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart5: serial@30a70000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a70000 0x10000>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART5_ROOT_CLK>,
					<&clks IMX7D_UART5_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@30a80000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a80000 0x10000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART6_ROOT_CLK>,
					<&clks IMX7D_UART6_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart7: serial@30a90000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a90000 0x10000>;
				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART7_ROOT_CLK>,
					<&clks IMX7D_UART7_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			usdhc1: usdhc@30b40000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_USDHC1_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: usdhc@30b50000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_USDHC2_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: usdhc@30b60000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_USDHC3_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
94967345 FL	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include <dt-bindings/clock/imx7d-clock.h>
	44	#include <dt-bindings/gpio/gpio.h>
	45	#include <dt-bindings/interrupt-controller/arm-gic.h>
	46	#include "imx7d-pinfunc.h"
	47	#include "skeleton.dtsi"
	48
	49	/ {
	50	aliases {
	51	gpio0 = &gpio1;
	52	gpio1 = &gpio2;
	53	gpio2 = &gpio3;
	54	gpio3 = &gpio4;
	55	gpio4 = &gpio5;
	56	gpio5 = &gpio6;
	57	gpio6 = &gpio7;
	58	i2c0 = &i2c1;
	59	i2c1 = &i2c2;
	60	i2c2 = &i2c3;
	61	i2c3 = &i2c4;
	62	mmc0 = &usdhc1;
	63	mmc1 = &usdhc2;
	64	mmc2 = &usdhc3;
65	serial0 = &uart1;
66	serial1 = &uart2;
67	serial2 = &uart3;
68	serial3 = &uart4;
69	serial4 = &uart5;
70	serial5 = &uart6;
71	serial6 = &uart7;
72	};
73
74	cpus {
75	#address-cells = <1>;
76	#size-cells = <0>;
77
78	cpu0: cpu@0 {
79	compatible = "arm,cortex-a7";
80	device_type = "cpu";
81	reg = <0>;
82	operating-points = <
83	/* KHz uV */
84	996000 1075000
85	792000 975000
86	>;
87	clock-latency = <61036>; /* two CLK32 periods */
88	clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
89	<&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
90	clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main";
91	};
92
93	cpu1: cpu@1 {
94	compatible = "arm,cortex-a7";
95	device_type = "cpu";
96	reg = <1>;
97	};
98	};
99
100	intc: interrupt-controller@31001000 {
101	compatible = "arm,cortex-a7-gic";
102	#interrupt-cells = <3>;
103	interrupt-controller;
104	reg = <0x31001000 0x1000>,
105	<0x31002000 0x1000>,
106	<0x31004000 0x2000>,
107	<0x31006000 0x2000>;
108	};
109
110	ckil: clock-cki {
111	compatible = "fixed-clock";
112	#clock-cells = <0>;
113	clock-frequency = <32768>;
114	clock-output-names = "ckil";
115	};
116
117	osc: clock-osc {
118	compatible = "fixed-clock";
119	#clock-cells = <0>;
120	clock-frequency = <24000000>;
121	clock-output-names = "osc";
122	};
123
124	soc {
125	#address-cells = <1>;
126	#size-cells = <1>;
127	compatible = "simple-bus";
128	interrupt-parent = <&intc>;
129	ranges;
130
131	aips1: aips-bus@30000000 {
132	compatible = "fsl,aips-bus", "simple-bus";
133	#address-cells = <1>;
134	#size-cells = <1>;
135	reg = <0x30000000 0x400000>;
136	ranges;
137
138	gpio1: gpio@30200000 {
139	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
140	reg = <0x30200000 0x10000>;
141	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
142	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
143	gpio-controller;
144	#gpio-cells = <2>;
145	interrupt-controller;
146	#interrupt-cells = <2>;
147	};
148
149	gpio2: gpio@30210000 {
150	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
151	reg = <0x30210000 0x10000>;
152	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
153	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
154	gpio-controller;
155	#gpio-cells = <2>;
156	interrupt-controller;
157	#interrupt-cells = <2>;
158	};
159
160	gpio3: gpio@30220000 {
161	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
162	reg = <0x30220000 0x10000>;
163	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
164	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
165	gpio-controller;
166	#gpio-cells = <2>;
167	interrupt-controller;
168	#interrupt-cells = <2>;
169	};
170
171	gpio4: gpio@30230000 {
172	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
173	reg = <0x30230000 0x10000>;
174	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
175	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
176	gpio-controller;
177	#gpio-cells = <2>;
178	interrupt-controller;
179	#interrupt-cells = <2>;
180	};
181
182	gpio5: gpio@30240000 {
183	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
184	reg = <0x30240000 0x10000>;
185	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
186	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
187	gpio-controller;
188	#gpio-cells = <2>;
189	interrupt-controller;
190	#interrupt-cells = <2>;
191	};
192
193	gpio6: gpio@30250000 {
194	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
195	reg = <0x30250000 0x10000>;
196	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
197	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
198	gpio-controller;
199	#gpio-cells = <2>;
200	interrupt-controller;
201	#interrupt-cells = <2>;
202	};
203
204	gpio7: gpio@30260000 {
205	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
206	reg = <0x30260000 0x10000>;
207	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
208	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
209	gpio-controller;
210	#gpio-cells = <2>;
211	interrupt-controller;
212	#interrupt-cells = <2>;
213	};
214
215	gpt1: gpt@302d0000 {
216	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
217	reg = <0x302d0000 0x10000>;
218	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
219	clocks = <&clks IMX7D_CLK_DUMMY>,
220	<&clks IMX7D_GPT1_ROOT_CLK>;
221	clock-names = "ipg", "per";
222	};
223
224	gpt2: gpt@302e0000 {
225	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
226	reg = <0x302e0000 0x10000>;
227	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
228	clocks = <&clks IMX7D_CLK_DUMMY>,
229	<&clks IMX7D_GPT2_ROOT_CLK>;
230	clock-names = "ipg", "per";
231	status = "disabled";
232	};
233
234	gpt3: gpt@302f0000 {
235	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
236	reg = <0x302f0000 0x10000>;
237	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
238	clocks = <&clks IMX7D_CLK_DUMMY>,
239	<&clks IMX7D_GPT3_ROOT_CLK>;
240	clock-names = "ipg", "per";
241	status = "disabled";
242	};
243
244	gpt4: gpt@30300000 {
245	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
246	reg = <0x30300000 0x10000>;
247	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
248	clocks = <&clks IMX7D_CLK_DUMMY>,
249	<&clks IMX7D_GPT4_ROOT_CLK>;
250	clock-names = "ipg", "per";
251	status = "disabled";
252	};
253
254	iomuxc: iomuxc@30330000 {
255	compatible = "fsl,imx7d-iomuxc";
256	reg = <0x30330000 0x10000>;
257	};
258
259	gpr: iomuxc-gpr@30340000 {
260	compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
261	reg = <0x30340000 0x10000>;
262	};
263
264	ocotp: ocotp-ctrl@30350000 {
265	compatible = "syscon";
266	reg = <0x30350000 0x10000>;
267	clocks = <&clks IMX7D_CLK_DUMMY>;
268	status = "disabled";
269	};
270
271	anatop: anatop@30360000 {
272	compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
273	"syscon", "simple-bus";
274	reg = <0x30360000 0x10000>;
275	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
276	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
277
278	reg_1p0d: regulator-vdd1p0d@210 {
279	compatible = "fsl,anatop-regulator";
280	regulator-name = "vdd1p0d";
281	regulator-min-microvolt = <800000>;
282	regulator-max-microvolt = <1200000>;
283	anatop-reg-offset = <0x210>;
284	anatop-vol-bit-shift = <8>;
285	anatop-vol-bit-width = <5>;
286	anatop-min-bit-val = <8>;
287	anatop-min-voltage = <800000>;
288	anatop-max-voltage = <1200000>;
289	anatop-enable-bit = <31>;
290	};
291	};
292
293	snvs: snvs@30370000 {
294	compatible = "fsl,sec-v4.0-mon", "simple-bus";
295	#address-cells = <1>;
296	#size-cells = <1>;
297	ranges = <0 0x30370000 0x10000>;
298
299	snvs-rtc-lp@34 {
300	compatible = "fsl,sec-v4.0-mon-rtc-lp";
301	reg = <0x34 0x58>;
302	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
303	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
304	};
305	};
306
307	clks: ccm@30380000 {
308	compatible = "fsl,imx7d-ccm";
309	reg = <0x30380000 0x10000>;
310	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
311	<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
312	#clock-cells = <1>;
313	clocks = <&ckil>, <&osc>;
314	clock-names = "ckil", "osc";
315	};
316
317	src: src@30390000 {
318	compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
319	reg = <0x30390000 0x10000>;
320	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
321	#reset-cells = <1>;
322	};
323	};
324
325	aips3: aips-bus@30800000 {
326	compatible = "fsl,aips-bus", "simple-bus";
327	#address-cells = <1>;
328	#size-cells = <1>;
329	reg = <0x30800000 0x400000>;
330	ranges;
331
332	uart1: serial@30860000 {
333	compatible = "fsl,imx7d-uart",
334	"fsl,imx6q-uart";
335	reg = <0x30860000 0x10000>;
336	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
337	clocks = <&clks IMX7D_UART1_ROOT_CLK>,
338	<&clks IMX7D_UART1_ROOT_CLK>;
339	clock-names = "ipg", "per";
340	status = "disabled";
341	};
342
343	uart2: serial@30870000 {
344	compatible = "fsl,imx7d-uart",
345	"fsl,imx6q-uart";
346	reg = <0x30870000 0x10000>;
347	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
348	clocks = <&clks IMX7D_UART2_ROOT_CLK>,
349	<&clks IMX7D_UART2_ROOT_CLK>;
350	clock-names = "ipg", "per";
351	status = "disabled";
352	};
353
354	uart3: serial@30880000 {
355	compatible = "fsl,imx7d-uart",
356	"fsl,imx6q-uart";
357	reg = <0x30880000 0x10000>;
358	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
359	clocks = <&clks IMX7D_UART3_ROOT_CLK>,
360	<&clks IMX7D_UART3_ROOT_CLK>;
361	clock-names = "ipg", "per";
362	status = "disabled";
363	};
364
365	i2c1: i2c@30a20000 {
366	#address-cells = <1>;
367	#size-cells = <0>;
368	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
369	reg = <0x30a20000 0x10000>;
370	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
371	clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
372	status = "disabled";
373	};
374
375	i2c2: i2c@30a30000 {
376	#address-cells = <1>;
377	#size-cells = <0>;
378	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
379	reg = <0x30a30000 0x10000>;
380	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
381	clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
382	status = "disabled";
383	};
384
385	i2c3: i2c@30a40000 {
386	#address-cells = <1>;
387	#size-cells = <0>;
388	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
389	reg = <0x30a40000 0x10000>;
390	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
391	clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
392	status = "disabled";
393	};
394
395	i2c4: i2c@30a50000 {
396	#address-cells = <1>;
397	#size-cells = <0>;
398	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
399	reg = <0x30a50000 0x10000>;
400	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
401	clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
402	status = "disabled";
403	};
404
405	uart4: serial@30a60000 {
406	compatible = "fsl,imx7d-uart",
407	"fsl,imx6q-uart";
408	reg = <0x30a60000 0x10000>;
409	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
410	clocks = <&clks IMX7D_UART4_ROOT_CLK>,
411	<&clks IMX7D_UART4_ROOT_CLK>;
412	clock-names = "ipg", "per";
413	status = "disabled";
414	};
415
416	uart5: serial@30a70000 {
417	compatible = "fsl,imx7d-uart",
418	"fsl,imx6q-uart";
419	reg = <0x30a70000 0x10000>;
420	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
421	clocks = <&clks IMX7D_UART5_ROOT_CLK>,
422	<&clks IMX7D_UART5_ROOT_CLK>;
423	clock-names = "ipg", "per";
424	status = "disabled";
425	};
426
427	uart6: serial@30a80000 {
428	compatible = "fsl,imx7d-uart",
429	"fsl,imx6q-uart";
430	reg = <0x30a80000 0x10000>;
431	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
432	clocks = <&clks IMX7D_UART6_ROOT_CLK>,
433	<&clks IMX7D_UART6_ROOT_CLK>;
434	clock-names = "ipg", "per";
435	status = "disabled";
436	};
437
438	uart7: serial@30a90000 {
439	compatible = "fsl,imx7d-uart",
440	"fsl,imx6q-uart";
441	reg = <0x30a90000 0x10000>;
442	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
443	clocks = <&clks IMX7D_UART7_ROOT_CLK>,
444	<&clks IMX7D_UART7_ROOT_CLK>;
445	clock-names = "ipg", "per";
446	status = "disabled";
447	};
448
449	usdhc1: usdhc@30b40000 {
450	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
451	reg = <0x30b40000 0x10000>;
452	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
453	clocks = <&clks IMX7D_CLK_DUMMY>,
454	<&clks IMX7D_CLK_DUMMY>,
455	<&clks IMX7D_USDHC1_ROOT_CLK>;
456	clock-names = "ipg", "ahb", "per";
457	bus-width = <4>;
458	status = "disabled";
459	};
460
461	usdhc2: usdhc@30b50000 {
462	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
463	reg = <0x30b50000 0x10000>;
464	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
465	clocks = <&clks IMX7D_CLK_DUMMY>,
466	<&clks IMX7D_CLK_DUMMY>,
467	<&clks IMX7D_USDHC2_ROOT_CLK>;
468	clock-names = "ipg", "ahb", "per";
469	bus-width = <4>;
470	status = "disabled";
471	};
472
473	usdhc3: usdhc@30b60000 {
474	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
475	reg = <0x30b60000 0x10000>;
476	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
477	clocks = <&clks IMX7D_CLK_DUMMY>,
478	<&clks IMX7D_CLK_DUMMY>,
479	<&clks IMX7D_USDHC3_ROOT_CLK>;
480	clock-names = "ipg", "ahb", "per";
481	bus-width = <4>;
482	status = "disabled";
483	};
484	};
485	};
486	};