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209636b6 MK |
1 | /* |
2 | * Copyright 2014 Texas Instruments, Inc. | |
3 | * | |
4 | * Keystone 2 Edison SoC specific device tree | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | clocks { | |
12 | mainpllclk: mainpllclk@2310110 { | |
13 | #clock-cells = <0>; | |
14 | compatible = "ti,keystone,main-pll-clock"; | |
15 | clocks = <&refclksys>; | |
c1bfa985 MK |
16 | reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; |
17 | reg-names = "control", "multiplier", "post-divider"; | |
209636b6 MK |
18 | }; |
19 | ||
20 | papllclk: papllclk@2620358 { | |
21 | #clock-cells = <0>; | |
22 | compatible = "ti,keystone,pll-clock"; | |
23 | clocks = <&refclkpass>; | |
2b7ef094 | 24 | clock-output-names = "papllclk"; |
209636b6 MK |
25 | reg = <0x02620358 4>; |
26 | reg-names = "control"; | |
27 | }; | |
28 | ||
29 | ddr3apllclk: ddr3apllclk@2620360 { | |
30 | #clock-cells = <0>; | |
31 | compatible = "ti,keystone,pll-clock"; | |
32 | clocks = <&refclkddr3a>; | |
33 | clock-output-names = "ddr-3a-pll-clk"; | |
34 | reg = <0x02620360 4>; | |
35 | reg-names = "control"; | |
36 | }; | |
37 | ||
38 | clkusb1: clkusb1 { | |
39 | #clock-cells = <0>; | |
40 | compatible = "ti,keystone,psc-clock"; | |
41 | clocks = <&chipclk16>; | |
99897500 | 42 | clock-output-names = "usb1"; |
209636b6 MK |
43 | reg = <0x02350004 0xb00>, <0x02350000 0x400>; |
44 | reg-names = "control", "domain"; | |
45 | domain-id = <0>; | |
46 | }; | |
47 | ||
48 | clkhyperlink0: clkhyperlink0 { | |
49 | #clock-cells = <0>; | |
50 | compatible = "ti,keystone,psc-clock"; | |
51 | clocks = <&chipclk12>; | |
52 | clock-output-names = "hyperlink-0"; | |
53 | reg = <0x02350030 0xb00>, <0x02350014 0x400>; | |
54 | reg-names = "control", "domain"; | |
55 | domain-id = <5>; | |
56 | }; | |
57 | ||
58 | clkpcie1: clkpcie1 { | |
59 | #clock-cells = <0>; | |
60 | compatible = "ti,keystone,psc-clock"; | |
61 | clocks = <&chipclk12>; | |
99897500 MK |
62 | clock-output-names = "pcie1"; |
63 | reg = <0x0235006c 0xb00>, <0x02350048 0x400>; | |
209636b6 MK |
64 | reg-names = "control", "domain"; |
65 | domain-id = <18>; | |
66 | }; | |
67 | ||
68 | clkxge: clkxge { | |
69 | #clock-cells = <0>; | |
70 | compatible = "ti,keystone,psc-clock"; | |
71 | clocks = <&chipclk13>; | |
72 | clock-output-names = "xge"; | |
73 | reg = <0x023500c8 0xb00>, <0x02350074 0x400>; | |
74 | reg-names = "control", "domain"; | |
75 | domain-id = <29>; | |
76 | }; | |
77 | }; |