projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d5e9fe84 SS |
1 | /* |
| 2 | * Copyright 2013 Texas Instruments, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| eb788f43 SS |
9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | ||
| 226d1c5b | 11 | #include "skeleton.dtsi" |
| d5e9fe84 SS |
12 | |
| 13 | / { | |
| 14 | model = "Texas Instruments Keystone 2 SoC"; | |
| d5e9fe84 SS |
15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; | |
| 17 | interrupt-parent = <&gic>; | |
| 18 | ||
| 19 | aliases { | |
| 20 | serial0 = &uart0; | |
| 21 | }; | |
| 22 | ||
| 23 | memory { | |
| 24 | reg = <0x00000000 0x80000000 0x00000000 0x40000000>; | |
| 25 | }; | |
| 26 | ||
| 27 | cpus { | |
| 28 | #address-cells = <1>; | |
| 29 | #size-cells = <0>; | |
| 30 | ||
| 31 | interrupt-parent = <&gic>; | |
| 32 | ||
| 33 | cpu@0 { | |
| 34 | compatible = "arm,cortex-a15"; | |
| 35 | device_type = "cpu"; | |
| 36 | reg = <0>; | |
| 37 | }; | |
| 38 | ||
| 39 | cpu@1 { | |
| 40 | compatible = "arm,cortex-a15"; | |
| 41 | device_type = "cpu"; | |
| 42 | reg = <1>; | |
| 43 | }; | |
| 44 | ||
| 45 | cpu@2 { | |
| 46 | compatible = "arm,cortex-a15"; | |
| 47 | device_type = "cpu"; | |
| 48 | reg = <2>; | |
| 49 | }; | |
| 50 | ||
| 51 | cpu@3 { | |
| 52 | compatible = "arm,cortex-a15"; | |
| 53 | device_type = "cpu"; | |
| 54 | reg = <3>; | |
| 55 | }; | |
| 56 | }; | |
| 57 | ||
| 58 | gic: interrupt-controller { | |
| 59 | compatible = "arm,cortex-a15-gic"; | |
| 60 | #interrupt-cells = <3>; | |
| 61 | #size-cells = <0>; | |
| 62 | #address-cells = <1>; | |
| 63 | interrupt-controller; | |
| 64 | reg = <0x0 0x02561000 0x0 0x1000>, | |
| a18b4aa2 SS |
65 | <0x0 0x02562000 0x0 0x2000>, |
| 66 | <0x0 0x02564000 0x0 0x1000>, | |
| 67 | <0x0 0x02566000 0x0 0x2000>; | |
| d5e9fe84 SS |
68 | }; |
| 69 | ||
| 70 | timer { | |
| 71 | compatible = "arm,armv7-timer"; | |
| eb788f43 SS |
72 | interrupts = |
| 73 | <GIC_PPI 13 | |
| 74 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 75 | <GIC_PPI 14 | |
| 76 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 77 | <GIC_PPI 11 | |
| 78 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 79 | <GIC_PPI 10 | |
| 80 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| d5e9fe84 SS |
81 | }; |
| 82 | ||
| 83 | pmu { | |
| 84 | compatible = "arm,cortex-a15-pmu"; | |
| eb788f43 SS |
85 | interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, |
| 86 | <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, | |
| 87 | <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, | |
| 88 | <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; | |
| d5e9fe84 SS |
89 | }; |
| 90 | ||
| 91 | soc { | |
| 92 | #address-cells = <1>; | |
| 93 | #size-cells = <1>; | |
| 94 | compatible = "ti,keystone","simple-bus"; | |
| 95 | interrupt-parent = <&gic>; | |
| 96 | ranges = <0x0 0x0 0x0 0xc0000000>; | |
| 97 | ||
| 98 | rstctrl: reset-controller { | |
| 99 | compatible = "ti,keystone-reset"; | |
| 100 | reg = <0x023100e8 4>; /* pll reset control reg */ | |
| 101 | }; | |
| 102 | ||
| feeea8f3 SS |
103 | /include/ "keystone-clocks.dtsi" |
| 104 | ||
| d5e9fe84 SS |
105 | uart0: serial@02530c00 { |
| 106 | compatible = "ns16550a"; | |
| 107 | current-speed = <115200>; | |
| 108 | reg-shift = <2>; | |
| 109 | reg-io-width = <4>; | |
| 110 | reg = <0x02530c00 0x100>; | |
| f023bd10 | 111 | clocks = <&clkuart0>; |
| eb788f43 | 112 | interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; |
| d5e9fe84 SS |
113 | }; |
| 114 | ||
| 115 | uart1: serial@02531000 { | |
| 116 | compatible = "ns16550a"; | |
| 117 | current-speed = <115200>; | |
| 118 | reg-shift = <2>; | |
| 119 | reg-io-width = <4>; | |
| 120 | reg = <0x02531000 0x100>; | |
| f023bd10 | 121 | clocks = <&clkuart1>; |
| eb788f43 | 122 | interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; |
| d5e9fe84 SS |
123 | }; |
| 124 | ||
| 6120ac23 SS |
125 | i2c0: i2c@2530000 { |
| 126 | compatible = "ti,davinci-i2c"; | |
| 127 | reg = <0x02530000 0x400>; | |
| 128 | clock-frequency = <100000>; | |
| 129 | clocks = <&clki2c>; | |
| 130 | interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; | |
| 131 | #address-cells = <1>; | |
| 132 | #size-cells = <0>; | |
| 133 | ||
| 134 | dtt@50 { | |
| 135 | compatible = "at,24c1024"; | |
| 136 | reg = <0x50>; | |
| 137 | }; | |
| 138 | }; | |
| 139 | ||
| 140 | i2c1: i2c@2530400 { | |
| 141 | compatible = "ti,davinci-i2c"; | |
| 142 | reg = <0x02530400 0x400>; | |
| 143 | clock-frequency = <100000>; | |
| 144 | clocks = <&clki2c>; | |
| 145 | interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; | |
| 146 | }; | |
| 147 | ||
| 148 | i2c2: i2c@2530800 { | |
| 149 | compatible = "ti,davinci-i2c"; | |
| 150 | reg = <0x02530800 0x400>; | |
| 151 | clock-frequency = <100000>; | |
| 152 | clocks = <&clki2c>; | |
| 153 | interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; | |
| 154 | }; | |
| b3bd6c59 SS |
155 | |
| 156 | spi0: spi@21000400 { | |
| 157 | compatible = "ti,dm6441-spi"; | |
| 158 | reg = <0x21000400 0x200>; | |
| 159 | num-cs = <4>; | |
| 160 | ti,davinci-spi-intr-line = <0>; | |
| 161 | interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; | |
| 162 | clocks = <&clkspi>; | |
| 163 | }; | |
| 164 | ||
| 165 | spi1: spi@21000600 { | |
| 166 | compatible = "ti,dm6441-spi"; | |
| 167 | reg = <0x21000600 0x200>; | |
| 168 | num-cs = <4>; | |
| 169 | ti,davinci-spi-intr-line = <0>; | |
| 170 | interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; | |
| 171 | clocks = <&clkspi>; | |
| 172 | }; | |
| 173 | ||
| 174 | spi2: spi@21000800 { | |
| 175 | compatible = "ti,dm6441-spi"; | |
| 176 | reg = <0x21000800 0x200>; | |
| 177 | num-cs = <4>; | |
| 178 | ti,davinci-spi-intr-line = <0>; | |
| 179 | interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; | |
| 180 | clocks = <&clkspi>; | |
| 181 | }; | |
| d5e9fe84 SS |
182 | }; |
| 183 | }; |