Commit | Line | Data |
---|---|---|
82bb2da1 | 1 | / { |
54397d85 | 2 | mbus { |
7b36efd0 | 3 | pciec: pcie-controller { |
54397d85 EG |
4 | compatible = "marvell,kirkwood-pcie"; |
5 | status = "disabled"; | |
6 | device_type = "pci"; | |
7 | ||
8 | #address-cells = <3>; | |
9 | #size-cells = <2>; | |
10 | ||
11 | bus-range = <0x00 0xff>; | |
12 | ||
13 | ranges = | |
14 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | |
16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; | |
17 | ||
7b36efd0 | 18 | pcie0: pcie@1,0 { |
54397d85 EG |
19 | device_type = "pci"; |
20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | |
21 | reg = <0x0800 0 0 0 0>; | |
22 | #address-cells = <3>; | |
23 | #size-cells = <2>; | |
24 | #interrupt-cells = <1>; | |
25 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
26 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
27 | interrupt-map-mask = <0 0 0 0>; | |
28 | interrupt-map = <0 0 0 0 &intc 9>; | |
29 | marvell,pcie-port = <0>; | |
30 | marvell,pcie-lane = <0>; | |
31 | clocks = <&gate_clk 2>; | |
32 | status = "disabled"; | |
33 | }; | |
34 | }; | |
35 | }; | |
36 | ||
82bb2da1 AL |
37 | ocp@f1000000 { |
38 | pinctrl: pinctrl@10000 { | |
39 | compatible = "marvell,88f6281-pinctrl"; | |
40 | reg = <0x10000 0x20>; | |
41 | ||
42 | pmx_nand: pmx-nand { | |
43 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | |
44 | "mpp4", "mpp5", "mpp18", | |
45 | "mpp19"; | |
46 | marvell,function = "nand"; | |
47 | }; | |
48 | pmx_sata0: pmx-sata0 { | |
49 | marvell,pins = "mpp5", "mpp21", "mpp23"; | |
50 | marvell,function = "sata0"; | |
51 | }; | |
52 | pmx_sata1: pmx-sata1 { | |
53 | marvell,pins = "mpp4", "mpp20", "mpp22"; | |
54 | marvell,function = "sata1"; | |
55 | }; | |
56 | pmx_spi: pmx-spi { | |
57 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; | |
58 | marvell,function = "spi"; | |
59 | }; | |
60 | pmx_twsi0: pmx-twsi0 { | |
61 | marvell,pins = "mpp8", "mpp9"; | |
62 | marvell,function = "twsi0"; | |
63 | }; | |
64 | pmx_uart0: pmx-uart0 { | |
65 | marvell,pins = "mpp10", "mpp11"; | |
66 | marvell,function = "uart0"; | |
67 | }; | |
68 | pmx_uart1: pmx-uart1 { | |
69 | marvell,pins = "mpp13", "mpp14"; | |
70 | marvell,function = "uart1"; | |
71 | }; | |
de64ee5e SP |
72 | pmx_sdio: pmx-sdio { |
73 | marvell,pins = "mpp12", "mpp13", "mpp14", | |
74 | "mpp15", "mpp16", "mpp17"; | |
75 | marvell,function = "sdio"; | |
76 | }; | |
82bb2da1 | 77 | }; |
670ee03c | 78 | |
7b36efd0 | 79 | rtc: rtc@10300 { |
df6bf2e9 VL |
80 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
81 | reg = <0x10300 0x20>; | |
82 | interrupts = <53>; | |
83 | clocks = <&gate_clk 7>; | |
84 | }; | |
85 | ||
7b36efd0 | 86 | sata: sata@80000 { |
df6bf2e9 VL |
87 | compatible = "marvell,orion-sata"; |
88 | reg = <0x80000 0x5000>; | |
89 | interrupts = <21>; | |
90 | clocks = <&gate_clk 14>, <&gate_clk 15>; | |
91 | clock-names = "0", "1"; | |
0ad82cd8 AL |
92 | phys = <&sata_phy0>, <&sata_phy1>; |
93 | phy-names = "port0", "port1"; | |
df6bf2e9 VL |
94 | status = "disabled"; |
95 | }; | |
96 | ||
7b36efd0 | 97 | sdio: mvsdio@90000 { |
df6bf2e9 VL |
98 | compatible = "marvell,orion-sdio"; |
99 | reg = <0x90000 0x200>; | |
100 | interrupts = <28>; | |
101 | clocks = <&gate_clk 4>; | |
0242399e SH |
102 | pinctrl-0 = <&pmx_sdio>; |
103 | pinctrl-names = "default"; | |
df6bf2e9 VL |
104 | bus-width = <4>; |
105 | cap-sdio-irq; | |
106 | cap-sd-highspeed; | |
107 | cap-mmc-highspeed; | |
108 | status = "disabled"; | |
109 | }; | |
82bb2da1 | 110 | }; |
de64ee5e | 111 | }; |