projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3d468b6d JC |
1 | /include/ "skeleton.dtsi" |
| 2 | ||
| 3ec81e7e EG |
3 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
| 4 | ||
| 3d468b6d | 5 | / { |
| 77843504 | 6 | compatible = "marvell,kirkwood"; |
| 278b45b0 AL |
7 | interrupt-parent = <&intc>; |
| 8 | ||
| 33a66754 AB |
9 | cpus { |
| 10 | #address-cells = <1>; | |
| 11 | #size-cells = <0>; | |
| 12 | ||
| 13 | cpu@0 { | |
| 14 | device_type = "cpu"; | |
| 15 | compatible = "marvell,feroceon"; | |
| 2290414b | 16 | reg = <0>; |
| 33a66754 AB |
17 | clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; |
| 18 | clock-names = "cpu_clk", "ddrclk", "powersave"; | |
| 19 | }; | |
| 20 | }; | |
| 21 | ||
| f9e75922 AL |
22 | aliases { |
| 23 | gpio0 = &gpio0; | |
| 24 | gpio1 = &gpio1; | |
| 25 | }; | |
| 3d468b6d | 26 | |
| 455f81a3 EG |
27 | mbus { |
| 28 | compatible = "marvell,kirkwood-mbus", "simple-bus"; | |
| 54397d85 EG |
29 | #address-cells = <2>; |
| 30 | #size-cells = <1>; | |
| 7f69f8a4 JG |
31 | /* If a board file needs to change this ranges it must replace it completely */ |
| 32 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */ | |
| 33 | MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */ | |
| 34 | MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */ | |
| 35 | >; | |
| 455f81a3 | 36 | controller = <&mbusc>; |
| 54397d85 EG |
37 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ |
| 38 | pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ | |
| 34a30090 JG |
39 | |
| 40 | crypto@0301 { | |
| 41 | compatible = "marvell,orion-crypto"; | |
| 42 | reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>, | |
| 43 | <MBUS_ID(0x03, 0x01) 0 0x800>; | |
| 44 | reg-names = "regs", "sram"; | |
| 45 | interrupts = <22>; | |
| 46 | clocks = <&gate_clk 17>; | |
| 47 | status = "okay"; | |
| 48 | }; | |
| 7045ff5a JG |
49 | |
| 50 | nand: nand@012f { | |
| 51 | #address-cells = <1>; | |
| 52 | #size-cells = <1>; | |
| 53 | cle = <0>; | |
| 54 | ale = <1>; | |
| 55 | bank-width = <1>; | |
| 56 | compatible = "marvell,orion-nand"; | |
| 57 | reg = <MBUS_ID(0x01, 0x2f) 0 0x400>; | |
| 58 | chip-delay = <25>; | |
| 59 | /* set partition map and/or chip-delay in board dts */ | |
| 60 | clocks = <&gate_clk 7>; | |
| 61 | status = "disabled"; | |
| 62 | }; | |
| 455f81a3 EG |
63 | }; |
| 64 | ||
| 163f2cea JC |
65 | ocp@f1000000 { |
| 66 | compatible = "simple-bus"; | |
| 7045ff5a | 67 | ranges = <0x00000000 0xf1000000 0x0100000>; |
| 163f2cea JC |
68 | #address-cells = <1>; |
| 69 | #size-cells = <1>; | |
| 70 | ||
| 455f81a3 EG |
71 | mbusc: mbus-controller@20000 { |
| 72 | compatible = "marvell,mbus-controller"; | |
| 73 | reg = <0x20000 0x80>, <0x1500 0x20>; | |
| 74 | }; | |
| 75 | ||
| 15f18591 SH |
76 | timer: timer@20300 { |
| 77 | compatible = "marvell,orion-timer"; | |
| 78 | reg = <0x20300 0x20>; | |
| 79 | interrupt-parent = <&bridge_intc>; | |
| 80 | interrupts = <1>, <2>; | |
| 81 | clocks = <&core_clk 0>; | |
| 82 | }; | |
| 83 | ||
| 84 | intc: main-interrupt-ctrl@20200 { | |
| 85 | compatible = "marvell,orion-intc"; | |
| 86 | interrupt-controller; | |
| 87 | #interrupt-cells = <1>; | |
| 88 | reg = <0x20200 0x10>, <0x20210 0x10>; | |
| 89 | }; | |
| 90 | ||
| 91 | bridge_intc: bridge-interrupt-ctrl@20110 { | |
| 92 | compatible = "marvell,orion-bridge-intc"; | |
| 93 | interrupt-controller; | |
| 94 | #interrupt-cells = <1>; | |
| 95 | reg = <0x20110 0x8>; | |
| 96 | interrupts = <1>; | |
| 97 | marvell,#interrupts = <6>; | |
| 98 | }; | |
| 99 | ||
| 1611f872 AL |
100 | core_clk: core-clocks@10030 { |
| 101 | compatible = "marvell,kirkwood-core-clock"; | |
| 102 | reg = <0x10030 0x4>; | |
| 103 | #clock-cells = <1>; | |
| 104 | }; | |
| 105 | ||
| 278b45b0 AL |
106 | gpio0: gpio@10100 { |
| 107 | compatible = "marvell,orion-gpio"; | |
| 108 | #gpio-cells = <2>; | |
| 109 | gpio-controller; | |
| 110 | reg = <0x10100 0x40>; | |
| f9e75922 AL |
111 | ngpios = <32>; |
| 112 | interrupt-controller; | |
| 09d75bc7 | 113 | #interrupt-cells = <2>; |
| 278b45b0 | 114 | interrupts = <35>, <36>, <37>, <38>; |
| de88747f | 115 | clocks = <&gate_clk 7>; |
| 278b45b0 AL |
116 | }; |
| 117 | ||
| 118 | gpio1: gpio@10140 { | |
| 119 | compatible = "marvell,orion-gpio"; | |
| 120 | #gpio-cells = <2>; | |
| 121 | gpio-controller; | |
| 122 | reg = <0x10140 0x40>; | |
| f9e75922 AL |
123 | ngpios = <18>; |
| 124 | interrupt-controller; | |
| 09d75bc7 | 125 | #interrupt-cells = <2>; |
| 278b45b0 | 126 | interrupts = <39>, <40>, <41>; |
| de88747f | 127 | clocks = <&gate_clk 7>; |
| 278b45b0 AL |
128 | }; |
| 129 | ||
| 163f2cea JC |
130 | serial@12000 { |
| 131 | compatible = "ns16550a"; | |
| 132 | reg = <0x12000 0x100>; | |
| 133 | reg-shift = <2>; | |
| 134 | interrupts = <33>; | |
| 1611f872 | 135 | clocks = <&gate_clk 7>; |
| 163f2cea JC |
136 | status = "disabled"; |
| 137 | }; | |
| 138 | ||
| 139 | serial@12100 { | |
| 140 | compatible = "ns16550a"; | |
| 141 | reg = <0x12100 0x100>; | |
| 142 | reg-shift = <2>; | |
| 143 | interrupts = <34>; | |
| 1611f872 | 144 | clocks = <&gate_clk 7>; |
| 163f2cea JC |
145 | status = "disabled"; |
| 146 | }; | |
| e871b87a | 147 | |
| 76372120 MW |
148 | spi@10600 { |
| 149 | compatible = "marvell,orion-spi"; | |
| 150 | #address-cells = <1>; | |
| 151 | #size-cells = <0>; | |
| 152 | cell-index = <0>; | |
| 153 | interrupts = <23>; | |
| 154 | reg = <0x10600 0x28>; | |
| 1611f872 | 155 | clocks = <&gate_clk 7>; |
| 76372120 MW |
156 | status = "disabled"; |
| 157 | }; | |
| 158 | ||
| 1611f872 AL |
159 | gate_clk: clock-gating-control@2011c { |
| 160 | compatible = "marvell,kirkwood-gating-clock"; | |
| 161 | reg = <0x2011c 0x4>; | |
| 162 | clocks = <&core_clk 0>; | |
| 163 | #clock-cells = <1>; | |
| 164 | }; | |
| 165 | ||
| 15f18591 | 166 | wdt: watchdog-timer@20300 { |
| 1e7bad0f AL |
167 | compatible = "marvell,orion-wdt"; |
| 168 | reg = <0x20300 0x28>; | |
| 15f18591 SH |
169 | interrupt-parent = <&bridge_intc>; |
| 170 | interrupts = <3>; | |
| 1611f872 | 171 | clocks = <&gate_clk 7>; |
| 1e7bad0f AL |
172 | status = "okay"; |
| 173 | }; | |
| 174 | ||
| c896ed0f AL |
175 | xor@60800 { |
| 176 | compatible = "marvell,orion-xor"; | |
| 177 | reg = <0x60800 0x100 | |
| 178 | 0x60A00 0x100>; | |
| 179 | status = "okay"; | |
| 180 | clocks = <&gate_clk 8>; | |
| 181 | ||
| 182 | xor00 { | |
| 183 | interrupts = <5>; | |
| 184 | dmacap,memcpy; | |
| 185 | dmacap,xor; | |
| 186 | }; | |
| 187 | xor01 { | |
| 188 | interrupts = <6>; | |
| 189 | dmacap,memcpy; | |
| 190 | dmacap,xor; | |
| 191 | dmacap,memset; | |
| 192 | }; | |
| 193 | }; | |
| 194 | ||
| 195 | xor@60900 { | |
| 196 | compatible = "marvell,orion-xor"; | |
| 197 | reg = <0x60900 0x100 | |
| ddf7e399 | 198 | 0x60B00 0x100>; |
| 1e7bad0f | 199 | status = "okay"; |
| c896ed0f AL |
200 | clocks = <&gate_clk 16>; |
| 201 | ||
| 202 | xor00 { | |
| 203 | interrupts = <7>; | |
| 204 | dmacap,memcpy; | |
| 205 | dmacap,xor; | |
| 206 | }; | |
| 207 | xor01 { | |
| 208 | interrupts = <8>; | |
| 209 | dmacap,memcpy; | |
| 210 | dmacap,xor; | |
| 211 | dmacap,memset; | |
| 212 | }; | |
| 1e7bad0f AL |
213 | }; |
| 214 | ||
| b6cf8070 AL |
215 | ehci@50000 { |
| 216 | compatible = "marvell,orion-ehci"; | |
| 217 | reg = <0x50000 0x1000>; | |
| 218 | interrupts = <19>; | |
| 53dfa8e4 | 219 | clocks = <&gate_clk 3>; |
| b6cf8070 AL |
220 | status = "okay"; |
| 221 | }; | |
| 222 | ||
| e91cac0a AL |
223 | i2c@11000 { |
| 224 | compatible = "marvell,mv64xxx-i2c"; | |
| 225 | reg = <0x11000 0x20>; | |
| 226 | #address-cells = <1>; | |
| 227 | #size-cells = <0>; | |
| 228 | interrupts = <29>; | |
| 229 | clock-frequency = <100000>; | |
| 1611f872 | 230 | clocks = <&gate_clk 7>; |
| e91cac0a AL |
231 | status = "disabled"; |
| 232 | }; | |
| f37fbd36 | 233 | |
| 876e2333 SH |
234 | mdio: mdio-bus@72004 { |
| 235 | compatible = "marvell,orion-mdio"; | |
| 236 | #address-cells = <1>; | |
| 237 | #size-cells = <0>; | |
| 238 | reg = <0x72004 0x84>; | |
| 239 | interrupts = <46>; | |
| 240 | clocks = <&gate_clk 0>; | |
| 241 | status = "disabled"; | |
| 242 | ||
| 243 | /* add phy nodes in board file */ | |
| 244 | }; | |
| 245 | ||
| 246 | eth0: ethernet-controller@72000 { | |
| 247 | compatible = "marvell,kirkwood-eth"; | |
| 248 | #address-cells = <1>; | |
| 249 | #size-cells = <0>; | |
| 250 | reg = <0x72000 0x4000>; | |
| 251 | clocks = <&gate_clk 0>; | |
| 252 | marvell,tx-checksum-limit = <1600>; | |
| 253 | status = "disabled"; | |
| 254 | ||
| 255 | ethernet0-port@0 { | |
| 256 | device_type = "network"; | |
| 257 | compatible = "marvell,kirkwood-eth-port"; | |
| 258 | reg = <0>; | |
| 259 | interrupts = <11>; | |
| 260 | /* overwrite MAC address in bootloader */ | |
| 261 | local-mac-address = [00 00 00 00 00 00]; | |
| 262 | /* set phy-handle property in board file */ | |
| 263 | }; | |
| 264 | }; | |
| 265 | ||
| 266 | eth1: ethernet-controller@76000 { | |
| 267 | compatible = "marvell,kirkwood-eth"; | |
| 268 | #address-cells = <1>; | |
| 269 | #size-cells = <0>; | |
| 270 | reg = <0x76000 0x4000>; | |
| 271 | clocks = <&gate_clk 19>; | |
| 272 | marvell,tx-checksum-limit = <1600>; | |
| 273 | status = "disabled"; | |
| 274 | ||
| 275 | ethernet1-port@0 { | |
| 276 | device_type = "network"; | |
| 277 | compatible = "marvell,kirkwood-eth-port"; | |
| 278 | reg = <0>; | |
| 279 | interrupts = <15>; | |
| 280 | /* overwrite MAC address in bootloader */ | |
| 281 | local-mac-address = [00 00 00 00 00 00]; | |
| 282 | /* set phy-handle property in board file */ | |
| 283 | }; | |
| 284 | }; | |
| 163f2cea JC |
285 | }; |
| 286 | }; |