Commit | Line | Data |
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e04920d9 RS |
1 | /* |
2 | * NXP LPC32xx SoC | |
3 | * | |
4 | * Copyright 2012 Roland Stigge <stigge@antcom.de> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
1a24edd2 | 14 | #include "skeleton.dtsi" |
e04920d9 | 15 | |
93898eb7 | 16 | #include <dt-bindings/clock/lpc32xx-clock.h> |
b715802f | 17 | #include <dt-bindings/interrupt-controller/irq.h> |
93898eb7 | 18 | |
e04920d9 RS |
19 | / { |
20 | compatible = "nxp,lpc3220"; | |
21 | interrupt-parent = <&mic>; | |
22 | ||
23 | cpus { | |
246d8fc3 | 24 | #address-cells = <1>; |
73158b77 LP |
25 | #size-cells = <0>; |
26 | ||
246d8fc3 | 27 | cpu@0 { |
73158b77 LP |
28 | compatible = "arm,arm926ej-s"; |
29 | device_type = "cpu"; | |
246d8fc3 | 30 | reg = <0x0>; |
e04920d9 RS |
31 | }; |
32 | }; | |
33 | ||
ef5f885e VZ |
34 | clocks { |
35 | xtal_32k: xtal_32k { | |
36 | compatible = "fixed-clock"; | |
37 | #clock-cells = <0>; | |
38 | clock-frequency = <32768>; | |
39 | clock-output-names = "xtal_32k"; | |
40 | }; | |
41 | ||
42 | xtal: xtal { | |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <13000000>; | |
46 | clock-output-names = "xtal"; | |
47 | }; | |
48 | }; | |
49 | ||
e04920d9 RS |
50 | ahb { |
51 | #address-cells = <1>; | |
52 | #size-cells = <1>; | |
53 | compatible = "simple-bus"; | |
f83ee67f VZ |
54 | ranges = <0x20000000 0x20000000 0x30000000>, |
55 | <0xe0000000 0xe0000000 0x04000000>; | |
e04920d9 RS |
56 | |
57 | /* | |
58 | * Enable either SLC or MLC | |
59 | */ | |
60 | slc: flash@20020000 { | |
61 | compatible = "nxp,lpc3220-slc"; | |
62 | reg = <0x20020000 0x1000>; | |
93898eb7 | 63 | clocks = <&clk LPC32XX_CLK_SLC>; |
cb85a9e5 | 64 | status = "disabled"; |
e04920d9 RS |
65 | }; |
66 | ||
6d1c3e93 | 67 | mlc: flash@200a8000 { |
e04920d9 | 68 | compatible = "nxp,lpc3220-mlc"; |
6d1c3e93 | 69 | reg = <0x200a8000 0x11000>; |
b715802f | 70 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 | 71 | clocks = <&clk LPC32XX_CLK_MLC>; |
cb85a9e5 | 72 | status = "disabled"; |
e04920d9 RS |
73 | }; |
74 | ||
25de7c96 | 75 | dma: dma@31000000 { |
e04920d9 RS |
76 | compatible = "arm,pl080", "arm,primecell"; |
77 | reg = <0x31000000 0x1000>; | |
b715802f | 78 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 VZ |
79 | clocks = <&clk LPC32XX_CLK_DMA>; |
80 | clock-names = "apb_pclk"; | |
e04920d9 RS |
81 | }; |
82 | ||
aa29efb4 VZ |
83 | usb { |
84 | #address-cells = <1>; | |
85 | #size-cells = <1>; | |
86 | compatible = "simple-bus"; | |
87 | ranges = <0x0 0x31020000 0x00001000>; | |
e04920d9 | 88 | |
aa29efb4 VZ |
89 | /* |
90 | * Enable either ohci or usbd (gadget)! | |
91 | */ | |
92 | ohci: ohci@0 { | |
93 | compatible = "nxp,ohci-nxp", "usb-ohci"; | |
94 | reg = <0x0 0x300>; | |
b715802f | 95 | interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; |
865e9009 | 96 | clocks = <&usbclk LPC32XX_USB_CLK_HOST>; |
aa29efb4 VZ |
97 | status = "disabled"; |
98 | }; | |
99 | ||
100 | usbd: usbd@0 { | |
101 | compatible = "nxp,lpc3220-udc"; | |
102 | reg = <0x0 0x300>; | |
b715802f VZ |
103 | interrupts = <61 IRQ_TYPE_LEVEL_HIGH>, |
104 | <62 IRQ_TYPE_LEVEL_HIGH>, | |
105 | <60 IRQ_TYPE_LEVEL_HIGH>, | |
106 | <58 IRQ_TYPE_LEVEL_LOW>; | |
865e9009 | 107 | clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; |
aa29efb4 VZ |
108 | status = "disabled"; |
109 | }; | |
110 | ||
111 | i2cusb: i2c@300 { | |
112 | compatible = "nxp,pnx-i2c"; | |
113 | reg = <0x300 0x100>; | |
b715802f | 114 | interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; |
865e9009 | 115 | clocks = <&usbclk LPC32XX_USB_CLK_I2C>; |
aa29efb4 VZ |
116 | #address-cells = <1>; |
117 | #size-cells = <0>; | |
118 | pnx,timeout = <0x64>; | |
119 | }; | |
865e9009 VZ |
120 | |
121 | usbclk: clock-controller@f00 { | |
122 | compatible = "nxp,lpc3220-usb-clk"; | |
123 | reg = <0xf00 0x100>; | |
124 | #clock-cells = <1>; | |
125 | }; | |
e04920d9 RS |
126 | }; |
127 | ||
25de7c96 | 128 | clcd: clcd@31040000 { |
e04920d9 RS |
129 | compatible = "arm,pl110", "arm,primecell"; |
130 | reg = <0x31040000 0x1000>; | |
b715802f | 131 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 VZ |
132 | clocks = <&clk LPC32XX_CLK_LCD>; |
133 | clock-names = "apb_pclk"; | |
cb85a9e5 | 134 | status = "disabled"; |
e04920d9 RS |
135 | }; |
136 | ||
137 | mac: ethernet@31060000 { | |
138 | compatible = "nxp,lpc-eth"; | |
139 | reg = <0x31060000 0x1000>; | |
b715802f | 140 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 | 141 | clocks = <&clk LPC32XX_CLK_MAC>; |
e04920d9 RS |
142 | }; |
143 | ||
f83ee67f VZ |
144 | emc: memory-controller@31080000 { |
145 | compatible = "arm,pl175", "arm,primecell"; | |
146 | reg = <0x31080000 0x1000>; | |
93898eb7 VZ |
147 | clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; |
148 | clock-names = "mpmcclk", "apb_pclk"; | |
f83ee67f VZ |
149 | #address-cells = <1>; |
150 | #size-cells = <1>; | |
151 | ||
152 | ranges = <0 0xe0000000 0x01000000>, | |
153 | <1 0xe1000000 0x01000000>, | |
154 | <2 0xe2000000 0x01000000>, | |
155 | <3 0xe3000000 0x01000000>; | |
156 | status = "disabled"; | |
157 | }; | |
158 | ||
e04920d9 RS |
159 | apb { |
160 | #address-cells = <1>; | |
161 | #size-cells = <1>; | |
162 | compatible = "simple-bus"; | |
163 | ranges = <0x20000000 0x20000000 0x30000000>; | |
164 | ||
165 | ssp0: ssp@20084000 { | |
166 | compatible = "arm,pl022", "arm,primecell"; | |
167 | reg = <0x20084000 0x1000>; | |
b715802f | 168 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 VZ |
169 | clocks = <&clk LPC32XX_CLK_SSP0>; |
170 | clock-names = "apb_pclk"; | |
e04920d9 RS |
171 | }; |
172 | ||
173 | spi1: spi@20088000 { | |
174 | compatible = "nxp,lpc3220-spi"; | |
175 | reg = <0x20088000 0x1000>; | |
176 | }; | |
177 | ||
178 | ssp1: ssp@2008c000 { | |
179 | compatible = "arm,pl022", "arm,primecell"; | |
180 | reg = <0x2008c000 0x1000>; | |
b715802f | 181 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 VZ |
182 | clocks = <&clk LPC32XX_CLK_SSP1>; |
183 | clock-names = "apb_pclk"; | |
e04920d9 RS |
184 | }; |
185 | ||
186 | spi2: spi@20090000 { | |
187 | compatible = "nxp,lpc3220-spi"; | |
188 | reg = <0x20090000 0x1000>; | |
189 | }; | |
190 | ||
191 | i2s0: i2s@20094000 { | |
192 | compatible = "nxp,lpc3220-i2s"; | |
193 | reg = <0x20094000 0x1000>; | |
194 | }; | |
195 | ||
25de7c96 | 196 | sd: sd@20098000 { |
2c7fa286 | 197 | compatible = "arm,pl18x", "arm,primecell"; |
e04920d9 | 198 | reg = <0x20098000 0x1000>; |
b715802f VZ |
199 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, |
200 | <13 IRQ_TYPE_LEVEL_HIGH>; | |
93898eb7 VZ |
201 | clocks = <&clk LPC32XX_CLK_SD>; |
202 | clock-names = "apb_pclk"; | |
2c7fa286 | 203 | status = "disabled"; |
e04920d9 RS |
204 | }; |
205 | ||
206 | i2s1: i2s@2009C000 { | |
207 | compatible = "nxp,lpc3220-i2s"; | |
208 | reg = <0x2009C000 0x1000>; | |
209 | }; | |
210 | ||
c70426f1 RS |
211 | /* UART5 first since it is the default console, ttyS0 */ |
212 | uart5: serial@40090000 { | |
213 | /* actually, ns16550a w/ 64 byte fifos! */ | |
214 | compatible = "nxp,lpc3220-uart"; | |
215 | reg = <0x40090000 0x1000>; | |
b715802f | 216 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 217 | reg-shift = <2>; |
93898eb7 | 218 | clocks = <&clk LPC32XX_CLK_UART5>; |
c70426f1 RS |
219 | status = "disabled"; |
220 | }; | |
221 | ||
e04920d9 | 222 | uart3: serial@40080000 { |
c70426f1 | 223 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 224 | reg = <0x40080000 0x1000>; |
b715802f | 225 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 226 | reg-shift = <2>; |
93898eb7 | 227 | clocks = <&clk LPC32XX_CLK_UART3>; |
c70426f1 | 228 | status = "disabled"; |
e04920d9 RS |
229 | }; |
230 | ||
231 | uart4: serial@40088000 { | |
c70426f1 | 232 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 233 | reg = <0x40088000 0x1000>; |
b715802f | 234 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 235 | reg-shift = <2>; |
93898eb7 | 236 | clocks = <&clk LPC32XX_CLK_UART4>; |
c70426f1 | 237 | status = "disabled"; |
e04920d9 RS |
238 | }; |
239 | ||
240 | uart6: serial@40098000 { | |
c70426f1 | 241 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 242 | reg = <0x40098000 0x1000>; |
b715802f | 243 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 244 | reg-shift = <2>; |
93898eb7 | 245 | clocks = <&clk LPC32XX_CLK_UART6>; |
c70426f1 | 246 | status = "disabled"; |
e04920d9 RS |
247 | }; |
248 | ||
249 | i2c1: i2c@400A0000 { | |
250 | compatible = "nxp,pnx-i2c"; | |
251 | reg = <0x400A0000 0x100>; | |
b715802f | 252 | interrupts = <51 IRQ_TYPE_LEVEL_LOW>; |
e04920d9 RS |
253 | #address-cells = <1>; |
254 | #size-cells = <0>; | |
255 | pnx,timeout = <0x64>; | |
93898eb7 | 256 | clocks = <&clk LPC32XX_CLK_I2C1>; |
e04920d9 RS |
257 | }; |
258 | ||
259 | i2c2: i2c@400A8000 { | |
260 | compatible = "nxp,pnx-i2c"; | |
261 | reg = <0x400A8000 0x100>; | |
b715802f | 262 | interrupts = <50 IRQ_TYPE_LEVEL_LOW>; |
e04920d9 RS |
263 | #address-cells = <1>; |
264 | #size-cells = <0>; | |
265 | pnx,timeout = <0x64>; | |
93898eb7 | 266 | clocks = <&clk LPC32XX_CLK_I2C2>; |
e04920d9 RS |
267 | }; |
268 | ||
b7d41c93 AB |
269 | mpwm: mpwm@400E8000 { |
270 | compatible = "nxp,lpc3220-motor-pwm"; | |
271 | reg = <0x400E8000 0x78>; | |
272 | status = "disabled"; | |
273 | #pwm-cells = <2>; | |
274 | }; | |
e04920d9 RS |
275 | }; |
276 | ||
277 | fab { | |
278 | #address-cells = <1>; | |
279 | #size-cells = <1>; | |
280 | compatible = "simple-bus"; | |
281 | ranges = <0x20000000 0x20000000 0x30000000>; | |
282 | ||
fe86131f VZ |
283 | /* System Control Block */ |
284 | scb { | |
285 | compatible = "simple-bus"; | |
286 | ranges = <0x0 0x040004000 0x00001000>; | |
287 | #address-cells = <1>; | |
288 | #size-cells = <1>; | |
289 | ||
290 | clk: clock-controller@0 { | |
291 | compatible = "nxp,lpc3220-clk"; | |
292 | reg = <0x00 0x114>; | |
293 | #clock-cells = <1>; | |
294 | ||
295 | clocks = <&xtal_32k>, <&xtal>; | |
296 | clock-names = "xtal_32k", "xtal"; | |
297 | }; | |
298 | }; | |
299 | ||
e04920d9 RS |
300 | /* |
301 | * MIC Interrupt controller includes: | |
302 | * MIC @40008000 | |
303 | * SIC1 @4000C000 | |
304 | * SIC2 @40010000 | |
305 | */ | |
306 | mic: interrupt-controller@40008000 { | |
307 | compatible = "nxp,lpc3220-mic"; | |
308 | interrupt-controller; | |
309 | reg = <0x40008000 0xC000>; | |
310 | #interrupt-cells = <2>; | |
311 | }; | |
312 | ||
313 | uart1: serial@40014000 { | |
ac5ced91 | 314 | compatible = "nxp,lpc3220-hsuart"; |
e04920d9 | 315 | reg = <0x40014000 0x1000>; |
b715802f | 316 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; |
ac5ced91 | 317 | status = "disabled"; |
e04920d9 RS |
318 | }; |
319 | ||
320 | uart2: serial@40018000 { | |
ac5ced91 | 321 | compatible = "nxp,lpc3220-hsuart"; |
e04920d9 | 322 | reg = <0x40018000 0x1000>; |
b715802f | 323 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; |
ac5ced91 | 324 | status = "disabled"; |
e04920d9 RS |
325 | }; |
326 | ||
ac5ced91 RS |
327 | uart7: serial@4001c000 { |
328 | compatible = "nxp,lpc3220-hsuart"; | |
329 | reg = <0x4001c000 0x1000>; | |
b715802f | 330 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; |
ac5ced91 | 331 | status = "disabled"; |
e04920d9 RS |
332 | }; |
333 | ||
25de7c96 | 334 | rtc: rtc@40024000 { |
e04920d9 RS |
335 | compatible = "nxp,lpc3220-rtc"; |
336 | reg = <0x40024000 0x1000>; | |
b715802f | 337 | interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 | 338 | clocks = <&clk LPC32XX_CLK_RTC>; |
e04920d9 RS |
339 | }; |
340 | ||
341 | gpio: gpio@40028000 { | |
342 | compatible = "nxp,lpc3220-gpio"; | |
343 | reg = <0x40028000 0x1000>; | |
a035254a RS |
344 | gpio-controller; |
345 | #gpio-cells = <3>; /* bank, pin, flags */ | |
e04920d9 RS |
346 | }; |
347 | ||
c1aa7007 VZ |
348 | timer4: timer@4002C000 { |
349 | compatible = "nxp,lpc3220-timer"; | |
350 | reg = <0x4002C000 0x1000>; | |
b715802f | 351 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
352 | clocks = <&clk LPC32XX_CLK_TIMER4>; |
353 | clock-names = "timerclk"; | |
c1aa7007 VZ |
354 | status = "disabled"; |
355 | }; | |
356 | ||
357 | timer5: timer@40030000 { | |
358 | compatible = "nxp,lpc3220-timer"; | |
359 | reg = <0x40030000 0x1000>; | |
b715802f | 360 | interrupts = <4 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
361 | clocks = <&clk LPC32XX_CLK_TIMER5>; |
362 | clock-names = "timerclk"; | |
c1aa7007 VZ |
363 | status = "disabled"; |
364 | }; | |
365 | ||
25de7c96 | 366 | watchdog: watchdog@4003C000 { |
e04920d9 RS |
367 | compatible = "nxp,pnx4008-wdt"; |
368 | reg = <0x4003C000 0x1000>; | |
93898eb7 | 369 | clocks = <&clk LPC32XX_CLK_WDOG>; |
e04920d9 RS |
370 | }; |
371 | ||
c1aa7007 VZ |
372 | timer0: timer@40044000 { |
373 | compatible = "nxp,lpc3220-timer"; | |
374 | reg = <0x40044000 0x1000>; | |
93898eb7 VZ |
375 | clocks = <&clk LPC32XX_CLK_TIMER0>; |
376 | clock-names = "timerclk"; | |
b715802f | 377 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; |
c1aa7007 VZ |
378 | }; |
379 | ||
e04920d9 RS |
380 | /* |
381 | * TSC vs. ADC: Since those two share the same | |
382 | * hardware, you need to choose from one of the | |
383 | * following two and do 'status = "okay";' for one of | |
384 | * them | |
385 | */ | |
386 | ||
25de7c96 | 387 | adc: adc@40048000 { |
e04920d9 RS |
388 | compatible = "nxp,lpc3220-adc"; |
389 | reg = <0x40048000 0x1000>; | |
b715802f | 390 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 | 391 | clocks = <&clk LPC32XX_CLK_ADC>; |
cb85a9e5 | 392 | status = "disabled"; |
e04920d9 RS |
393 | }; |
394 | ||
25de7c96 | 395 | tsc: tsc@40048000 { |
e04920d9 RS |
396 | compatible = "nxp,lpc3220-tsc"; |
397 | reg = <0x40048000 0x1000>; | |
b715802f | 398 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 | 399 | clocks = <&clk LPC32XX_CLK_ADC>; |
cb85a9e5 | 400 | status = "disabled"; |
e04920d9 RS |
401 | }; |
402 | ||
c1aa7007 VZ |
403 | timer1: timer@4004C000 { |
404 | compatible = "nxp,lpc3220-timer"; | |
405 | reg = <0x4004C000 0x1000>; | |
b715802f | 406 | interrupts = <17 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
407 | clocks = <&clk LPC32XX_CLK_TIMER1>; |
408 | clock-names = "timerclk"; | |
c1aa7007 VZ |
409 | }; |
410 | ||
25de7c96 | 411 | key: key@40050000 { |
e04920d9 RS |
412 | compatible = "nxp,lpc3220-key"; |
413 | reg = <0x40050000 0x1000>; | |
b715802f | 414 | interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; |
a6d1be0e | 415 | status = "disabled"; |
e04920d9 RS |
416 | }; |
417 | ||
c1aa7007 VZ |
418 | timer2: timer@40058000 { |
419 | compatible = "nxp,lpc3220-timer"; | |
420 | reg = <0x40058000 0x1000>; | |
b715802f | 421 | interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
422 | clocks = <&clk LPC32XX_CLK_TIMER2>; |
423 | clock-names = "timerclk"; | |
c1aa7007 VZ |
424 | status = "disabled"; |
425 | }; | |
426 | ||
2a6c6563 | 427 | pwm1: pwm@4005C000 { |
de639854 | 428 | compatible = "nxp,lpc3220-pwm"; |
2a6c6563 | 429 | reg = <0x4005C000 0x4>; |
93898eb7 | 430 | clocks = <&clk LPC32XX_CLK_PWM1>; |
2a6c6563 VZ |
431 | status = "disabled"; |
432 | }; | |
433 | ||
434 | pwm2: pwm@4005C004 { | |
435 | compatible = "nxp,lpc3220-pwm"; | |
436 | reg = <0x4005C004 0x4>; | |
93898eb7 | 437 | clocks = <&clk LPC32XX_CLK_PWM2>; |
de639854 APS |
438 | status = "disabled"; |
439 | }; | |
c1aa7007 VZ |
440 | |
441 | timer3: timer@40060000 { | |
442 | compatible = "nxp,lpc3220-timer"; | |
443 | reg = <0x40060000 0x1000>; | |
b715802f | 444 | interrupts = <19 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
445 | clocks = <&clk LPC32XX_CLK_TIMER3>; |
446 | clock-names = "timerclk"; | |
c1aa7007 VZ |
447 | status = "disabled"; |
448 | }; | |
e04920d9 RS |
449 | }; |
450 | }; | |
451 | }; |