[deliverable/linux.git] / arch / arm / boot / dts / lpc32xx.dtsi

/*
 * NXP LPC32xx SoC
 *
 * Copyright 2012 Roland Stigge <stigge@antcom.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"

#include <dt-bindings/clock/lpc32xx-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "nxp,lpc3220";
	interrupt-parent = <&mic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0x0>;
		};
	};

	clocks {
		xtal_32k: xtal_32k {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "xtal_32k";
		};

		xtal: xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <13000000>;
			clock-output-names = "xtal";
		};
	};

	ahb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0x20000000 0x20000000 0x30000000>,
			 <0xe0000000 0xe0000000 0x04000000>;

		/*
		 * Enable either SLC or MLC
		 */
		slc: flash@20020000 {
			compatible = "nxp,lpc3220-slc";
			reg = <0x20020000 0x1000>;
			clocks = <&clk LPC32XX_CLK_SLC>;
			status = "disabled";
		};

		mlc: flash@200a8000 {
			compatible = "nxp,lpc3220-mlc";
			reg = <0x200a8000 0x11000>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk LPC32XX_CLK_MLC>;
			status = "disabled";
		};

		dma: dma@31000000 {
			compatible = "arm,pl080", "arm,primecell";
			reg = <0x31000000 0x1000>;
			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk LPC32XX_CLK_DMA>;
			clock-names = "apb_pclk";
		};

		usb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x31020000 0x00001000>;

			/*
			 * Enable either ohci or usbd (gadget)!
			 */
			ohci: ohci@0 {
				compatible = "nxp,ohci-nxp", "usb-ohci";
				reg = <0x0 0x300>;
				interrupt-parent = <&sic1>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
				status = "disabled";
			};

			usbd: usbd@0 {
				compatible = "nxp,lpc3220-udc";
				reg = <0x0 0x300>;
				interrupt-parent = <&sic1>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
					     <30 IRQ_TYPE_LEVEL_HIGH>,
					     <28 IRQ_TYPE_LEVEL_HIGH>,
					     <26 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
				status = "disabled";
			};

			i2cusb: i2c@300 {
				compatible = "nxp,pnx-i2c";
				reg = <0x300 0x100>;
				interrupt-parent = <&sic1>;
				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
				#address-cells = <1>;
				#size-cells = <0>;
				pnx,timeout = <0x64>;
			};

			usbclk: clock-controller@f00 {
				compatible = "nxp,lpc3220-usb-clk";
				reg = <0xf00 0x100>;
				#clock-cells = <1>;
			};
		};

		clcd: clcd@31040000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0x31040000 0x1000>;
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk LPC32XX_CLK_LCD>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		mac: ethernet@31060000 {
			compatible = "nxp,lpc-eth";
			reg = <0x31060000 0x1000>;
			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk LPC32XX_CLK_MAC>;
		};

		emc: memory-controller@31080000 {
			compatible = "arm,pl175", "arm,primecell";
			reg = <0x31080000 0x1000>;
			clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
			clock-names = "mpmcclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe0000000 0x01000000>,
				 <1 0xe1000000 0x01000000>,
				 <2 0xe2000000 0x01000000>,
				 <3 0xe3000000 0x01000000>;
			status = "disabled";
		};

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x20000000 0x20000000 0x30000000>;

			/*
			 * ssp0 and spi1 are shared pins;
			 * enable one in your board dts, as needed.
			 */
			ssp0: ssp@20084000 {
				compatible = "arm,pl022", "arm,primecell";
				reg = <0x20084000 0x1000>;
				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk LPC32XX_CLK_SSP0>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			spi1: spi@20088000 {
				compatible = "nxp,lpc3220-spi";
				reg = <0x20088000 0x1000>;
				clocks = <&clk LPC32XX_CLK_SPI1>;
				status = "disabled";
			};

			/*
			 * ssp1 and spi2 are shared pins;
			 * enable one in your board dts, as needed.
			 */
			ssp1: ssp@2008c000 {
				compatible = "arm,pl022", "arm,primecell";
				reg = <0x2008c000 0x1000>;
				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk LPC32XX_CLK_SSP1>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			spi2: spi@20090000 {
				compatible = "nxp,lpc3220-spi";
				reg = <0x20090000 0x1000>;
				clocks = <&clk LPC32XX_CLK_SPI2>;
				status = "disabled";
			};

			i2s0: i2s@20094000 {
				compatible = "nxp,lpc3220-i2s";
				reg = <0x20094000 0x1000>;
			};

			sd: sd@20098000 {
				compatible = "arm,pl18x", "arm,primecell";
				reg = <0x20098000 0x1000>;
				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
					     <13 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk LPC32XX_CLK_SD>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			i2s1: i2s@2009C000 {
				compatible = "nxp,lpc3220-i2s";
				reg = <0x2009C000 0x1000>;
			};

			/* UART5 first since it is the default console, ttyS0 */
			uart5: serial@40090000 {
				/* actually, ns16550a w/ 64 byte fifos! */
				compatible = "nxp,lpc3220-uart";
				reg = <0x40090000 0x1000>;
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				clocks = <&clk LPC32XX_CLK_UART5>;
				status = "disabled";
			};

			uart3: serial@40080000 {
				compatible = "nxp,lpc3220-uart";
				reg = <0x40080000 0x1000>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				clocks = <&clk LPC32XX_CLK_UART3>;
				status = "disabled";
			};

			uart4: serial@40088000 {
				compatible = "nxp,lpc3220-uart";
				reg = <0x40088000 0x1000>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				clocks = <&clk LPC32XX_CLK_UART4>;
				status = "disabled";
			};

			uart6: serial@40098000 {
				compatible = "nxp,lpc3220-uart";
				reg = <0x40098000 0x1000>;
				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				clocks = <&clk LPC32XX_CLK_UART6>;
				status = "disabled";
			};

			i2c1: i2c@400A0000 {
				compatible = "nxp,pnx-i2c";
				reg = <0x400A0000 0x100>;
				interrupt-parent = <&sic1>;
				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
				#address-cells = <1>;
				#size-cells = <0>;
				pnx,timeout = <0x64>;
				clocks = <&clk LPC32XX_CLK_I2C1>;
			};

			i2c2: i2c@400A8000 {
				compatible = "nxp,pnx-i2c";
				reg = <0x400A8000 0x100>;
				interrupt-parent = <&sic1>;
				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
				#address-cells = <1>;
				#size-cells = <0>;
				pnx,timeout = <0x64>;
				clocks = <&clk LPC32XX_CLK_I2C2>;
			};

			mpwm: mpwm@400E8000 {
				compatible = "nxp,lpc3220-motor-pwm";
				reg = <0x400E8000 0x78>;
				status = "disabled";
				#pwm-cells = <2>;
			};
		};

		fab {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x20000000 0x20000000 0x30000000>;

			/* System Control Block */
			scb {
				compatible = "simple-bus";
				ranges = <0x0 0x040004000 0x00001000>;
				#address-cells = <1>;
				#size-cells = <1>;

				clk: clock-controller@0 {
					compatible = "nxp,lpc3220-clk";
					reg = <0x00 0x114>;
					#clock-cells = <1>;

					clocks = <&xtal_32k>, <&xtal>;
					clock-names = "xtal_32k", "xtal";

					assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
					assigned-clock-rates = <208000000>;
				};
			};

			mic: interrupt-controller@40008000 {
				compatible = "nxp,lpc3220-mic";
				reg = <0x40008000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			sic1: interrupt-controller@4000c000 {
				compatible = "nxp,lpc3220-sic";
				reg = <0x4000c000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&mic>;
				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
					     <30 IRQ_TYPE_LEVEL_LOW>;
				};

			sic2: interrupt-controller@40010000 {
				compatible = "nxp,lpc3220-sic";
				reg = <0x40010000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&mic>;
				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
					     <31 IRQ_TYPE_LEVEL_LOW>;
			};

			uart1: serial@40014000 {
				compatible = "nxp,lpc3220-hsuart";
				reg = <0x40014000 0x1000>;
				interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			uart2: serial@40018000 {
				compatible = "nxp,lpc3220-hsuart";
				reg = <0x40018000 0x1000>;
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			uart7: serial@4001c000 {
				compatible = "nxp,lpc3220-hsuart";
				reg = <0x4001c000 0x1000>;
				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			rtc: rtc@40024000 {
				compatible = "nxp,lpc3220-rtc";
				reg = <0x40024000 0x1000>;
				interrupt-parent = <&sic1>;
				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk LPC32XX_CLK_RTC>;
			};

			gpio: gpio@40028000 {
				compatible = "nxp,lpc3220-gpio";
				reg = <0x40028000 0x1000>;
				gpio-controller;
				#gpio-cells = <3>; /* bank, pin, flags */
			};

			timer4: timer@4002C000 {
				compatible = "nxp,lpc3220-timer";
				reg = <0x4002C000 0x1000>;
				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&clk LPC32XX_CLK_TIMER4>;
				clock-names = "timerclk";
				status = "disabled";
			};

			timer5: timer@40030000 {
				compatible = "nxp,lpc3220-timer";
				reg = <0x40030000 0x1000>;
				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&clk LPC32XX_CLK_TIMER5>;
				clock-names = "timerclk";
				status = "disabled";
			};

			watchdog: watchdog@4003C000 {
				compatible = "nxp,pnx4008-wdt";
				reg = <0x4003C000 0x1000>;
				clocks = <&clk LPC32XX_CLK_WDOG>;
			};

			timer0: timer@40044000 {
				compatible = "nxp,lpc3220-timer";
				reg = <0x40044000 0x1000>;
				clocks = <&clk LPC32XX_CLK_TIMER0>;
				clock-names = "timerclk";
				interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
			};

			/*
			 * TSC vs. ADC: Since those two share the same
			 * hardware, you need to choose from one of the
			 * following two and do 'status = "okay";' for one of
			 * them
			 */

			adc: adc@40048000 {
				compatible = "nxp,lpc3220-adc";
				reg = <0x40048000 0x1000>;
				interrupt-parent = <&sic1>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk LPC32XX_CLK_ADC>;
				status = "disabled";
			};

			tsc: tsc@40048000 {
				compatible = "nxp,lpc3220-tsc";
				reg = <0x40048000 0x1000>;
				interrupt-parent = <&sic1>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk LPC32XX_CLK_ADC>;
				status = "disabled";
			};

			timer1: timer@4004C000 {
				compatible = "nxp,lpc3220-timer";
				reg = <0x4004C000 0x1000>;
				interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&clk LPC32XX_CLK_TIMER1>;
				clock-names = "timerclk";
			};

			key: key@40050000 {
				compatible = "nxp,lpc3220-key";
				reg = <0x40050000 0x1000>;
				interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			timer2: timer@40058000 {
				compatible = "nxp,lpc3220-timer";
				reg = <0x40058000 0x1000>;
				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&clk LPC32XX_CLK_TIMER2>;
				clock-names = "timerclk";
				status = "disabled";
			};

			pwm1: pwm@4005C000 {
				compatible = "nxp,lpc3220-pwm";
				reg = <0x4005C000 0x4>;
				clocks = <&clk LPC32XX_CLK_PWM1>;
				status = "disabled";
			};

			pwm2: pwm@4005C004 {
				compatible = "nxp,lpc3220-pwm";
				reg = <0x4005C004 0x4>;
				clocks = <&clk LPC32XX_CLK_PWM2>;
				status = "disabled";
			};

			timer3: timer@40060000 {
				compatible = "nxp,lpc3220-timer";
				reg = <0x40060000 0x1000>;
				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&clk LPC32XX_CLK_TIMER3>;
				clock-names = "timerclk";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
e04920d9 RS	1	/*
	2	* NXP LPC32xx SoC
	3	*
	4	* Copyright 2012 Roland Stigge <stigge@antcom.de>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
1a24edd2	14	#include "skeleton.dtsi"
e04920d9	15
93898eb7	16	#include <dt-bindings/clock/lpc32xx-clock.h>
b715802f	17	#include <dt-bindings/interrupt-controller/irq.h>
93898eb7	18
e04920d9 RS	19	/ {
	20	compatible = "nxp,lpc3220";
	21	interrupt-parent = <&mic>;
	22
	23	cpus {
246d8fc3	24	#address-cells = <1>;
73158b77 LP	25	#size-cells = <0>;
73158b77 LP	26
246d8fc3	27	cpu@0 {
73158b77 LP	28	compatible = "arm,arm926ej-s";
73158b77 LP	29	device_type = "cpu";
246d8fc3	30	reg = <0x0>;
e04920d9 RS	31	};
	32	};
	33
ef5f885e VZ	34	clocks {
	35	xtal_32k: xtal_32k {
	36	compatible = "fixed-clock";
	37	#clock-cells = <0>;
	38	clock-frequency = <32768>;
	39	clock-output-names = "xtal_32k";
	40	};
	41
	42	xtal: xtal {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <13000000>;
	46	clock-output-names = "xtal";
	47	};
	48	};
	49
e04920d9 RS	50	ahb {
	51	#address-cells = <1>;
	52	#size-cells = <1>;
	53	compatible = "simple-bus";
f83ee67f VZ	54	ranges = <0x20000000 0x20000000 0x30000000>,
f83ee67f VZ	55	<0xe0000000 0xe0000000 0x04000000>;
e04920d9 RS	56
	57	/*
	58	* Enable either SLC or MLC
	59	*/
	60	slc: flash@20020000 {
	61	compatible = "nxp,lpc3220-slc";
	62	reg = <0x20020000 0x1000>;
93898eb7	63	clocks = <&clk LPC32XX_CLK_SLC>;
cb85a9e5	64	status = "disabled";
e04920d9 RS	65	};
e04920d9 RS	66
6d1c3e93	67	mlc: flash@200a8000 {
e04920d9	68	compatible = "nxp,lpc3220-mlc";
6d1c3e93	69	reg = <0x200a8000 0x11000>;
b715802f	70	interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
93898eb7	71	clocks = <&clk LPC32XX_CLK_MLC>;
cb85a9e5	72	status = "disabled";
e04920d9 RS	73	};
e04920d9 RS	74
25de7c96	75	dma: dma@31000000 {
e04920d9 RS	76	compatible = "arm,pl080", "arm,primecell";
e04920d9 RS	77	reg = <0x31000000 0x1000>;
b715802f	78	interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
93898eb7 VZ	79	clocks = <&clk LPC32XX_CLK_DMA>;
93898eb7 VZ	80	clock-names = "apb_pclk";
e04920d9 RS	81	};
e04920d9 RS	82
aa29efb4 VZ	83	usb {
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	compatible = "simple-bus";
	87	ranges = <0x0 0x31020000 0x00001000>;
e04920d9	88
aa29efb4 VZ	89	/*
	90	* Enable either ohci or usbd (gadget)!
	91	*/
	92	ohci: ohci@0 {
	93	compatible = "nxp,ohci-nxp", "usb-ohci";
	94	reg = <0x0 0x300>;
9b8ad3fb VZ	95	interrupt-parent = <&sic1>;
9b8ad3fb VZ	96	interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
865e9009	97	clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
aa29efb4 VZ	98	status = "disabled";
	99	};
	100
	101	usbd: usbd@0 {
	102	compatible = "nxp,lpc3220-udc";
	103	reg = <0x0 0x300>;
9b8ad3fb VZ	104	interrupt-parent = <&sic1>;
	105	interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
	106	<30 IRQ_TYPE_LEVEL_HIGH>,
	107	<28 IRQ_TYPE_LEVEL_HIGH>,
	108	<26 IRQ_TYPE_LEVEL_LOW>;
865e9009	109	clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
aa29efb4 VZ	110	status = "disabled";
	111	};
	112
	113	i2cusb: i2c@300 {
	114	compatible = "nxp,pnx-i2c";
	115	reg = <0x300 0x100>;
9b8ad3fb VZ	116	interrupt-parent = <&sic1>;
9b8ad3fb VZ	117	interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
865e9009	118	clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
aa29efb4 VZ	119	#address-cells = <1>;
	120	#size-cells = <0>;
	121	pnx,timeout = <0x64>;
	122	};
865e9009 VZ	123
	124	usbclk: clock-controller@f00 {
	125	compatible = "nxp,lpc3220-usb-clk";
	126	reg = <0xf00 0x100>;
	127	#clock-cells = <1>;
	128	};
e04920d9 RS	129	};
e04920d9 RS	130
25de7c96	131	clcd: clcd@31040000 {
e04920d9 RS	132	compatible = "arm,pl110", "arm,primecell";
e04920d9 RS	133	reg = <0x31040000 0x1000>;
b715802f	134	interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
93898eb7 VZ	135	clocks = <&clk LPC32XX_CLK_LCD>;
93898eb7 VZ	136	clock-names = "apb_pclk";
cb85a9e5	137	status = "disabled";
e04920d9 RS	138	};
	139
	140	mac: ethernet@31060000 {
	141	compatible = "nxp,lpc-eth";
	142	reg = <0x31060000 0x1000>;
b715802f	143	interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
93898eb7	144	clocks = <&clk LPC32XX_CLK_MAC>;
e04920d9 RS	145	};
e04920d9 RS	146
f83ee67f VZ	147	emc: memory-controller@31080000 {
	148	compatible = "arm,pl175", "arm,primecell";
	149	reg = <0x31080000 0x1000>;
93898eb7 VZ	150	clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
93898eb7 VZ	151	clock-names = "mpmcclk", "apb_pclk";
f83ee67f VZ	152	#address-cells = <1>;
	153	#size-cells = <1>;
	154
	155	ranges = <0 0xe0000000 0x01000000>,
	156	<1 0xe1000000 0x01000000>,
	157	<2 0xe2000000 0x01000000>,
	158	<3 0xe3000000 0x01000000>;
	159	status = "disabled";
	160	};
	161
e04920d9 RS	162	apb {
	163	#address-cells = <1>;
	164	#size-cells = <1>;
	165	compatible = "simple-bus";
	166	ranges = <0x20000000 0x20000000 0x30000000>;
	167
961212e3 SL	168	/*
	169	* ssp0 and spi1 are shared pins;
	170	* enable one in your board dts, as needed.
	171	*/
e04920d9 RS	172	ssp0: ssp@20084000 {
	173	compatible = "arm,pl022", "arm,primecell";
	174	reg = <0x20084000 0x1000>;
b715802f	175	interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
93898eb7 VZ	176	clocks = <&clk LPC32XX_CLK_SSP0>;
93898eb7 VZ	177	clock-names = "apb_pclk";
961212e3	178	status = "disabled";
e04920d9 RS	179	};
	180
	181	spi1: spi@20088000 {
	182	compatible = "nxp,lpc3220-spi";
	183	reg = <0x20088000 0x1000>;
73fdaa0f	184	clocks = <&clk LPC32XX_CLK_SPI1>;
961212e3	185	status = "disabled";
e04920d9 RS	186	};
e04920d9 RS	187
961212e3 SL	188	/*
	189	* ssp1 and spi2 are shared pins;
	190	* enable one in your board dts, as needed.
	191	*/
e04920d9 RS	192	ssp1: ssp@2008c000 {
	193	compatible = "arm,pl022", "arm,primecell";
	194	reg = <0x2008c000 0x1000>;
b715802f	195	interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
93898eb7 VZ	196	clocks = <&clk LPC32XX_CLK_SSP1>;
93898eb7 VZ	197	clock-names = "apb_pclk";
961212e3	198	status = "disabled";
e04920d9 RS	199	};
	200
	201	spi2: spi@20090000 {
	202	compatible = "nxp,lpc3220-spi";
	203	reg = <0x20090000 0x1000>;
73fdaa0f	204	clocks = <&clk LPC32XX_CLK_SPI2>;
961212e3	205	status = "disabled";
e04920d9 RS	206	};
	207
	208	i2s0: i2s@20094000 {
	209	compatible = "nxp,lpc3220-i2s";
	210	reg = <0x20094000 0x1000>;
	211	};
	212
25de7c96	213	sd: sd@20098000 {
2c7fa286	214	compatible = "arm,pl18x", "arm,primecell";
e04920d9	215	reg = <0x20098000 0x1000>;
b715802f VZ	216	interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
b715802f VZ	217	<13 IRQ_TYPE_LEVEL_HIGH>;
93898eb7 VZ	218	clocks = <&clk LPC32XX_CLK_SD>;
93898eb7 VZ	219	clock-names = "apb_pclk";
2c7fa286	220	status = "disabled";
e04920d9 RS	221	};
	222
	223	i2s1: i2s@2009C000 {
	224	compatible = "nxp,lpc3220-i2s";
	225	reg = <0x2009C000 0x1000>;
	226	};
	227
c70426f1 RS	228	/* UART5 first since it is the default console, ttyS0 */
	229	uart5: serial@40090000 {
	230	/* actually, ns16550a w/ 64 byte fifos! */
	231	compatible = "nxp,lpc3220-uart";
	232	reg = <0x40090000 0x1000>;
b715802f	233	interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
c70426f1	234	reg-shift = <2>;
93898eb7	235	clocks = <&clk LPC32XX_CLK_UART5>;
c70426f1 RS	236	status = "disabled";
	237	};
	238
e04920d9	239	uart3: serial@40080000 {
c70426f1	240	compatible = "nxp,lpc3220-uart";
e04920d9	241	reg = <0x40080000 0x1000>;
b715802f	242	interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
c70426f1	243	reg-shift = <2>;
93898eb7	244	clocks = <&clk LPC32XX_CLK_UART3>;
c70426f1	245	status = "disabled";
e04920d9 RS	246	};
	247
	248	uart4: serial@40088000 {
c70426f1	249	compatible = "nxp,lpc3220-uart";
e04920d9	250	reg = <0x40088000 0x1000>;
b715802f	251	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
c70426f1	252	reg-shift = <2>;
93898eb7	253	clocks = <&clk LPC32XX_CLK_UART4>;
c70426f1	254	status = "disabled";
e04920d9 RS	255	};
	256
	257	uart6: serial@40098000 {
c70426f1	258	compatible = "nxp,lpc3220-uart";
e04920d9	259	reg = <0x40098000 0x1000>;
b715802f	260	interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
c70426f1	261	reg-shift = <2>;
93898eb7	262	clocks = <&clk LPC32XX_CLK_UART6>;
c70426f1	263	status = "disabled";
e04920d9 RS	264	};
	265
	266	i2c1: i2c@400A0000 {
	267	compatible = "nxp,pnx-i2c";
	268	reg = <0x400A0000 0x100>;
9b8ad3fb VZ	269	interrupt-parent = <&sic1>;
9b8ad3fb VZ	270	interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
e04920d9 RS	271	#address-cells = <1>;
	272	#size-cells = <0>;
	273	pnx,timeout = <0x64>;
93898eb7	274	clocks = <&clk LPC32XX_CLK_I2C1>;
e04920d9 RS	275	};
	276
	277	i2c2: i2c@400A8000 {
	278	compatible = "nxp,pnx-i2c";
	279	reg = <0x400A8000 0x100>;
9b8ad3fb VZ	280	interrupt-parent = <&sic1>;
9b8ad3fb VZ	281	interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
e04920d9 RS	282	#address-cells = <1>;
	283	#size-cells = <0>;
	284	pnx,timeout = <0x64>;
93898eb7	285	clocks = <&clk LPC32XX_CLK_I2C2>;
e04920d9 RS	286	};
e04920d9 RS	287
b7d41c93 AB	288	mpwm: mpwm@400E8000 {
	289	compatible = "nxp,lpc3220-motor-pwm";
	290	reg = <0x400E8000 0x78>;
	291	status = "disabled";
	292	#pwm-cells = <2>;
	293	};
e04920d9 RS	294	};
	295
	296	fab {
	297	#address-cells = <1>;
	298	#size-cells = <1>;
	299	compatible = "simple-bus";
	300	ranges = <0x20000000 0x20000000 0x30000000>;
	301
fe86131f VZ	302	/* System Control Block */
	303	scb {
	304	compatible = "simple-bus";
	305	ranges = <0x0 0x040004000 0x00001000>;
	306	#address-cells = <1>;
	307	#size-cells = <1>;
	308
	309	clk: clock-controller@0 {
	310	compatible = "nxp,lpc3220-clk";
	311	reg = <0x00 0x114>;
	312	#clock-cells = <1>;
	313
	314	clocks = <&xtal_32k>, <&xtal>;
	315	clock-names = "xtal_32k", "xtal";
c17e9377 VZ	316
	317	assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
	318	assigned-clock-rates = <208000000>;
fe86131f VZ	319	};
	320	};
	321
e04920d9 RS	322	mic: interrupt-controller@40008000 {
e04920d9 RS	323	compatible = "nxp,lpc3220-mic";
9b8ad3fb	324	reg = <0x40008000 0x4000>;
e04920d9	325	interrupt-controller;
e04920d9 RS	326	#interrupt-cells = <2>;
	327	};
	328
9b8ad3fb VZ	329	sic1: interrupt-controller@4000c000 {
	330	compatible = "nxp,lpc3220-sic";
	331	reg = <0x4000c000 0x4000>;
	332	interrupt-controller;
	333	#interrupt-cells = <2>;
	334
	335	interrupt-parent = <&mic>;
	336	interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
	337	<30 IRQ_TYPE_LEVEL_LOW>;
	338	};
	339
	340	sic2: interrupt-controller@40010000 {
	341	compatible = "nxp,lpc3220-sic";
	342	reg = <0x40010000 0x4000>;
	343	interrupt-controller;
	344	#interrupt-cells = <2>;
	345
	346	interrupt-parent = <&mic>;
	347	interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
	348	<31 IRQ_TYPE_LEVEL_LOW>;
	349	};
	350
e04920d9	351	uart1: serial@40014000 {
ac5ced91	352	compatible = "nxp,lpc3220-hsuart";
e04920d9	353	reg = <0x40014000 0x1000>;
b715802f	354	interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
ac5ced91	355	status = "disabled";
e04920d9 RS	356	};
	357
	358	uart2: serial@40018000 {
ac5ced91	359	compatible = "nxp,lpc3220-hsuart";
e04920d9	360	reg = <0x40018000 0x1000>;
b715802f	361	interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
ac5ced91	362	status = "disabled";
e04920d9 RS	363	};
e04920d9 RS	364
ac5ced91 RS	365	uart7: serial@4001c000 {
	366	compatible = "nxp,lpc3220-hsuart";
	367	reg = <0x4001c000 0x1000>;
b715802f	368	interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
ac5ced91	369	status = "disabled";
e04920d9 RS	370	};
e04920d9 RS	371
25de7c96	372	rtc: rtc@40024000 {
e04920d9 RS	373	compatible = "nxp,lpc3220-rtc";
e04920d9 RS	374	reg = <0x40024000 0x1000>;
9b8ad3fb VZ	375	interrupt-parent = <&sic1>;
9b8ad3fb VZ	376	interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
93898eb7	377	clocks = <&clk LPC32XX_CLK_RTC>;
e04920d9 RS	378	};
	379
	380	gpio: gpio@40028000 {
	381	compatible = "nxp,lpc3220-gpio";
	382	reg = <0x40028000 0x1000>;
a035254a RS	383	gpio-controller;
a035254a RS	384	#gpio-cells = <3>; /* bank, pin, flags */
e04920d9 RS	385	};
e04920d9 RS	386
c1aa7007 VZ	387	timer4: timer@4002C000 {
	388	compatible = "nxp,lpc3220-timer";
	389	reg = <0x4002C000 0x1000>;
b715802f	390	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
93898eb7 VZ	391	clocks = <&clk LPC32XX_CLK_TIMER4>;
93898eb7 VZ	392	clock-names = "timerclk";
c1aa7007 VZ	393	status = "disabled";
	394	};
	395
	396	timer5: timer@40030000 {
	397	compatible = "nxp,lpc3220-timer";
	398	reg = <0x40030000 0x1000>;
b715802f	399	interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
93898eb7 VZ	400	clocks = <&clk LPC32XX_CLK_TIMER5>;
93898eb7 VZ	401	clock-names = "timerclk";
c1aa7007 VZ	402	status = "disabled";
	403	};
	404
25de7c96	405	watchdog: watchdog@4003C000 {
e04920d9 RS	406	compatible = "nxp,pnx4008-wdt";
e04920d9 RS	407	reg = <0x4003C000 0x1000>;
93898eb7	408	clocks = <&clk LPC32XX_CLK_WDOG>;
e04920d9 RS	409	};
e04920d9 RS	410
c1aa7007 VZ	411	timer0: timer@40044000 {
	412	compatible = "nxp,lpc3220-timer";
	413	reg = <0x40044000 0x1000>;
93898eb7 VZ	414	clocks = <&clk LPC32XX_CLK_TIMER0>;
93898eb7 VZ	415	clock-names = "timerclk";
b715802f	416	interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
c1aa7007 VZ	417	};
c1aa7007 VZ	418
e04920d9 RS	419	/*
	420	* TSC vs. ADC: Since those two share the same
	421	* hardware, you need to choose from one of the
	422	* following two and do 'status = "okay";' for one of
	423	* them
	424	*/
	425
25de7c96	426	adc: adc@40048000 {
e04920d9 RS	427	compatible = "nxp,lpc3220-adc";
e04920d9 RS	428	reg = <0x40048000 0x1000>;
9b8ad3fb VZ	429	interrupt-parent = <&sic1>;
9b8ad3fb VZ	430	interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
93898eb7	431	clocks = <&clk LPC32XX_CLK_ADC>;
cb85a9e5	432	status = "disabled";
e04920d9 RS	433	};
e04920d9 RS	434
25de7c96	435	tsc: tsc@40048000 {
e04920d9 RS	436	compatible = "nxp,lpc3220-tsc";
e04920d9 RS	437	reg = <0x40048000 0x1000>;
9b8ad3fb VZ	438	interrupt-parent = <&sic1>;
9b8ad3fb VZ	439	interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
93898eb7	440	clocks = <&clk LPC32XX_CLK_ADC>;
cb85a9e5	441	status = "disabled";
e04920d9 RS	442	};
e04920d9 RS	443
c1aa7007 VZ	444	timer1: timer@4004C000 {
	445	compatible = "nxp,lpc3220-timer";
	446	reg = <0x4004C000 0x1000>;
b715802f	447	interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
93898eb7 VZ	448	clocks = <&clk LPC32XX_CLK_TIMER1>;
93898eb7 VZ	449	clock-names = "timerclk";
c1aa7007 VZ	450	};
c1aa7007 VZ	451
25de7c96	452	key: key@40050000 {
e04920d9 RS	453	compatible = "nxp,lpc3220-key";
e04920d9 RS	454	reg = <0x40050000 0x1000>;
b715802f	455	interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
a6d1be0e	456	status = "disabled";
e04920d9 RS	457	};
e04920d9 RS	458
c1aa7007 VZ	459	timer2: timer@40058000 {
	460	compatible = "nxp,lpc3220-timer";
	461	reg = <0x40058000 0x1000>;
b715802f	462	interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
93898eb7 VZ	463	clocks = <&clk LPC32XX_CLK_TIMER2>;
93898eb7 VZ	464	clock-names = "timerclk";
c1aa7007 VZ	465	status = "disabled";
	466	};
	467
2a6c6563	468	pwm1: pwm@4005C000 {
de639854	469	compatible = "nxp,lpc3220-pwm";
2a6c6563	470	reg = <0x4005C000 0x4>;
93898eb7	471	clocks = <&clk LPC32XX_CLK_PWM1>;
2a6c6563 VZ	472	status = "disabled";
	473	};
	474
	475	pwm2: pwm@4005C004 {
	476	compatible = "nxp,lpc3220-pwm";
	477	reg = <0x4005C004 0x4>;
93898eb7	478	clocks = <&clk LPC32XX_CLK_PWM2>;
de639854 APS	479	status = "disabled";
de639854 APS	480	};
c1aa7007 VZ	481
	482	timer3: timer@40060000 {
	483	compatible = "nxp,lpc3220-timer";
	484	reg = <0x40060000 0x1000>;
b715802f	485	interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
93898eb7 VZ	486	clocks = <&clk LPC32XX_CLK_TIMER3>;
93898eb7 VZ	487	clock-names = "timerclk";
c1aa7007 VZ	488	status = "disabled";
c1aa7007 VZ	489	};
e04920d9 RS	490	};
	491	};
	492	};