[deliverable/linux.git] / arch / arm / boot / dts / mmp2.dtsi

/*
 *  Copyright (C) 2012 Marvell Technology Group Ltd.
 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  publishhed by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/marvell,mmp2.h>

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		i2c0 = &twsi1;
		i2c1 = &twsi2;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		L2: l2-cache {
			compatible = "marvell,tauros2-cache";
			marvell,tauros2-cache-features = <0x3>;
		};

		axi@d4200000 {	/* AXI */
			compatible = "mrvl,axi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xd4200000 0x00200000>;
			ranges;

			intc: interrupt-controller@d4282000 {
				compatible = "mrvl,mmp2-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0xd4282000 0x1000>;
				mrvl,intc-nr-irqs = <64>;
			};

			intcmux4: interrupt-controller@d4282150 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <4>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x150 0x4>, <0x168 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
			};

			intcmux5: interrupt-controller@d4282154 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <5>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x154 0x4>, <0x16c 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
				mrvl,clr-mfp-irq = <1>;
			};

			intcmux9: interrupt-controller@d4282180 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <9>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x180 0x4>, <0x17c 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <3>;
			};

			intcmux17: interrupt-controller@d4282158 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <17>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x158 0x4>, <0x170 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <5>;
			};

			intcmux35: interrupt-controller@d428215c {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <35>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x15c 0x4>, <0x174 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <15>;
			};

			intcmux51: interrupt-controller@d4282160 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <51>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x160 0x4>, <0x178 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
			};

			intcmux55: interrupt-controller@d4282188 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <55>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x188 0x4>, <0x184 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
			};
		};

		apb@d4000000 {	/* APB */
			compatible = "mrvl,apb-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xd4000000 0x00200000>;
			ranges;

			timer0: timer@d4014000 {
				compatible = "mrvl,mmp-timer";
				reg = <0xd4014000 0x100>;
				interrupts = <13>;
			};

			uart1: uart@d4030000 {
				compatible = "mrvl,mmp-uart";
				reg = <0xd4030000 0x1000>;
				interrupts = <27>;
				clocks = <&soc_clocks MMP2_CLK_UART0>;
				resets = <&soc_clocks MMP2_CLK_UART0>;
				status = "disabled";
			};

			uart2: uart@d4017000 {
				compatible = "mrvl,mmp-uart";
				reg = <0xd4017000 0x1000>;
				interrupts = <28>;
				clocks = <&soc_clocks MMP2_CLK_UART1>;
				resets = <&soc_clocks MMP2_CLK_UART1>;
				status = "disabled";
			};

			uart3: uart@d4018000 {
				compatible = "mrvl,mmp-uart";
				reg = <0xd4018000 0x1000>;
				interrupts = <24>;
				clocks = <&soc_clocks MMP2_CLK_UART2>;
				resets = <&soc_clocks MMP2_CLK_UART2>;
				status = "disabled";
			};

			uart4: uart@d4016000 {
				compatible = "mrvl,mmp-uart";
				reg = <0xd4016000 0x1000>;
				interrupts = <46>;
				clocks = <&soc_clocks MMP2_CLK_UART3>;
				resets = <&soc_clocks MMP2_CLK_UART3>;
				status = "disabled";
			};

			gpio@d4019000 {
				compatible = "marvell,mmp2-gpio";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xd4019000 0x1000>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <49>;
				interrupt-names = "gpio_mux";
				clocks = <&soc_clocks MMP2_CLK_GPIO>;
				resets = <&soc_clocks MMP2_CLK_GPIO>;
				interrupt-controller;
				#interrupt-cells = <1>;
				ranges;

				gcb0: gpio@d4019000 {
					reg = <0xd4019000 0x4>;
				};

				gcb1: gpio@d4019004 {
					reg = <0xd4019004 0x4>;
				};

				gcb2: gpio@d4019008 {
					reg = <0xd4019008 0x4>;
				};

				gcb3: gpio@d4019100 {
					reg = <0xd4019100 0x4>;
				};

				gcb4: gpio@d4019104 {
					reg = <0xd4019104 0x4>;
				};

				gcb5: gpio@d4019108 {
					reg = <0xd4019108 0x4>;
				};
			};

			twsi1: i2c@d4011000 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4011000 0x1000>;
				interrupts = <7>;
				clocks = <&soc_clocks MMP2_CLK_TWSI0>;
				resets = <&soc_clocks MMP2_CLK_TWSI0>;
				#address-cells = <1>;
				#size-cells = <0>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			twsi2: i2c@d4025000 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4025000 0x1000>;
				interrupts = <58>;
				clocks = <&soc_clocks MMP2_CLK_TWSI1>;
				resets = <&soc_clocks MMP2_CLK_TWSI1>;
				status = "disabled";
			};

			rtc: rtc@d4010000 {
				compatible = "mrvl,mmp-rtc";
				reg = <0xd4010000 0x1000>;
				interrupts = <1 0>;
				interrupt-names = "rtc 1Hz", "rtc alarm";
				interrupt-parent = <&intcmux5>;
				clocks = <&soc_clocks MMP2_CLK_RTC>;
				resets = <&soc_clocks MMP2_CLK_RTC>;
				status = "disabled";
			};
		};

		soc_clocks: clocks{
			compatible = "marvell,mmp2-clock";
			reg = <0xd4050000 0x1000>,
			      <0xd4282800 0x400>,
			      <0xd4015000 0x1000>;
			reg-names = "mpmu", "apmu", "apbc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};
	};
};
Commit	Line	Data
ff290fc3 HZ	1	/*
	2	* Copyright (C) 2012 Marvell Technology Group Ltd.
	3	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
	9
51454eb4	10	#include "skeleton.dtsi"
d41ef540	11	#include <dt-bindings/clock/marvell,mmp2.h>
ff290fc3 HZ	12
	13	/ {
	14	aliases {
	15	serial0 = &uart1;
	16	serial1 = &uart2;
	17	serial2 = &uart3;
	18	serial3 = &uart4;
	19	i2c0 = &twsi1;
	20	i2c1 = &twsi2;
	21	};
	22
	23	soc {
	24	#address-cells = <1>;
	25	#size-cells = <1>;
	26	compatible = "simple-bus";
	27	interrupt-parent = <&intc>;
	28	ranges;
	29
51931b37 HZ	30	L2: l2-cache {
	31	compatible = "marvell,tauros2-cache";
	32	marvell,tauros2-cache-features = <0x3>;
	33	};
	34
ff290fc3 HZ	35	axi@d4200000 { /* AXI */
	36	compatible = "mrvl,axi-bus", "simple-bus";
	37	#address-cells = <1>;
	38	#size-cells = <1>;
	39	reg = <0xd4200000 0x00200000>;
	40	ranges;
	41
	42	intc: interrupt-controller@d4282000 {
	43	compatible = "mrvl,mmp2-intc";
	44	interrupt-controller;
	45	#interrupt-cells = <1>;
	46	reg = <0xd4282000 0x1000>;
	47	mrvl,intc-nr-irqs = <64>;
	48	};
	49
58f1193e	50	intcmux4: interrupt-controller@d4282150 {
ff290fc3 HZ	51	compatible = "mrvl,mmp2-mux-intc";
	52	interrupts = <4>;
	53	interrupt-controller;
	54	#interrupt-cells = <1>;
	55	reg = <0x150 0x4>, <0x168 0x4>;
	56	reg-names = "mux status", "mux mask";
	57	mrvl,intc-nr-irqs = <2>;
	58	};
	59
	60	intcmux5: interrupt-controller@d4282154 {
	61	compatible = "mrvl,mmp2-mux-intc";
	62	interrupts = <5>;
	63	interrupt-controller;
	64	#interrupt-cells = <1>;
	65	reg = <0x154 0x4>, <0x16c 0x4>;
	66	reg-names = "mux status", "mux mask";
	67	mrvl,intc-nr-irqs = <2>;
	68	mrvl,clr-mfp-irq = <1>;
	69	};
	70
	71	intcmux9: interrupt-controller@d4282180 {
	72	compatible = "mrvl,mmp2-mux-intc";
	73	interrupts = <9>;
	74	interrupt-controller;
	75	#interrupt-cells = <1>;
	76	reg = <0x180 0x4>, <0x17c 0x4>;
	77	reg-names = "mux status", "mux mask";
	78	mrvl,intc-nr-irqs = <3>;
	79	};
	80
	81	intcmux17: interrupt-controller@d4282158 {
	82	compatible = "mrvl,mmp2-mux-intc";
	83	interrupts = <17>;
	84	interrupt-controller;
	85	#interrupt-cells = <1>;
	86	reg = <0x158 0x4>, <0x170 0x4>;
	87	reg-names = "mux status", "mux mask";
	88	mrvl,intc-nr-irqs = <5>;
	89	};
	90
	91	intcmux35: interrupt-controller@d428215c {
	92	compatible = "mrvl,mmp2-mux-intc";
	93	interrupts = <35>;
	94	interrupt-controller;
	95	#interrupt-cells = <1>;
	96	reg = <0x15c 0x4>, <0x174 0x4>;
	97	reg-names = "mux status", "mux mask";
	98	mrvl,intc-nr-irqs = <15>;
	99	};
	100
	101	intcmux51: interrupt-controller@d4282160 {
	102	compatible = "mrvl,mmp2-mux-intc";
	103	interrupts = <51>;
	104	interrupt-controller;
	105	#interrupt-cells = <1>;
	106	reg = <0x160 0x4>, <0x178 0x4>;
	107	reg-names = "mux status", "mux mask";
	108	mrvl,intc-nr-irqs = <2>;
	109	};
	110
	111	intcmux55: interrupt-controller@d4282188 {
	112	compatible = "mrvl,mmp2-mux-intc";
	113	interrupts = <55>;
	114	interrupt-controller;
115	#interrupt-cells = <1>;
116	reg = <0x188 0x4>, <0x184 0x4>;
117	reg-names = "mux status", "mux mask";
118	mrvl,intc-nr-irqs = <2>;
119	};
120	};
121
122	apb@d4000000 { /* APB */
123	compatible = "mrvl,apb-bus", "simple-bus";
124	#address-cells = <1>;
125	#size-cells = <1>;
126	reg = <0xd4000000 0x00200000>;
127	ranges;
128
129	timer0: timer@d4014000 {
130	compatible = "mrvl,mmp-timer";
131	reg = <0xd4014000 0x100>;
132	interrupts = <13>;
133	};
134
135	uart1: uart@d4030000 {
136	compatible = "mrvl,mmp-uart";
137	reg = <0xd4030000 0x1000>;
138	interrupts = <27>;
d41ef540 CX	139	clocks = <&soc_clocks MMP2_CLK_UART0>;
d41ef540 CX	140	resets = <&soc_clocks MMP2_CLK_UART0>;
ff290fc3 HZ	141	status = "disabled";
	142	};
	143
	144	uart2: uart@d4017000 {
	145	compatible = "mrvl,mmp-uart";
	146	reg = <0xd4017000 0x1000>;
	147	interrupts = <28>;
d41ef540 CX	148	clocks = <&soc_clocks MMP2_CLK_UART1>;
d41ef540 CX	149	resets = <&soc_clocks MMP2_CLK_UART1>;
ff290fc3 HZ	150	status = "disabled";
	151	};
	152
	153	uart3: uart@d4018000 {
	154	compatible = "mrvl,mmp-uart";
	155	reg = <0xd4018000 0x1000>;
	156	interrupts = <24>;
d41ef540 CX	157	clocks = <&soc_clocks MMP2_CLK_UART2>;
d41ef540 CX	158	resets = <&soc_clocks MMP2_CLK_UART2>;
ff290fc3 HZ	159	status = "disabled";
	160	};
	161
	162	uart4: uart@d4016000 {
	163	compatible = "mrvl,mmp-uart";
	164	reg = <0xd4016000 0x1000>;
	165	interrupts = <46>;
d41ef540 CX	166	clocks = <&soc_clocks MMP2_CLK_UART3>;
d41ef540 CX	167	resets = <&soc_clocks MMP2_CLK_UART3>;
ff290fc3 HZ	168	status = "disabled";
	169	};
	170
	171	gpio@d4019000 {
f8731174	172	compatible = "marvell,mmp2-gpio";
ff290fc3 HZ	173	#address-cells = <1>;
	174	#size-cells = <1>;
	175	reg = <0xd4019000 0x1000>;
	176	gpio-controller;
	177	#gpio-cells = <2>;
	178	interrupts = <49>;
	179	interrupt-names = "gpio_mux";
d41ef540 CX	180	clocks = <&soc_clocks MMP2_CLK_GPIO>;
d41ef540 CX	181	resets = <&soc_clocks MMP2_CLK_GPIO>;
ff290fc3 HZ	182	interrupt-controller;
	183	#interrupt-cells = <1>;
	184	ranges;
	185
	186	gcb0: gpio@d4019000 {
	187	reg = <0xd4019000 0x4>;
	188	};
	189
	190	gcb1: gpio@d4019004 {
	191	reg = <0xd4019004 0x4>;
	192	};
	193
	194	gcb2: gpio@d4019008 {
	195	reg = <0xd4019008 0x4>;
	196	};
	197
	198	gcb3: gpio@d4019100 {
	199	reg = <0xd4019100 0x4>;
	200	};
	201
	202	gcb4: gpio@d4019104 {
	203	reg = <0xd4019104 0x4>;
	204	};
	205
	206	gcb5: gpio@d4019108 {
	207	reg = <0xd4019108 0x4>;
	208	};
	209	};
	210
	211	twsi1: i2c@d4011000 {
	212	compatible = "mrvl,mmp-twsi";
	213	reg = <0xd4011000 0x1000>;
	214	interrupts = <7>;
d41ef540 CX	215	clocks = <&soc_clocks MMP2_CLK_TWSI0>;
d41ef540 CX	216	resets = <&soc_clocks MMP2_CLK_TWSI0>;
58f1193e QX	217	#address-cells = <1>;
58f1193e QX	218	#size-cells = <0>;
ff290fc3 HZ	219	mrvl,i2c-fast-mode;
	220	status = "disabled";
	221	};
	222
	223	twsi2: i2c@d4025000 {
	224	compatible = "mrvl,mmp-twsi";
	225	reg = <0xd4025000 0x1000>;
	226	interrupts = <58>;
d41ef540 CX	227	clocks = <&soc_clocks MMP2_CLK_TWSI1>;
d41ef540 CX	228	resets = <&soc_clocks MMP2_CLK_TWSI1>;
ff290fc3 HZ	229	status = "disabled";
	230	};
	231
	232	rtc: rtc@d4010000 {
	233	compatible = "mrvl,mmp-rtc";
	234	reg = <0xd4010000 0x1000>;
	235	interrupts = <1 0>;
	236	interrupt-names = "rtc 1Hz", "rtc alarm";
	237	interrupt-parent = <&intcmux5>;
d41ef540 CX	238	clocks = <&soc_clocks MMP2_CLK_RTC>;
d41ef540 CX	239	resets = <&soc_clocks MMP2_CLK_RTC>;
ff290fc3 HZ	240	status = "disabled";
	241	};
	242	};
d41ef540 CX	243
	244	soc_clocks: clocks{
	245	compatible = "marvell,mmp2-clock";
	246	reg = <0xd4050000 0x1000>,
	247	<0xd4282800 0x400>,
	248	<0xd4015000 0x1000>;
	249	reg-names = "mpmu", "apmu", "apbc";
	250	#clock-cells = <1>;
	251	#reset-cells = <1>;
	252	};
ff290fc3 HZ	253	};
ff290fc3 HZ	254	};