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31ac0d69 JC |
1 | /* |
2 | * Copyright (c) 2016 MediaTek Inc. | |
3 | * Author: John Crispin <blogic@openwrt.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <dt-bindings/interrupt-controller/irq.h> | |
16 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
17 | #include "skeleton64.dtsi" | |
18 | ||
19 | / { | |
20 | compatible = "mediatek,mt7623"; | |
21 | interrupt-parent = <&sysirq>; | |
22 | ||
23 | cpus { | |
24 | #address-cells = <1>; | |
25 | #size-cells = <0>; | |
27f99788 | 26 | enable-method = "mediatek,mt6589-smp"; |
31ac0d69 JC |
27 | |
28 | cpu@0 { | |
29 | device_type = "cpu"; | |
30 | compatible = "arm,cortex-a7"; | |
31 | reg = <0x0>; | |
32 | }; | |
33 | cpu@1 { | |
34 | device_type = "cpu"; | |
35 | compatible = "arm,cortex-a7"; | |
36 | reg = <0x1>; | |
37 | }; | |
38 | cpu@2 { | |
39 | device_type = "cpu"; | |
40 | compatible = "arm,cortex-a7"; | |
41 | reg = <0x2>; | |
42 | }; | |
43 | cpu@3 { | |
44 | device_type = "cpu"; | |
45 | compatible = "arm,cortex-a7"; | |
46 | reg = <0x3>; | |
47 | }; | |
48 | }; | |
49 | ||
50 | system_clk: dummy13m { | |
51 | compatible = "fixed-clock"; | |
52 | clock-frequency = <13000000>; | |
53 | #clock-cells = <0>; | |
54 | }; | |
55 | ||
56 | rtc_clk: dummy32k { | |
57 | compatible = "fixed-clock"; | |
58 | clock-frequency = <32000>; | |
59 | #clock-cells = <0>; | |
60 | }; | |
61 | ||
62 | uart_clk: dummy26m { | |
63 | compatible = "fixed-clock"; | |
64 | clock-frequency = <26000000>; | |
65 | #clock-cells = <0>; | |
66 | }; | |
67 | ||
68 | timer { | |
69 | compatible = "arm,armv7-timer"; | |
70 | interrupt-parent = <&gic>; | |
71 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
72 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
73 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
74 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
75 | }; | |
76 | ||
77 | watchdog: watchdog@10007000 { | |
78 | compatible = "mediatek,mt7623-wdt", | |
79 | "mediatek,mt6589-wdt"; | |
80 | reg = <0 0x10007000 0 0x100>; | |
81 | }; | |
82 | ||
83 | timer: timer@10008000 { | |
84 | compatible = "mediatek,mt7623-timer", | |
85 | "mediatek,mt6577-timer"; | |
86 | reg = <0 0x10008000 0 0x80>; | |
87 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; | |
88 | clocks = <&system_clk>, <&rtc_clk>; | |
89 | clock-names = "system-clk", "rtc-clk"; | |
90 | }; | |
91 | ||
92 | sysirq: interrupt-controller@10200100 { | |
93 | compatible = "mediatek,mt7623-sysirq", | |
94 | "mediatek,mt6577-sysirq"; | |
95 | interrupt-controller; | |
96 | #interrupt-cells = <3>; | |
97 | interrupt-parent = <&gic>; | |
98 | reg = <0 0x10200100 0 0x1c>; | |
99 | }; | |
100 | ||
101 | gic: interrupt-controller@10211000 { | |
102 | compatible = "arm,cortex-a7-gic"; | |
103 | interrupt-controller; | |
104 | #interrupt-cells = <3>; | |
105 | interrupt-parent = <&gic>; | |
106 | reg = <0 0x10211000 0 0x1000>, | |
107 | <0 0x10212000 0 0x1000>, | |
108 | <0 0x10214000 0 0x2000>, | |
109 | <0 0x10216000 0 0x2000>; | |
110 | }; | |
111 | ||
112 | uart0: serial@11002000 { | |
113 | compatible = "mediatek,mt7623-uart", | |
114 | "mediatek,mt6577-uart"; | |
115 | reg = <0 0x11002000 0 0x400>; | |
116 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; | |
117 | clocks = <&uart_clk>; | |
118 | status = "disabled"; | |
119 | }; | |
120 | ||
121 | uart1: serial@11003000 { | |
122 | compatible = "mediatek,mt7623-uart", | |
123 | "mediatek,mt6577-uart"; | |
124 | reg = <0 0x11003000 0 0x400>; | |
125 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; | |
126 | clocks = <&uart_clk>; | |
127 | status = "disabled"; | |
128 | }; | |
129 | ||
130 | uart2: serial@11004000 { | |
131 | compatible = "mediatek,mt7623-uart", | |
132 | "mediatek,mt6577-uart"; | |
133 | reg = <0 0x11004000 0 0x400>; | |
134 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; | |
135 | clocks = <&uart_clk>; | |
136 | status = "disabled"; | |
137 | }; | |
138 | ||
139 | uart3: serial@11005000 { | |
140 | compatible = "mediatek,mt7623-uart", | |
141 | "mediatek,mt6577-uart"; | |
142 | reg = <0 0x11005000 0 0x400>; | |
143 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; | |
144 | clocks = <&uart_clk>; | |
145 | status = "disabled"; | |
146 | }; | |
147 | }; |