[deliverable/linux.git] / arch / arm / boot / dts / omap2420-clocks.dtsi

/*
 * Device Tree Source for OMAP2420 clock data
 *
 * Copyright (C) 2014 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

&prcm_clocks {
	sys_clkout2_src_gate: sys_clkout2_src_gate {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <15>;
		reg = <0x0070>;
	};

	sys_clkout2_src_mux: sys_clkout2_src_mux {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
		ti,bit-shift = <8>;
		reg = <0x0070>;
	};

	sys_clkout2_src: sys_clkout2_src {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
	};

	sys_clkout2: sys_clkout2 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&sys_clkout2_src>;
		ti,bit-shift = <11>;
		ti,max-div = <64>;
		reg = <0x0070>;
		ti,index-power-of-two;
	};

	dsp_gate_ick: dsp_gate_ick {
		#clock-cells = <0>;
		compatible = "ti,composite-interface-clock";
		clocks = <&dsp_fck>;
		ti,bit-shift = <1>;
		reg = <0x0810>;
	};

	dsp_div_ick: dsp_div_ick {
		#clock-cells = <0>;
		compatible = "ti,composite-divider-clock";
		clocks = <&dsp_fck>;
		ti,bit-shift = <5>;
		ti,max-div = <3>;
		reg = <0x0840>;
		ti,index-starts-at-one;
	};

	dsp_ick: dsp_ick {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
	};

	iva1_gate_ifck: iva1_gate_ifck {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <10>;
		reg = <0x0800>;
	};

	iva1_div_ifck: iva1_div_ifck {
		#clock-cells = <0>;
		compatible = "ti,composite-divider-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <8>;
		reg = <0x0840>;
		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
	};

	iva1_ifck: iva1_ifck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
	};

	iva1_ifck_div: iva1_ifck_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&iva1_ifck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	iva1_mpu_int_ifck: iva1_mpu_int_ifck {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&iva1_ifck_div>;
		ti,bit-shift = <8>;
		reg = <0x0800>;
	};

	wdt3_ick: wdt3_ick {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <28>;
		reg = <0x0210>;
	};

	wdt3_fck: wdt3_fck {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_32k_ck>;
		ti,bit-shift = <28>;
		reg = <0x0200>;
	};

	mmc_ick: mmc_ick {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <26>;
		reg = <0x0210>;
	};

	mmc_fck: mmc_fck {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <26>;
		reg = <0x0200>;
	};

	eac_ick: eac_ick {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <24>;
		reg = <0x0210>;
	};

	eac_fck: eac_fck {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <24>;
		reg = <0x0200>;
	};

	i2c1_fck: i2c1_fck {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_12m_ck>;
		ti,bit-shift = <19>;
		reg = <0x0200>;
	};

	i2c2_fck: i2c2_fck {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_12m_ck>;
		ti,bit-shift = <20>;
		reg = <0x0200>;
	};

	vlynq_ick: vlynq_ick {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&core_l3_ck>;
		ti,bit-shift = <3>;
		reg = <0x0210>;
	};

	vlynq_gate_fck: vlynq_gate_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <3>;
		reg = <0x0200>;
	};

	core_d18_ck: core_d18_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&core_ck>;
		clock-mult = <1>;
		clock-div = <18>;
	};

	vlynq_mux_fck: vlynq_mux_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
		ti,bit-shift = <15>;
		reg = <0x0240>;
	};

	vlynq_fck: vlynq_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
	};
};

&prcm_clockdomains {
	gfx_clkdm: gfx_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&gfx_ick>;
	};

	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
	};

	wkup_clkdm: wkup_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
			 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
			 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
	};

	iva1_clkdm: iva1_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&iva1_mpu_int_ifck>;
	};

	dss_clkdm: dss_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dss_ick>, <&dss_54m_fck>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
			 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
			 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
			 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
			 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
			 <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
			 <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
			 <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
			 <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
			 <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
			 <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
			 <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
			 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
			 <&pka_ick>;
	};
};

&func_96m_ck {
	compatible = "fixed-factor-clock";
	clocks = <&apll96_ck>;
	clock-mult = <1>;
	clock-div = <1>;
};

&dsp_div_fck {
	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
};

&ssi_ssr_sst_div_fck {
	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
Commit	Line	Data
bc797691 TK	1	/*
	2	* Device Tree Source for OMAP2420 clock data
	3	*
	4	* Copyright (C) 2014 Texas Instruments, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	&prcm_clocks {
	12	sys_clkout2_src_gate: sys_clkout2_src_gate {
	13	#clock-cells = <0>;
	14	compatible = "ti,composite-no-wait-gate-clock";
	15	clocks = <&core_ck>;
	16	ti,bit-shift = <15>;
	17	reg = <0x0070>;
	18	};
	19
	20	sys_clkout2_src_mux: sys_clkout2_src_mux {
	21	#clock-cells = <0>;
	22	compatible = "ti,composite-mux-clock";
	23	clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
	24	ti,bit-shift = <8>;
	25	reg = <0x0070>;
	26	};
	27
	28	sys_clkout2_src: sys_clkout2_src {
	29	#clock-cells = <0>;
	30	compatible = "ti,composite-clock";
	31	clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
	32	};
	33
	34	sys_clkout2: sys_clkout2 {
	35	#clock-cells = <0>;
	36	compatible = "ti,divider-clock";
	37	clocks = <&sys_clkout2_src>;
	38	ti,bit-shift = <11>;
	39	ti,max-div = <64>;
	40	reg = <0x0070>;
	41	ti,index-power-of-two;
	42	};
	43
	44	dsp_gate_ick: dsp_gate_ick {
	45	#clock-cells = <0>;
	46	compatible = "ti,composite-interface-clock";
	47	clocks = <&dsp_fck>;
	48	ti,bit-shift = <1>;
	49	reg = <0x0810>;
	50	};
	51
	52	dsp_div_ick: dsp_div_ick {
	53	#clock-cells = <0>;
	54	compatible = "ti,composite-divider-clock";
	55	clocks = <&dsp_fck>;
	56	ti,bit-shift = <5>;
	57	ti,max-div = <3>;
	58	reg = <0x0840>;
	59	ti,index-starts-at-one;
	60	};
	61
	62	dsp_ick: dsp_ick {
	63	#clock-cells = <0>;
	64	compatible = "ti,composite-clock";
65	clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
66	};
67
68	iva1_gate_ifck: iva1_gate_ifck {
69	#clock-cells = <0>;
70	compatible = "ti,composite-gate-clock";
71	clocks = <&core_ck>;
72	ti,bit-shift = <10>;
73	reg = <0x0800>;
74	};
75
76	iva1_div_ifck: iva1_div_ifck {
77	#clock-cells = <0>;
78	compatible = "ti,composite-divider-clock";
79	clocks = <&core_ck>;
80	ti,bit-shift = <8>;
81	reg = <0x0840>;
82	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
83	};
84
85	iva1_ifck: iva1_ifck {
86	#clock-cells = <0>;
87	compatible = "ti,composite-clock";
88	clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
89	};
90
91	iva1_ifck_div: iva1_ifck_div {
92	#clock-cells = <0>;
93	compatible = "fixed-factor-clock";
94	clocks = <&iva1_ifck>;
95	clock-mult = <1>;
96	clock-div = <2>;
97	};
98
99	iva1_mpu_int_ifck: iva1_mpu_int_ifck {
100	#clock-cells = <0>;
101	compatible = "ti,wait-gate-clock";
102	clocks = <&iva1_ifck_div>;
103	ti,bit-shift = <8>;
104	reg = <0x0800>;
105	};
106
107	wdt3_ick: wdt3_ick {
108	#clock-cells = <0>;
109	compatible = "ti,omap3-interface-clock";
110	clocks = <&l4_ck>;
111	ti,bit-shift = <28>;
112	reg = <0x0210>;
113	};
114
115	wdt3_fck: wdt3_fck {
116	#clock-cells = <0>;
117	compatible = "ti,wait-gate-clock";
118	clocks = <&func_32k_ck>;
119	ti,bit-shift = <28>;
120	reg = <0x0200>;
121	};
122
123	mmc_ick: mmc_ick {
124	#clock-cells = <0>;
125	compatible = "ti,omap3-interface-clock";
126	clocks = <&l4_ck>;
127	ti,bit-shift = <26>;
128	reg = <0x0210>;
129	};
130
131	mmc_fck: mmc_fck {
132	#clock-cells = <0>;
133	compatible = "ti,wait-gate-clock";
134	clocks = <&func_96m_ck>;
135	ti,bit-shift = <26>;
136	reg = <0x0200>;
137	};
138
139	eac_ick: eac_ick {
140	#clock-cells = <0>;
141	compatible = "ti,omap3-interface-clock";
142	clocks = <&l4_ck>;
143	ti,bit-shift = <24>;
144	reg = <0x0210>;
145	};
146
147	eac_fck: eac_fck {
148	#clock-cells = <0>;
149	compatible = "ti,wait-gate-clock";
150	clocks = <&func_96m_ck>;
151	ti,bit-shift = <24>;
152	reg = <0x0200>;
153	};
154
155	i2c1_fck: i2c1_fck {
156	#clock-cells = <0>;
157	compatible = "ti,wait-gate-clock";
158	clocks = <&func_12m_ck>;
159	ti,bit-shift = <19>;
160	reg = <0x0200>;
161	};
162
163	i2c2_fck: i2c2_fck {
164	#clock-cells = <0>;
165	compatible = "ti,wait-gate-clock";
166	clocks = <&func_12m_ck>;
167	ti,bit-shift = <20>;
168	reg = <0x0200>;
169	};
170
171	vlynq_ick: vlynq_ick {
172	#clock-cells = <0>;
173	compatible = "ti,omap3-interface-clock";
174	clocks = <&core_l3_ck>;
175	ti,bit-shift = <3>;
176	reg = <0x0210>;
177	};
178
179	vlynq_gate_fck: vlynq_gate_fck {
180	#clock-cells = <0>;
181	compatible = "ti,composite-gate-clock";
182	clocks = <&core_ck>;
183	ti,bit-shift = <3>;
184	reg = <0x0200>;
185	};
186
187	core_d18_ck: core_d18_ck {
188	#clock-cells = <0>;
189	compatible = "fixed-factor-clock";
190	clocks = <&core_ck>;
191	clock-mult = <1>;
192	clock-div = <18>;
193	};
194
195	vlynq_mux_fck: vlynq_mux_fck {
196	#clock-cells = <0>;
197	compatible = "ti,composite-mux-clock";
198	clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
199	ti,bit-shift = <15>;
200	reg = <0x0240>;
201	};
202
203	vlynq_fck: vlynq_fck {
204	#clock-cells = <0>;
205	compatible = "ti,composite-clock";
206	clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
207	};
208	};
209
210	&prcm_clockdomains {
211	gfx_clkdm: gfx_clkdm {
212	compatible = "ti,clockdomain";
213	clocks = <&gfx_ick>;
214	};
215
216	core_l3_clkdm: core_l3_clkdm {
217	compatible = "ti,clockdomain";
218	clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
219	};
220
221	wkup_clkdm: wkup_clkdm {
222	compatible = "ti,clockdomain";
223	clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
224	<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
225	<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
226	};
227
228	iva1_clkdm: iva1_clkdm {
229	compatible = "ti,clockdomain";
230	clocks = <&iva1_mpu_int_ifck>;
231	};
232
233	dss_clkdm: dss_clkdm {
234	compatible = "ti,clockdomain";
235	clocks = <&dss_ick>, <&dss_54m_fck>;
236	};
237
238	core_l4_clkdm: core_l4_clkdm {
239	compatible = "ti,clockdomain";
240	clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
241	<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
242	<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
243	<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
244	<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
245	<&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
246	<&uart3_ick>, <&uart3_fck>, <&cam_ick>,
247	<&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
248	<&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
249	<&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
250	<&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
251	<&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
252	<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
253	<&pka_ick>;
254	};
255	};
256
257	&func_96m_ck {
258	compatible = "fixed-factor-clock";
259	clocks = <&apll96_ck>;
260	clock-mult = <1>;
261	clock-div = <1>;
262	};
263
264	&dsp_div_fck {
265	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
266	};
267
268	&ssi_ssr_sst_div_fck {
269	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
270	};