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26f3ff87 CF |
1 | /* |
2 | * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | /dts-v1/; | |
10 | ||
11 | #include "omap3-lilly-a83x.dtsi" | |
12 | ||
13 | / { | |
14 | model = "INCOstartec LILLY-DBB056 (DM3730)"; | |
15 | compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; | |
16 | }; | |
17 | ||
18 | &twl { | |
19 | vaux2: regulator-vaux2 { | |
20 | compatible = "ti,twl4030-vaux2"; | |
21 | regulator-min-microvolt = <2800000>; | |
22 | regulator-max-microvolt = <2800000>; | |
23 | regulator-always-on; | |
24 | }; | |
25 | }; | |
26 | ||
27 | &omap3_pmx_core { | |
28 | pinctrl-names = "default"; | |
29 | pinctrl-0 = <&lcd_pins>; | |
30 | ||
31 | lan9117_pins: pinmux_lan9117_pins { | |
32 | pinctrl-single,pins = < | |
33 | OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ | |
34 | >; | |
35 | }; | |
36 | ||
37 | gpio4_pins: pinmux_gpio4_pins { | |
38 | pinctrl-single,pins = < | |
39 | OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ | |
40 | >; | |
41 | }; | |
42 | ||
43 | gpio5_pins: pinmux_gpio5_pins { | |
44 | pinctrl-single,pins = < | |
45 | OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ | |
46 | >; | |
47 | }; | |
48 | ||
49 | lcd_pins: pinmux_lcd_pins { | |
50 | pinctrl-single,pins = < | |
51 | OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ | |
52 | OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ | |
53 | OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ | |
54 | OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ | |
55 | OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ | |
56 | OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ | |
57 | OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ | |
58 | OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ | |
59 | OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ | |
60 | OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ | |
61 | OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ | |
62 | OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ | |
63 | OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ | |
64 | OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ | |
65 | OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ | |
66 | OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ | |
67 | OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ | |
68 | OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ | |
69 | OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ | |
70 | OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ | |
71 | OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ | |
72 | OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ | |
73 | >; | |
74 | }; | |
75 | ||
76 | mmc2_pins: pinmux_mmc2_pins { | |
77 | pinctrl-single,pins = < | |
78 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ | |
79 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ | |
80 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ | |
81 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ | |
82 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ | |
83 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ | |
84 | OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ | |
85 | OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ | |
86 | OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ | |
87 | OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ | |
88 | OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ | |
89 | OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ | |
90 | >; | |
91 | }; | |
92 | ||
93 | spi1_pins: pinmux_spi1_pins { | |
94 | pinctrl-single,pins = < | |
95 | OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ | |
96 | OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ | |
97 | OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ | |
98 | OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ | |
99 | >; | |
100 | }; | |
101 | }; | |
102 | ||
103 | &gpio4 { | |
104 | pinctrl-names = "default"; | |
105 | pinctrl-0 = <&gpio4_pins>; | |
106 | }; | |
107 | ||
108 | &gpio5 { | |
109 | pinctrl-names = "default"; | |
110 | pinctrl-0 = <&gpio5_pins>; | |
111 | }; | |
112 | ||
113 | &mmc2 { | |
114 | status = "okay"; | |
115 | bus-width = <4>; | |
116 | vmmc-supply = <&vmmc1>; | |
117 | cd-gpios = <&gpio6 4 0>; /* gpio_164 */ | |
118 | wp-gpios = <&gpio6 3 0>; /* gpio_163 */ | |
119 | pinctrl-names = "default"; | |
120 | pinctrl-0 = <&mmc2_pins>; | |
121 | ti,dual-volt; | |
122 | }; | |
123 | ||
124 | &mcspi1 { | |
125 | status = "okay"; | |
126 | pinctrl-names = "default"; | |
127 | pinctrl-0 = <&spi1_pins>; | |
128 | }; | |
129 | ||
130 | &gpmc { | |
131 | ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ | |
132 | <4 0 0x20000000 0x01000000>, | |
133 | <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ | |
134 | ||
135 | ethernet@4,0 { | |
136 | compatible = "smsc,lan9117", "smsc,lan9115"; | |
137 | bank-width = <2>; | |
138 | gpmc,mux-add-data = <2>; | |
139 | gpmc,cs-on-ns = <10>; | |
140 | gpmc,cs-rd-off-ns = <65>; | |
141 | gpmc,cs-wr-off-ns = <65>; | |
142 | gpmc,adv-on-ns = <0>; | |
143 | gpmc,adv-rd-off-ns = <10>; | |
144 | gpmc,adv-wr-off-ns = <10>; | |
145 | gpmc,oe-on-ns = <10>; | |
146 | gpmc,oe-off-ns = <65>; | |
147 | gpmc,we-on-ns = <10>; | |
148 | gpmc,we-off-ns = <65>; | |
149 | gpmc,rd-cycle-ns = <100>; | |
150 | gpmc,wr-cycle-ns = <100>; | |
151 | gpmc,access-ns = <60>; | |
152 | gpmc,page-burst-access-ns = <5>; | |
153 | gpmc,bus-turnaround-ns = <0>; | |
154 | gpmc,cycle2cycle-delay-ns = <75>; | |
155 | gpmc,wr-data-mux-bus-ns = <15>; | |
156 | gpmc,wr-access-ns = <75>; | |
157 | gpmc,cycle2cycle-samecsen; | |
158 | gpmc,cycle2cycle-diffcsen; | |
159 | vddvario-supply = <®_vcc3>; | |
160 | vdd33a-supply = <®_vcc3>; | |
161 | reg-io-width = <4>; | |
162 | interrupt-parent = <&gpio4>; | |
163 | interrupts = <2 0x2>; | |
164 | reg = <4 0 0xff>; | |
165 | pinctrl-names = "default"; | |
166 | pinctrl-0 = <&lan9117_pins>; | |
167 | phy-mode = "mii"; | |
168 | smsc,force-internal-phy; | |
169 | }; | |
170 | }; |