Commit | Line | Data |
---|---|---|
a4d4b153 PM |
1 | /* |
2 | * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz> | |
c3580bc1 | 3 | * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi> |
a4d4b153 PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 (or later) as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | ||
69540a7c | 12 | #include "omap34xx.dtsi" |
3fdb7717 | 13 | #include <dt-bindings/input/input.h> |
a4d4b153 | 14 | |
69540a7c PR |
15 | /* |
16 | * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall | |
17 | * for omap AES HW crypto support. When linux kernel try to access memory of AES | |
18 | * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" | |
19 | * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no | |
20 | * crash anymore) omap AES support will be disabled for all Nokia N900 devices. | |
21 | * There is "unofficial" version of bootloader which enables AES in L3 firewall | |
22 | * but it is not widely used and to prevent kernel crash rather AES is disabled. | |
23 | * There is also no runtime detection code if AES is disabled in L3 firewall... | |
24 | */ | |
25 | &aes { | |
26 | status = "disabled"; | |
27 | }; | |
28 | ||
a4d4b153 PM |
29 | / { |
30 | model = "Nokia N900"; | |
c3580bc1 | 31 | compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; |
a4d4b153 | 32 | |
1861cda0 ID |
33 | aliases { |
34 | i2c0; | |
35 | i2c1 = &i2c1; | |
36 | i2c2 = &i2c2; | |
37 | i2c3 = &i2c3; | |
38 | }; | |
39 | ||
a4d4b153 PM |
40 | cpus { |
41 | cpu@0 { | |
42 | cpu0-supply = <&vcc>; | |
43 | }; | |
44 | }; | |
45 | ||
c1be2032 TL |
46 | leds { |
47 | compatible = "gpio-leds"; | |
48 | heartbeat { | |
49 | label = "debug::sleep"; | |
50 | gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */ | |
51 | linux,default-trigger = "default-on"; | |
52 | pinctrl-names = "default"; | |
53 | pinctrl-0 = <&debug_leds>; | |
54 | }; | |
55 | }; | |
56 | ||
a4d4b153 PM |
57 | memory { |
58 | device_type = "memory"; | |
59 | reg = <0x80000000 0x10000000>; /* 256 MB */ | |
60 | }; | |
61 | ||
3931c839 SR |
62 | gpio_keys { |
63 | compatible = "gpio-keys"; | |
64 | ||
65 | camera_lens_cover { | |
66 | label = "Camera Lens Cover"; | |
67 | gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ | |
97d7f2ff PR |
68 | linux,input-type = <EV_SW>; |
69 | linux,code = <SW_CAMERA_LENS_COVER>; | |
05cf1e03 | 70 | linux,can-disable; |
3931c839 SR |
71 | }; |
72 | ||
73 | camera_focus { | |
74 | label = "Camera Focus"; | |
75 | gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ | |
97d7f2ff | 76 | linux,code = <KEY_CAMERA_FOCUS>; |
05cf1e03 | 77 | linux,can-disable; |
3931c839 SR |
78 | }; |
79 | ||
80 | camera_capture { | |
81 | label = "Camera Capture"; | |
82 | gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ | |
97d7f2ff | 83 | linux,code = <KEY_CAMERA>; |
05cf1e03 | 84 | linux,can-disable; |
3931c839 SR |
85 | }; |
86 | ||
87 | lock_button { | |
88 | label = "Lock Button"; | |
89 | gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ | |
97d7f2ff | 90 | linux,code = <KEY_SCREENLOCK>; |
05cf1e03 | 91 | linux,can-disable; |
3931c839 SR |
92 | }; |
93 | ||
94 | keypad_slide { | |
95 | label = "Keypad Slide"; | |
96 | gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ | |
97d7f2ff PR |
97 | linux,input-type = <EV_SW>; |
98 | linux,code = <SW_KEYPAD_SLIDE>; | |
05cf1e03 | 99 | linux,can-disable; |
3931c839 SR |
100 | }; |
101 | ||
102 | proximity_sensor { | |
103 | label = "Proximity Sensor"; | |
104 | gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ | |
97d7f2ff PR |
105 | linux,input-type = <EV_SW>; |
106 | linux,code = <SW_FRONT_PROXIMITY>; | |
05cf1e03 | 107 | linux,can-disable; |
3931c839 SR |
108 | }; |
109 | }; | |
110 | ||
b950762c PR |
111 | isp1707: isp1707 { |
112 | compatible = "nxp,isp1707"; | |
e17337a2 SR |
113 | nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; |
114 | usb-phy = <&usb2_phy>; | |
115 | }; | |
1133420f TV |
116 | |
117 | tv: connector { | |
32797b3e | 118 | compatible = "composite-video-connector"; |
1133420f TV |
119 | label = "tv"; |
120 | ||
121 | port { | |
122 | tv_connector_in: endpoint { | |
123 | remote-endpoint = <&venc_out>; | |
124 | }; | |
125 | }; | |
126 | }; | |
f7d0f2a0 SR |
127 | |
128 | sound: n900-audio { | |
129 | compatible = "nokia,n900-audio"; | |
130 | ||
131 | nokia,cpu-dai = <&mcbsp2>; | |
132 | nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; | |
133 | nokia,headphone-amplifier = <&tpa6130a2>; | |
134 | ||
135 | tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ | |
136 | jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ | |
137 | eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ | |
138 | speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; | |
139 | }; | |
28398c69 SR |
140 | |
141 | battery: n900-battery { | |
142 | compatible = "nokia,n900-battery"; | |
143 | io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; | |
144 | io-channel-names = "temp", "bsi", "vbat"; | |
145 | }; | |
a4d4b153 PM |
146 | }; |
147 | ||
ac888a88 SR |
148 | &omap3_pmx_core { |
149 | pinctrl-names = "default"; | |
150 | ||
7a89eecf SR |
151 | uart2_pins: pinmux_uart2_pins { |
152 | pinctrl-single,pins = < | |
675e457c JMC |
153 | OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ |
154 | OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ | |
7a89eecf SR |
155 | >; |
156 | }; | |
157 | ||
158 | uart3_pins: pinmux_uart3_pins { | |
159 | pinctrl-single,pins = < | |
675e457c JMC |
160 | OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ |
161 | OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ | |
7a89eecf SR |
162 | >; |
163 | }; | |
164 | ||
271d4c6b TL |
165 | ethernet_pins: pinmux_ethernet_pins { |
166 | pinctrl-single,pins = < | |
167 | OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ | |
168 | OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ | |
169 | OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ | |
170 | >; | |
171 | }; | |
172 | ||
9a894953 TL |
173 | gpmc_pins: pinmux_gpmc_pins { |
174 | pinctrl-single,pins = < | |
175 | ||
176 | /* address lines */ | |
177 | OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ | |
178 | OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ | |
179 | OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ | |
180 | ||
181 | /* data lines, gpmc_d0..d7 not muxable according to TRM */ | |
182 | OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ | |
183 | OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ | |
184 | OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ | |
185 | OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ | |
186 | OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ | |
187 | OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ | |
188 | OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ | |
189 | OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ | |
190 | ||
191 | /* | |
192 | * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable | |
193 | * according to TRM. OneNAND seems to require PIN_INPUT on clock. | |
194 | */ | |
195 | OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ | |
196 | OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ | |
197 | >; | |
198 | }; | |
199 | ||
ac888a88 SR |
200 | i2c1_pins: pinmux_i2c1_pins { |
201 | pinctrl-single,pins = < | |
675e457c JMC |
202 | OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ |
203 | OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ | |
ac888a88 SR |
204 | >; |
205 | }; | |
206 | ||
207 | i2c2_pins: pinmux_i2c2_pins { | |
208 | pinctrl-single,pins = < | |
675e457c JMC |
209 | OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ |
210 | OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ | |
ac888a88 SR |
211 | >; |
212 | }; | |
213 | ||
214 | i2c3_pins: pinmux_i2c3_pins { | |
215 | pinctrl-single,pins = < | |
675e457c JMC |
216 | OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ |
217 | OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ | |
ac888a88 SR |
218 | >; |
219 | }; | |
f1751cff | 220 | |
c1be2032 TL |
221 | debug_leds: pinmux_debug_led_pins { |
222 | pinctrl-single,pins = < | |
223 | OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ | |
224 | >; | |
225 | }; | |
226 | ||
c1ad2206 SR |
227 | mcspi4_pins: pinmux_mcspi4_pins { |
228 | pinctrl-single,pins = < | |
675e457c JMC |
229 | OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ |
230 | OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ | |
231 | OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ | |
232 | OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ | |
c1ad2206 SR |
233 | >; |
234 | }; | |
235 | ||
f1751cff SR |
236 | mmc1_pins: pinmux_mmc1_pins { |
237 | pinctrl-single,pins = < | |
675e457c JMC |
238 | OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ |
239 | OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ | |
240 | OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ | |
241 | OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ | |
242 | OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ | |
243 | OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ | |
f1751cff SR |
244 | >; |
245 | }; | |
d1e6f516 | 246 | |
edd5eb4e TL |
247 | mmc2_pins: pinmux_mmc2_pins { |
248 | pinctrl-single,pins = < | |
675e457c JMC |
249 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ |
250 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ | |
251 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ | |
252 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ | |
253 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ | |
254 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ | |
255 | OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ | |
256 | OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ | |
257 | OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ | |
258 | OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ | |
edd5eb4e TL |
259 | >; |
260 | }; | |
261 | ||
1133420f | 262 | acx565akm_pins: pinmux_acx565akm_pins { |
d1e6f516 | 263 | pinctrl-single,pins = < |
675e457c | 264 | OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ |
d1e6f516 SR |
265 | >; |
266 | }; | |
1133420f TV |
267 | |
268 | dss_sdi_pins: pinmux_dss_sdi_pins { | |
269 | pinctrl-single,pins = < | |
675e457c JMC |
270 | OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ |
271 | OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ | |
272 | OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ | |
273 | OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ | |
1133420f | 274 | |
675e457c JMC |
275 | OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ |
276 | OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ | |
1133420f TV |
277 | >; |
278 | }; | |
c1ad2206 SR |
279 | |
280 | wl1251_pins: pinmux_wl1251 { | |
281 | pinctrl-single,pins = < | |
675e457c JMC |
282 | OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ |
283 | OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ | |
c1ad2206 SR |
284 | >; |
285 | }; | |
782e25a4 SR |
286 | |
287 | ssi_pins: pinmux_ssi { | |
288 | pinctrl-single,pins = < | |
675e457c JMC |
289 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ |
290 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ | |
e0e80d43 | 291 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ |
675e457c JMC |
292 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ |
293 | OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ | |
294 | OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ | |
295 | OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ | |
296 | OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ | |
782e25a4 SR |
297 | >; |
298 | }; | |
76ad4ac1 SR |
299 | |
300 | modem_pins: pinmux_modem { | |
301 | pinctrl-single,pins = < | |
675e457c | 302 | OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ |
e0e80d43 | 303 | OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ |
675e457c JMC |
304 | OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ |
305 | OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ | |
306 | OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ | |
307 | OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ | |
76ad4ac1 SR |
308 | >; |
309 | }; | |
ac888a88 SR |
310 | }; |
311 | ||
a4d4b153 | 312 | &i2c1 { |
ac888a88 SR |
313 | pinctrl-names = "default"; |
314 | pinctrl-0 = <&i2c1_pins>; | |
315 | ||
a4d4b153 PM |
316 | clock-frequency = <2200000>; |
317 | ||
318 | twl: twl@48 { | |
319 | reg = <0x48>; | |
320 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | |
321 | interrupt-parent = <&intc>; | |
322 | }; | |
323 | }; | |
324 | ||
325 | #include "twl4030.dtsi" | |
ac888a88 | 326 | #include "twl4030_omap3.dtsi" |
a4d4b153 | 327 | |
9cdbbadd SR |
328 | &vaux1 { |
329 | regulator-name = "V28"; | |
330 | regulator-min-microvolt = <2800000>; | |
331 | regulator-max-microvolt = <2800000>; | |
0698178c | 332 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
14fd7330 | 333 | regulator-always-on; /* due to battery cover sensor */ |
9cdbbadd SR |
334 | }; |
335 | ||
336 | &vaux2 { | |
337 | regulator-name = "VCSI"; | |
338 | regulator-min-microvolt = <1800000>; | |
339 | regulator-max-microvolt = <1800000>; | |
0698178c | 340 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
341 | }; |
342 | ||
343 | &vaux3 { | |
344 | regulator-name = "VMMC2_30"; | |
345 | regulator-min-microvolt = <2800000>; | |
346 | regulator-max-microvolt = <3000000>; | |
0698178c | 347 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
348 | }; |
349 | ||
350 | &vaux4 { | |
351 | regulator-name = "VCAM_ANA_28"; | |
352 | regulator-min-microvolt = <2800000>; | |
353 | regulator-max-microvolt = <2800000>; | |
0698178c | 354 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
355 | }; |
356 | ||
357 | &vmmc1 { | |
358 | regulator-name = "VMMC1"; | |
359 | regulator-min-microvolt = <1850000>; | |
360 | regulator-max-microvolt = <3150000>; | |
0698178c | 361 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
362 | }; |
363 | ||
364 | &vmmc2 { | |
365 | regulator-name = "V28_A"; | |
366 | regulator-min-microvolt = <2800000>; | |
367 | regulator-max-microvolt = <3000000>; | |
0698178c | 368 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
369 | regulator-always-on; /* due VIO leak to AIC34 VDDs */ |
370 | }; | |
371 | ||
372 | &vpll1 { | |
373 | regulator-name = "VPLL"; | |
374 | regulator-min-microvolt = <1800000>; | |
375 | regulator-max-microvolt = <1800000>; | |
0698178c | 376 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
377 | regulator-always-on; |
378 | }; | |
379 | ||
380 | &vpll2 { | |
381 | regulator-name = "VSDI_CSI"; | |
382 | regulator-min-microvolt = <1800000>; | |
383 | regulator-max-microvolt = <1800000>; | |
0698178c | 384 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
385 | regulator-always-on; |
386 | }; | |
387 | ||
388 | &vsim { | |
389 | regulator-name = "VMMC2_IO_18"; | |
390 | regulator-min-microvolt = <1800000>; | |
391 | regulator-max-microvolt = <1800000>; | |
0698178c | 392 | regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ |
9cdbbadd SR |
393 | }; |
394 | ||
395 | &vio { | |
396 | regulator-name = "VIO"; | |
397 | regulator-min-microvolt = <1800000>; | |
398 | regulator-max-microvolt = <1800000>; | |
9cdbbadd SR |
399 | }; |
400 | ||
401 | &vintana1 { | |
402 | regulator-name = "VINTANA1"; | |
403 | /* fixed to 1500000 */ | |
404 | regulator-always-on; | |
405 | }; | |
406 | ||
407 | &vintana2 { | |
408 | regulator-name = "VINTANA2"; | |
409 | regulator-min-microvolt = <2750000>; | |
410 | regulator-max-microvolt = <2750000>; | |
411 | regulator-always-on; | |
412 | }; | |
413 | ||
414 | &vintdig { | |
415 | regulator-name = "VINTDIG"; | |
416 | /* fixed to 1500000 */ | |
417 | regulator-always-on; | |
418 | }; | |
419 | ||
06ba7a61 SR |
420 | &twl { |
421 | twl_audio: audio { | |
422 | compatible = "ti,twl4030-audio"; | |
423 | ti,enable-vibra = <1>; | |
424 | }; | |
9188883f TL |
425 | |
426 | twl_power: power { | |
daebabd5 | 427 | compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; |
9188883f TL |
428 | ti,use_poweroff; |
429 | }; | |
06ba7a61 SR |
430 | }; |
431 | ||
85c215f3 | 432 | &twl_keypad { |
3fdb7717 SR |
433 | linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) |
434 | MATRIX_KEY(0x00, 0x01, KEY_O) | |
435 | MATRIX_KEY(0x00, 0x02, KEY_P) | |
436 | MATRIX_KEY(0x00, 0x03, KEY_COMMA) | |
437 | MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) | |
438 | MATRIX_KEY(0x00, 0x06, KEY_A) | |
439 | MATRIX_KEY(0x00, 0x07, KEY_S) | |
440 | ||
441 | MATRIX_KEY(0x01, 0x00, KEY_W) | |
442 | MATRIX_KEY(0x01, 0x01, KEY_D) | |
443 | MATRIX_KEY(0x01, 0x02, KEY_F) | |
444 | MATRIX_KEY(0x01, 0x03, KEY_G) | |
445 | MATRIX_KEY(0x01, 0x04, KEY_H) | |
446 | MATRIX_KEY(0x01, 0x05, KEY_J) | |
447 | MATRIX_KEY(0x01, 0x06, KEY_K) | |
448 | MATRIX_KEY(0x01, 0x07, KEY_L) | |
449 | ||
450 | MATRIX_KEY(0x02, 0x00, KEY_E) | |
451 | MATRIX_KEY(0x02, 0x01, KEY_DOT) | |
452 | MATRIX_KEY(0x02, 0x02, KEY_UP) | |
453 | MATRIX_KEY(0x02, 0x03, KEY_ENTER) | |
454 | MATRIX_KEY(0x02, 0x05, KEY_Z) | |
455 | MATRIX_KEY(0x02, 0x06, KEY_X) | |
456 | MATRIX_KEY(0x02, 0x07, KEY_C) | |
457 | MATRIX_KEY(0x02, 0x08, KEY_F9) | |
458 | ||
459 | MATRIX_KEY(0x03, 0x00, KEY_R) | |
460 | MATRIX_KEY(0x03, 0x01, KEY_V) | |
461 | MATRIX_KEY(0x03, 0x02, KEY_B) | |
462 | MATRIX_KEY(0x03, 0x03, KEY_N) | |
463 | MATRIX_KEY(0x03, 0x04, KEY_M) | |
464 | MATRIX_KEY(0x03, 0x05, KEY_SPACE) | |
465 | MATRIX_KEY(0x03, 0x06, KEY_SPACE) | |
466 | MATRIX_KEY(0x03, 0x07, KEY_LEFT) | |
467 | ||
468 | MATRIX_KEY(0x04, 0x00, KEY_T) | |
469 | MATRIX_KEY(0x04, 0x01, KEY_DOWN) | |
470 | MATRIX_KEY(0x04, 0x02, KEY_RIGHT) | |
471 | MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) | |
472 | MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) | |
473 | MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) | |
474 | MATRIX_KEY(0x04, 0x08, KEY_F10) | |
475 | ||
476 | MATRIX_KEY(0x05, 0x00, KEY_Y) | |
477 | MATRIX_KEY(0x05, 0x08, KEY_F11) | |
478 | ||
479 | MATRIX_KEY(0x06, 0x00, KEY_U) | |
480 | ||
481 | MATRIX_KEY(0x07, 0x00, KEY_I) | |
482 | MATRIX_KEY(0x07, 0x01, KEY_F7) | |
483 | MATRIX_KEY(0x07, 0x02, KEY_F8) | |
85c215f3 SR |
484 | >; |
485 | }; | |
486 | ||
a4d4b153 PM |
487 | &twl_gpio { |
488 | ti,pullups = <0x0>; | |
489 | ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ | |
490 | }; | |
491 | ||
492 | &i2c2 { | |
ac888a88 SR |
493 | pinctrl-names = "default"; |
494 | pinctrl-0 = <&i2c2_pins>; | |
495 | ||
48fc9864 | 496 | clock-frequency = <100000>; |
b2b9b258 | 497 | |
14e3e295 SR |
498 | tlv320aic3x: tlv320aic3x@18 { |
499 | compatible = "ti,tlv320aic3x"; | |
500 | reg = <0x18>; | |
501 | gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ | |
502 | ai3x-gpio-func = < | |
503 | 0 /* AIC3X_GPIO1_FUNC_DISABLED */ | |
504 | 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ | |
505 | >; | |
506 | ||
507 | AVDD-supply = <&vmmc2>; | |
508 | DRVDD-supply = <&vmmc2>; | |
509 | IOVDD-supply = <&vio>; | |
510 | DVDD-supply = <&vio>; | |
1819e303 PM |
511 | |
512 | ai3x-micbias-vg = <1>; | |
14e3e295 SR |
513 | }; |
514 | ||
515 | tlv320aic3x_aux: tlv320aic3x@19 { | |
516 | compatible = "ti,tlv320aic3x"; | |
517 | reg = <0x19>; | |
518 | gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ | |
519 | ||
520 | AVDD-supply = <&vmmc2>; | |
521 | DRVDD-supply = <&vmmc2>; | |
522 | IOVDD-supply = <&vio>; | |
523 | DVDD-supply = <&vio>; | |
1819e303 PM |
524 | |
525 | ai3x-micbias-vg = <2>; | |
14e3e295 SR |
526 | }; |
527 | ||
12f2f873 SR |
528 | tsl2563: tsl2563@29 { |
529 | compatible = "amstaos,tsl2563"; | |
530 | reg = <0x29>; | |
531 | ||
532 | amstaos,cover-comp-gain = <16>; | |
533 | }; | |
534 | ||
14628e44 PR |
535 | adp1653: led-controller@30 { |
536 | compatible = "adi,adp1653"; | |
537 | reg = <0x30>; | |
538 | enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ | |
539 | ||
540 | flash { | |
541 | flash-timeout-us = <500000>; | |
542 | flash-max-microamp = <320000>; | |
543 | led-max-microamp = <50000>; | |
544 | }; | |
545 | indicator { | |
546 | led-max-microamp = <17500>; | |
547 | }; | |
548 | }; | |
549 | ||
a0bf1f3e SR |
550 | lp5523: lp5523@32 { |
551 | compatible = "national,lp5523"; | |
552 | reg = <0x32>; | |
553 | clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ | |
554 | enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ | |
555 | ||
556 | chan0 { | |
557 | chan-name = "lp5523:kb1"; | |
558 | led-cur = /bits/ 8 <50>; | |
559 | max-cur = /bits/ 8 <100>; | |
560 | }; | |
561 | ||
562 | chan1 { | |
563 | chan-name = "lp5523:kb2"; | |
564 | led-cur = /bits/ 8 <50>; | |
565 | max-cur = /bits/ 8 <100>; | |
566 | }; | |
567 | ||
568 | chan2 { | |
569 | chan-name = "lp5523:kb3"; | |
570 | led-cur = /bits/ 8 <50>; | |
571 | max-cur = /bits/ 8 <100>; | |
572 | }; | |
573 | ||
574 | chan3 { | |
575 | chan-name = "lp5523:kb4"; | |
576 | led-cur = /bits/ 8 <50>; | |
577 | max-cur = /bits/ 8 <100>; | |
578 | }; | |
579 | ||
580 | chan4 { | |
581 | chan-name = "lp5523:b"; | |
582 | led-cur = /bits/ 8 <50>; | |
583 | max-cur = /bits/ 8 <100>; | |
584 | }; | |
585 | ||
586 | chan5 { | |
587 | chan-name = "lp5523:g"; | |
588 | led-cur = /bits/ 8 <50>; | |
589 | max-cur = /bits/ 8 <100>; | |
590 | }; | |
591 | ||
592 | chan6 { | |
593 | chan-name = "lp5523:r"; | |
594 | led-cur = /bits/ 8 <50>; | |
595 | max-cur = /bits/ 8 <100>; | |
596 | }; | |
597 | ||
598 | chan7 { | |
599 | chan-name = "lp5523:kb5"; | |
600 | led-cur = /bits/ 8 <50>; | |
601 | max-cur = /bits/ 8 <100>; | |
602 | }; | |
603 | ||
604 | chan8 { | |
605 | chan-name = "lp5523:kb6"; | |
606 | led-cur = /bits/ 8 <50>; | |
607 | max-cur = /bits/ 8 <100>; | |
608 | }; | |
609 | }; | |
610 | ||
b2b9b258 SR |
611 | bq27200: bq27200@55 { |
612 | compatible = "ti,bq27200"; | |
613 | reg = <0x55>; | |
614 | }; | |
9e2367c8 SR |
615 | |
616 | tpa6130a2: tpa6130a2@60 { | |
617 | compatible = "ti,tpa6130a2"; | |
618 | reg = <0x60>; | |
619 | ||
620 | Vdd-supply = <&vmmc2>; | |
621 | ||
622 | power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ | |
623 | }; | |
334a09c8 | 624 | |
406c07e7 SR |
625 | si4713: si4713@63 { |
626 | compatible = "silabs,si4713"; | |
627 | reg = <0x63>; | |
628 | ||
629 | interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ | |
630 | reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ | |
631 | vio-supply = <&vio>; | |
632 | vdd-supply = <&vaux1>; | |
633 | }; | |
634 | ||
334a09c8 SR |
635 | bq24150a: bq24150a@6b { |
636 | compatible = "ti,bq24150a"; | |
637 | reg = <0x6b>; | |
638 | ||
639 | ti,current-limit = <100>; | |
640 | ti,weak-battery-voltage = <3400>; | |
641 | ti,battery-regulation-voltage = <4200>; | |
642 | ti,charge-current = <650>; | |
643 | ti,termination-current = <100>; | |
644 | ti,resistor-sense = <68>; | |
645 | ||
b950762c | 646 | ti,usb-charger-detection = <&isp1707>; |
334a09c8 | 647 | }; |
a4d4b153 PM |
648 | }; |
649 | ||
650 | &i2c3 { | |
ac888a88 SR |
651 | pinctrl-names = "default"; |
652 | pinctrl-0 = <&i2c3_pins>; | |
653 | ||
48fc9864 | 654 | clock-frequency = <400000>; |
1ac4e6fe SR |
655 | |
656 | lis302dl: lis3lv02d@1d { | |
657 | compatible = "st,lis3lv02d"; | |
658 | reg = <0x1d>; | |
659 | ||
660 | Vdd-supply = <&vaux1>; | |
661 | Vdd_IO-supply = <&vio>; | |
662 | ||
663 | interrupt-parent = <&gpio6>; | |
664 | interrupts = <21 20>; /* 181 and 180 */ | |
665 | ||
666 | /* click flags */ | |
667 | st,click-single-x; | |
668 | st,click-single-y; | |
669 | st,click-single-z; | |
670 | ||
671 | /* Limits are 0.5g * value */ | |
672 | st,click-threshold-x = <8>; | |
673 | st,click-threshold-y = <8>; | |
674 | st,click-threshold-z = <10>; | |
675 | ||
676 | /* Click must be longer than time limit */ | |
677 | st,click-time-limit = <9>; | |
678 | ||
679 | /* Kind of debounce filter */ | |
680 | st,click-latency = <50>; | |
681 | ||
682 | /* Interrupt line 2 for click detection */ | |
683 | st,irq2-click; | |
684 | ||
685 | st,wakeup-x-hi; | |
686 | st,wakeup-y-hi; | |
687 | st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ | |
688 | ||
689 | st,wakeup2-z-hi; | |
690 | st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ | |
691 | ||
692 | st,hipass1-disable; | |
693 | st,hipass2-disable; | |
694 | ||
695 | st,axis-x = <1>; /* LIS3_DEV_X */ | |
696 | st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ | |
697 | st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ | |
698 | ||
699 | st,min-limit-x = <(-32)>; | |
700 | st,min-limit-y = <3>; | |
701 | st,min-limit-z = <3>; | |
702 | ||
703 | st,max-limit-x = <(-3)>; | |
704 | st,max-limit-y = <32>; | |
705 | st,max-limit-z = <32>; | |
706 | }; | |
a4d4b153 PM |
707 | }; |
708 | ||
709 | &mmc1 { | |
f1751cff SR |
710 | pinctrl-names = "default"; |
711 | pinctrl-0 = <&mmc1_pins>; | |
712 | vmmc-supply = <&vmmc1>; | |
713 | bus-width = <4>; | |
714 | cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */ | |
a4d4b153 PM |
715 | }; |
716 | ||
edd5eb4e | 717 | /* most boards use vaux3, only some old versions use vmmc2 instead */ |
a4d4b153 | 718 | &mmc2 { |
edd5eb4e TL |
719 | pinctrl-names = "default"; |
720 | pinctrl-0 = <&mmc2_pins>; | |
721 | vmmc-supply = <&vaux3>; | |
722 | vmmc_aux-supply = <&vsim>; | |
723 | bus-width = <8>; | |
724 | non-removable; | |
a4d4b153 PM |
725 | }; |
726 | ||
727 | &mmc3 { | |
728 | status = "disabled"; | |
729 | }; | |
730 | ||
8699d2dd | 731 | &gpmc { |
271d4c6b TL |
732 | ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ |
733 | <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ | |
9a894953 TL |
734 | pinctrl-names = "default"; |
735 | pinctrl-0 = <&gpmc_pins>; | |
8699d2dd | 736 | |
e2c5eb78 | 737 | /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ |
8699d2dd SR |
738 | onenand@0,0 { |
739 | #address-cells = <1>; | |
740 | #size-cells = <1>; | |
e2c5eb78 | 741 | reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ |
8699d2dd SR |
742 | |
743 | gpmc,sync-read; | |
744 | gpmc,sync-write; | |
745 | gpmc,burst-length = <16>; | |
746 | gpmc,burst-read; | |
747 | gpmc,burst-wrap; | |
748 | gpmc,burst-write; | |
749 | gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ | |
750 | gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ | |
751 | gpmc,cs-on-ns = <0>; | |
752 | gpmc,cs-rd-off-ns = <87>; | |
753 | gpmc,cs-wr-off-ns = <87>; | |
754 | gpmc,adv-on-ns = <0>; | |
755 | gpmc,adv-rd-off-ns = <10>; | |
756 | gpmc,adv-wr-off-ns = <10>; | |
757 | gpmc,oe-on-ns = <15>; | |
758 | gpmc,oe-off-ns = <87>; | |
759 | gpmc,we-on-ns = <0>; | |
760 | gpmc,we-off-ns = <87>; | |
761 | gpmc,rd-cycle-ns = <112>; | |
762 | gpmc,wr-cycle-ns = <112>; | |
763 | gpmc,access-ns = <81>; | |
764 | gpmc,page-burst-access-ns = <15>; | |
765 | gpmc,bus-turnaround-ns = <0>; | |
766 | gpmc,cycle2cycle-delay-ns = <0>; | |
767 | gpmc,wait-monitoring-ns = <0>; | |
768 | gpmc,clk-activation-ns = <5>; | |
769 | gpmc,wr-data-mux-bus-ns = <30>; | |
770 | gpmc,wr-access-ns = <81>; | |
771 | gpmc,sync-clk-ps = <15000>; | |
772 | ||
773 | /* | |
774 | * MTD partition table corresponding to Nokia's | |
775 | * Maemo 5 (Fremantle) release. | |
776 | */ | |
777 | partition@0 { | |
778 | label = "bootloader"; | |
779 | reg = <0x00000000 0x00020000>; | |
780 | read-only; | |
781 | }; | |
782 | partition@1 { | |
783 | label = "config"; | |
784 | reg = <0x00020000 0x00060000>; | |
785 | }; | |
786 | partition@2 { | |
787 | label = "log"; | |
788 | reg = <0x00080000 0x00040000>; | |
789 | }; | |
790 | partition@3 { | |
791 | label = "kernel"; | |
792 | reg = <0x000c0000 0x00200000>; | |
793 | }; | |
794 | partition@4 { | |
795 | label = "initfs"; | |
796 | reg = <0x002c0000 0x00200000>; | |
797 | }; | |
798 | partition@5 { | |
799 | label = "rootfs"; | |
800 | reg = <0x004c0000 0x0fb40000>; | |
801 | }; | |
802 | }; | |
271d4c6b | 803 | |
7ac72746 | 804 | /* Ethernet is on some early development boards and qemu */ |
271d4c6b TL |
805 | ethernet@gpmc { |
806 | compatible = "smsc,lan91c94"; | |
807 | interrupt-parent = <&gpio2>; | |
808 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ | |
cb9071d4 | 809 | reg = <1 0 0xf>; /* 16 byte IO range */ |
271d4c6b TL |
810 | bank-width = <2>; |
811 | pinctrl-names = "default"; | |
812 | pinctrl-0 = <ðernet_pins>; | |
7d2911c4 TL |
813 | power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ |
814 | reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ | |
271d4c6b TL |
815 | gpmc,device-width = <2>; |
816 | gpmc,sync-clk-ps = <0>; | |
817 | gpmc,cs-on-ns = <0>; | |
818 | gpmc,cs-rd-off-ns = <48>; | |
819 | gpmc,cs-wr-off-ns = <24>; | |
820 | gpmc,adv-on-ns = <0>; | |
821 | gpmc,adv-rd-off-ns = <0>; | |
822 | gpmc,adv-wr-off-ns = <0>; | |
823 | gpmc,we-on-ns = <12>; | |
824 | gpmc,we-off-ns = <18>; | |
825 | gpmc,oe-on-ns = <12>; | |
826 | gpmc,oe-off-ns = <48>; | |
827 | gpmc,page-burst-access-ns = <0>; | |
828 | gpmc,access-ns = <42>; | |
829 | gpmc,rd-cycle-ns = <180>; | |
830 | gpmc,wr-cycle-ns = <180>; | |
831 | gpmc,bus-turnaround-ns = <0>; | |
832 | gpmc,cycle2cycle-delay-ns = <0>; | |
833 | gpmc,wait-monitoring-ns = <0>; | |
834 | gpmc,clk-activation-ns = <0>; | |
835 | gpmc,wr-access-ns = <0>; | |
836 | gpmc,wr-data-mux-bus-ns = <12>; | |
837 | }; | |
8699d2dd SR |
838 | }; |
839 | ||
a4d4b153 PM |
840 | &mcspi1 { |
841 | /* | |
842 | * For some reason, touchscreen is necessary for screen to work at | |
843 | * all on real hw. It works well without it on emulator. | |
844 | * | |
845 | * Also... order in the device tree actually matters here. | |
846 | */ | |
847 | tsc2005@0 { | |
50525891 | 848 | compatible = "ti,tsc2005"; |
a4d4b153 PM |
849 | spi-max-frequency = <6000000>; |
850 | reg = <0>; | |
50525891 SR |
851 | |
852 | vio-supply = <&vio>; | |
853 | ||
854 | reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ | |
855 | interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ | |
856 | ||
857 | touchscreen-fuzz-x = <4>; | |
858 | touchscreen-fuzz-y = <7>; | |
859 | touchscreen-fuzz-pressure = <2>; | |
8770d089 PM |
860 | touchscreen-size-x = <4096>; |
861 | touchscreen-size-y = <4096>; | |
50525891 SR |
862 | touchscreen-max-pressure = <2048>; |
863 | ||
864 | ti,x-plate-ohms = <280>; | |
865 | ti,esd-recovery-timeout-ms = <8000>; | |
a4d4b153 | 866 | }; |
1133420f TV |
867 | |
868 | acx565akm@2 { | |
869 | compatible = "sony,acx565akm"; | |
a4d4b153 PM |
870 | spi-max-frequency = <6000000>; |
871 | reg = <2>; | |
d1e6f516 SR |
872 | |
873 | pinctrl-names = "default"; | |
1133420f TV |
874 | pinctrl-0 = <&acx565akm_pins>; |
875 | ||
876 | label = "lcd"; | |
877 | reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ | |
878 | ||
879 | port { | |
880 | lcd_in: endpoint { | |
881 | remote-endpoint = <&sdi_out>; | |
882 | }; | |
883 | }; | |
a4d4b153 PM |
884 | }; |
885 | }; | |
886 | ||
c1ad2206 SR |
887 | &mcspi4 { |
888 | pinctrl-names = "default"; | |
889 | pinctrl-0 = <&mcspi4_pins>; | |
890 | ||
891 | wl1251@0 { | |
892 | pinctrl-names = "default"; | |
893 | pinctrl-0 = <&wl1251_pins>; | |
894 | ||
895 | vio-supply = <&vio>; | |
896 | ||
897 | compatible = "ti,wl1251"; | |
898 | reg = <0>; | |
899 | spi-max-frequency = <48000000>; | |
900 | ||
901 | spi-cpol; | |
902 | spi-cpha; | |
903 | ||
904 | ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ | |
905 | ||
906 | interrupt-parent = <&gpio2>; | |
907 | interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ | |
908 | }; | |
909 | }; | |
910 | ||
a4d4b153 PM |
911 | &usb_otg_hs { |
912 | interface-type = <0>; | |
913 | usb-phy = <&usb2_phy>; | |
d2afcf09 RQ |
914 | phys = <&usb2_phy>; |
915 | phy-names = "usb2-phy"; | |
a4d4b153 PM |
916 | mode = <2>; |
917 | power = <50>; | |
918 | }; | |
7a89eecf SR |
919 | |
920 | &uart1 { | |
921 | status = "disabled"; | |
922 | }; | |
923 | ||
924 | &uart2 { | |
31f0820a | 925 | interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; |
7a89eecf SR |
926 | pinctrl-names = "default"; |
927 | pinctrl-0 = <&uart2_pins>; | |
928 | }; | |
929 | ||
930 | &uart3 { | |
31f0820a | 931 | interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; |
7a89eecf SR |
932 | pinctrl-names = "default"; |
933 | pinctrl-0 = <&uart3_pins>; | |
934 | }; | |
1133420f TV |
935 | |
936 | &dss { | |
937 | status = "ok"; | |
938 | ||
939 | pinctrl-names = "default"; | |
940 | pinctrl-0 = <&dss_sdi_pins>; | |
941 | ||
942 | vdds_sdi-supply = <&vaux1>; | |
943 | ||
944 | ports { | |
945 | #address-cells = <1>; | |
946 | #size-cells = <0>; | |
947 | ||
948 | port@1 { | |
949 | reg = <1>; | |
950 | ||
951 | sdi_out: endpoint { | |
952 | remote-endpoint = <&lcd_in>; | |
953 | datapairs = <2>; | |
954 | }; | |
955 | }; | |
956 | }; | |
957 | }; | |
958 | ||
959 | &venc { | |
960 | status = "ok"; | |
961 | ||
962 | vdda-supply = <&vdac>; | |
963 | ||
964 | port { | |
965 | venc_out: endpoint { | |
966 | remote-endpoint = <&tv_connector_in>; | |
967 | ti,channels = <1>; | |
968 | }; | |
969 | }; | |
970 | }; | |
f7d0f2a0 SR |
971 | |
972 | &mcbsp2 { | |
973 | status = "ok"; | |
974 | }; | |
782e25a4 SR |
975 | |
976 | &ssi_port1 { | |
977 | pinctrl-names = "default"; | |
978 | pinctrl-0 = <&ssi_pins>; | |
979 | ||
980 | ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ | |
76ad4ac1 SR |
981 | |
982 | modem: hsi-client { | |
983 | compatible = "nokia,n900-modem"; | |
984 | ||
985 | pinctrl-names = "default"; | |
986 | pinctrl-0 = <&modem_pins>; | |
987 | ||
988 | hsi-channel-ids = <0>, <1>, <2>, <3>; | |
989 | hsi-channel-names = "mcsaab-control", | |
990 | "speech-control", | |
991 | "speech-data", | |
992 | "mcsaab-data"; | |
993 | hsi-speed-kbps = <55000>; | |
994 | hsi-mode = "frame"; | |
995 | hsi-flow = "synchronized"; | |
996 | hsi-arb-mode = "round-robin"; | |
997 | ||
998 | interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ | |
999 | ||
1000 | gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ | |
1001 | <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ | |
1002 | <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ | |
1003 | <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ | |
1004 | <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ | |
1005 | gpio-names = "cmt_apeslpx", | |
1006 | "cmt_rst_rq", | |
1007 | "cmt_en", | |
1008 | "cmt_rst", | |
1009 | "cmt_bsi"; | |
1010 | }; | |
782e25a4 SR |
1011 | }; |
1012 | ||
1013 | &ssi_port2 { | |
1014 | status = "disabled"; | |
76ad4ac1 | 1015 | }; |