Commit | Line | Data |
---|---|---|
189892f4 BC |
1 | /* |
2 | * Device Tree Source for OMAP3 SoC | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
6d624eab | 11 | #include <dt-bindings/gpio/gpio.h> |
71fdc6e4 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
bcd3cca7 | 13 | #include <dt-bindings/pinctrl/omap.h> |
6d624eab | 14 | |
98ef7957 | 15 | #include "skeleton.dtsi" |
189892f4 BC |
16 | |
17 | / { | |
18 | compatible = "ti,omap3430", "ti,omap3"; | |
4c94ac29 | 19 | interrupt-parent = <&intc>; |
189892f4 | 20 | |
cf3c79de RN |
21 | aliases { |
22 | serial0 = &uart1; | |
23 | serial1 = &uart2; | |
24 | serial2 = &uart3; | |
cf3c79de RN |
25 | }; |
26 | ||
476b679a | 27 | cpus { |
eeb25fd5 LP |
28 | #address-cells = <1>; |
29 | #size-cells = <0>; | |
30 | ||
476b679a BC |
31 | cpu@0 { |
32 | compatible = "arm,cortex-a8"; | |
eeb25fd5 LP |
33 | device_type = "cpu"; |
34 | reg = <0x0>; | |
476b679a BC |
35 | }; |
36 | }; | |
37 | ||
9b07b477 JH |
38 | pmu { |
39 | compatible = "arm,cortex-a8-pmu"; | |
40 | interrupts = <3>; | |
41 | ti,hwmods = "debugss"; | |
42 | }; | |
43 | ||
189892f4 | 44 | /* |
161e89a6 | 45 | * The soc node represents the soc top level view. It is used for IPs |
189892f4 BC |
46 | * that are not memory mapped in the MPU view or for the MPU itself. |
47 | */ | |
48 | soc { | |
49 | compatible = "ti,omap-infra"; | |
476b679a BC |
50 | mpu { |
51 | compatible = "ti,omap3-mpu"; | |
52 | ti,hwmods = "mpu"; | |
53 | }; | |
54 | ||
55 | iva { | |
56 | compatible = "ti,iva2.2"; | |
57 | ti,hwmods = "iva"; | |
58 | ||
59 | dsp { | |
60 | compatible = "ti,omap3-c64"; | |
61 | }; | |
62 | }; | |
189892f4 BC |
63 | }; |
64 | ||
65 | /* | |
66 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
67 | * The real OMAP interconnect network is quite complex. | |
68 | * Since that will not bring real advantage to represent that in DT for | |
69 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
70 | * hierarchy. | |
71 | */ | |
72 | ocp { | |
73 | compatible = "simple-bus"; | |
74 | #address-cells = <1>; | |
75 | #size-cells = <1>; | |
76 | ranges; | |
77 | ti,hwmods = "l3_main"; | |
78 | ||
510c0ffd JH |
79 | counter32k: counter@48320000 { |
80 | compatible = "ti,omap-counter32k"; | |
81 | reg = <0x48320000 0x20>; | |
82 | ti,hwmods = "counter_32k"; | |
83 | }; | |
84 | ||
d65c5423 BC |
85 | intc: interrupt-controller@48200000 { |
86 | compatible = "ti,omap2-intc"; | |
189892f4 BC |
87 | interrupt-controller; |
88 | #interrupt-cells = <1>; | |
d65c5423 BC |
89 | ti,intc-size = <96>; |
90 | reg = <0x48200000 0x1000>; | |
189892f4 | 91 | }; |
cf3c79de | 92 | |
2c2dc545 JH |
93 | sdma: dma-controller@48056000 { |
94 | compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; | |
95 | reg = <0x48056000 0x1000>; | |
96 | interrupts = <12>, | |
97 | <13>, | |
98 | <14>, | |
99 | <15>; | |
100 | #dma-cells = <1>; | |
101 | #dma-channels = <32>; | |
102 | #dma-requests = <96>; | |
103 | }; | |
104 | ||
679e3310 TL |
105 | omap3_pmx_core: pinmux@48002030 { |
106 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
107 | reg = <0x48002030 0x05cc>; | |
108 | #address-cells = <1>; | |
109 | #size-cells = <0>; | |
110 | pinctrl-single,register-width = <16>; | |
d623a0e1 | 111 | pinctrl-single,function-mask = <0xff1f>; |
679e3310 TL |
112 | }; |
113 | ||
161e89a6 | 114 | omap3_pmx_wkup: pinmux@0x48002a00 { |
679e3310 | 115 | compatible = "ti,omap3-padconf", "pinctrl-single"; |
161e89a6 | 116 | reg = <0x48002a00 0x5c>; |
679e3310 TL |
117 | #address-cells = <1>; |
118 | #size-cells = <0>; | |
119 | pinctrl-single,register-width = <16>; | |
d623a0e1 | 120 | pinctrl-single,function-mask = <0xff1f>; |
679e3310 TL |
121 | }; |
122 | ||
385a64bb BC |
123 | gpio1: gpio@48310000 { |
124 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
125 | reg = <0x48310000 0x200>; |
126 | interrupts = <29>; | |
385a64bb | 127 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 128 | ti,gpio-always-on; |
385a64bb BC |
129 | gpio-controller; |
130 | #gpio-cells = <2>; | |
131 | interrupt-controller; | |
ff5c9059 | 132 | #interrupt-cells = <2>; |
385a64bb BC |
133 | }; |
134 | ||
135 | gpio2: gpio@49050000 { | |
136 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
137 | reg = <0x49050000 0x200>; |
138 | interrupts = <30>; | |
385a64bb BC |
139 | ti,hwmods = "gpio2"; |
140 | gpio-controller; | |
141 | #gpio-cells = <2>; | |
142 | interrupt-controller; | |
ff5c9059 | 143 | #interrupt-cells = <2>; |
385a64bb BC |
144 | }; |
145 | ||
146 | gpio3: gpio@49052000 { | |
147 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
148 | reg = <0x49052000 0x200>; |
149 | interrupts = <31>; | |
385a64bb BC |
150 | ti,hwmods = "gpio3"; |
151 | gpio-controller; | |
152 | #gpio-cells = <2>; | |
153 | interrupt-controller; | |
ff5c9059 | 154 | #interrupt-cells = <2>; |
385a64bb BC |
155 | }; |
156 | ||
157 | gpio4: gpio@49054000 { | |
158 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
159 | reg = <0x49054000 0x200>; |
160 | interrupts = <32>; | |
385a64bb BC |
161 | ti,hwmods = "gpio4"; |
162 | gpio-controller; | |
163 | #gpio-cells = <2>; | |
164 | interrupt-controller; | |
ff5c9059 | 165 | #interrupt-cells = <2>; |
385a64bb BC |
166 | }; |
167 | ||
168 | gpio5: gpio@49056000 { | |
169 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
170 | reg = <0x49056000 0x200>; |
171 | interrupts = <33>; | |
385a64bb BC |
172 | ti,hwmods = "gpio5"; |
173 | gpio-controller; | |
174 | #gpio-cells = <2>; | |
175 | interrupt-controller; | |
ff5c9059 | 176 | #interrupt-cells = <2>; |
385a64bb BC |
177 | }; |
178 | ||
179 | gpio6: gpio@49058000 { | |
180 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
181 | reg = <0x49058000 0x200>; |
182 | interrupts = <34>; | |
385a64bb BC |
183 | ti,hwmods = "gpio6"; |
184 | gpio-controller; | |
185 | #gpio-cells = <2>; | |
186 | interrupt-controller; | |
ff5c9059 | 187 | #interrupt-cells = <2>; |
385a64bb BC |
188 | }; |
189 | ||
19bfb76c | 190 | uart1: serial@4806a000 { |
cf3c79de RN |
191 | compatible = "ti,omap3-uart"; |
192 | ti,hwmods = "uart1"; | |
193 | clock-frequency = <48000000>; | |
194 | }; | |
195 | ||
19bfb76c | 196 | uart2: serial@4806c000 { |
cf3c79de RN |
197 | compatible = "ti,omap3-uart"; |
198 | ti,hwmods = "uart2"; | |
199 | clock-frequency = <48000000>; | |
200 | }; | |
201 | ||
19bfb76c | 202 | uart3: serial@49020000 { |
cf3c79de RN |
203 | compatible = "ti,omap3-uart"; |
204 | ti,hwmods = "uart3"; | |
205 | clock-frequency = <48000000>; | |
206 | }; | |
207 | ||
ca59a5c1 BC |
208 | i2c1: i2c@48070000 { |
209 | compatible = "ti,omap3-i2c"; | |
210 | #address-cells = <1>; | |
211 | #size-cells = <0>; | |
212 | ti,hwmods = "i2c1"; | |
213 | }; | |
214 | ||
215 | i2c2: i2c@48072000 { | |
216 | compatible = "ti,omap3-i2c"; | |
217 | #address-cells = <1>; | |
218 | #size-cells = <0>; | |
219 | ti,hwmods = "i2c2"; | |
220 | }; | |
221 | ||
222 | i2c3: i2c@48060000 { | |
223 | compatible = "ti,omap3-i2c"; | |
224 | #address-cells = <1>; | |
225 | #size-cells = <0>; | |
226 | ti,hwmods = "i2c3"; | |
227 | }; | |
fc72d248 BC |
228 | |
229 | mcspi1: spi@48098000 { | |
230 | compatible = "ti,omap2-mcspi"; | |
231 | #address-cells = <1>; | |
232 | #size-cells = <0>; | |
233 | ti,hwmods = "mcspi1"; | |
234 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
235 | dmas = <&sdma 35>, |
236 | <&sdma 36>, | |
237 | <&sdma 37>, | |
238 | <&sdma 38>, | |
239 | <&sdma 39>, | |
240 | <&sdma 40>, | |
241 | <&sdma 41>, | |
242 | <&sdma 42>; | |
243 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
244 | "tx2", "rx2", "tx3", "rx3"; | |
fc72d248 BC |
245 | }; |
246 | ||
247 | mcspi2: spi@4809a000 { | |
248 | compatible = "ti,omap2-mcspi"; | |
249 | #address-cells = <1>; | |
250 | #size-cells = <0>; | |
251 | ti,hwmods = "mcspi2"; | |
252 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
253 | dmas = <&sdma 43>, |
254 | <&sdma 44>, | |
255 | <&sdma 45>, | |
256 | <&sdma 46>; | |
257 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
258 | }; |
259 | ||
260 | mcspi3: spi@480b8000 { | |
261 | compatible = "ti,omap2-mcspi"; | |
262 | #address-cells = <1>; | |
263 | #size-cells = <0>; | |
264 | ti,hwmods = "mcspi3"; | |
265 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
266 | dmas = <&sdma 15>, |
267 | <&sdma 16>, | |
268 | <&sdma 23>, | |
269 | <&sdma 24>; | |
270 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
271 | }; |
272 | ||
273 | mcspi4: spi@480ba000 { | |
274 | compatible = "ti,omap2-mcspi"; | |
275 | #address-cells = <1>; | |
276 | #size-cells = <0>; | |
277 | ti,hwmods = "mcspi4"; | |
278 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
279 | dmas = <&sdma 70>, <&sdma 71>; |
280 | dma-names = "tx0", "rx0"; | |
fc72d248 | 281 | }; |
b3431f5b RN |
282 | |
283 | mmc1: mmc@4809c000 { | |
284 | compatible = "ti,omap3-hsmmc"; | |
285 | ti,hwmods = "mmc1"; | |
286 | ti,dual-volt; | |
2c2dc545 JH |
287 | dmas = <&sdma 61>, <&sdma 62>; |
288 | dma-names = "tx", "rx"; | |
b3431f5b RN |
289 | }; |
290 | ||
291 | mmc2: mmc@480b4000 { | |
292 | compatible = "ti,omap3-hsmmc"; | |
293 | ti,hwmods = "mmc2"; | |
2c2dc545 JH |
294 | dmas = <&sdma 47>, <&sdma 48>; |
295 | dma-names = "tx", "rx"; | |
b3431f5b RN |
296 | }; |
297 | ||
298 | mmc3: mmc@480ad000 { | |
299 | compatible = "ti,omap3-hsmmc"; | |
300 | ti,hwmods = "mmc3"; | |
2c2dc545 JH |
301 | dmas = <&sdma 77>, <&sdma 78>; |
302 | dma-names = "tx", "rx"; | |
b3431f5b | 303 | }; |
94c30732 XJ |
304 | |
305 | wdt2: wdt@48314000 { | |
306 | compatible = "ti,omap3-wdt"; | |
307 | ti,hwmods = "wd_timer2"; | |
308 | }; | |
0be484bf PU |
309 | |
310 | mcbsp1: mcbsp@48074000 { | |
311 | compatible = "ti,omap3-mcbsp"; | |
312 | reg = <0x48074000 0xff>; | |
313 | reg-names = "mpu"; | |
314 | interrupts = <16>, /* OCP compliant interrupt */ | |
315 | <59>, /* TX interrupt */ | |
316 | <60>; /* RX interrupt */ | |
317 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
318 | ti,buffer-size = <128>; |
319 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
320 | dmas = <&sdma 31>, |
321 | <&sdma 32>; | |
322 | dma-names = "tx", "rx"; | |
0be484bf PU |
323 | }; |
324 | ||
325 | mcbsp2: mcbsp@49022000 { | |
326 | compatible = "ti,omap3-mcbsp"; | |
327 | reg = <0x49022000 0xff>, | |
328 | <0x49028000 0xff>; | |
329 | reg-names = "mpu", "sidetone"; | |
330 | interrupts = <17>, /* OCP compliant interrupt */ | |
331 | <62>, /* TX interrupt */ | |
332 | <63>, /* RX interrupt */ | |
333 | <4>; /* Sidetone */ | |
334 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 335 | ti,buffer-size = <1280>; |
eef6fcaa | 336 | ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; |
4e4ead73 SG |
337 | dmas = <&sdma 33>, |
338 | <&sdma 34>; | |
339 | dma-names = "tx", "rx"; | |
0be484bf PU |
340 | }; |
341 | ||
342 | mcbsp3: mcbsp@49024000 { | |
343 | compatible = "ti,omap3-mcbsp"; | |
344 | reg = <0x49024000 0xff>, | |
345 | <0x4902a000 0xff>; | |
346 | reg-names = "mpu", "sidetone"; | |
347 | interrupts = <22>, /* OCP compliant interrupt */ | |
348 | <89>, /* TX interrupt */ | |
349 | <90>, /* RX interrupt */ | |
350 | <5>; /* Sidetone */ | |
351 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 352 | ti,buffer-size = <128>; |
eef6fcaa | 353 | ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; |
4e4ead73 SG |
354 | dmas = <&sdma 17>, |
355 | <&sdma 18>; | |
356 | dma-names = "tx", "rx"; | |
0be484bf PU |
357 | }; |
358 | ||
359 | mcbsp4: mcbsp@49026000 { | |
360 | compatible = "ti,omap3-mcbsp"; | |
361 | reg = <0x49026000 0xff>; | |
362 | reg-names = "mpu"; | |
363 | interrupts = <23>, /* OCP compliant interrupt */ | |
364 | <54>, /* TX interrupt */ | |
365 | <55>; /* RX interrupt */ | |
366 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
367 | ti,buffer-size = <128>; |
368 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
369 | dmas = <&sdma 19>, |
370 | <&sdma 20>; | |
371 | dma-names = "tx", "rx"; | |
0be484bf PU |
372 | }; |
373 | ||
374 | mcbsp5: mcbsp@48096000 { | |
375 | compatible = "ti,omap3-mcbsp"; | |
376 | reg = <0x48096000 0xff>; | |
377 | reg-names = "mpu"; | |
378 | interrupts = <27>, /* OCP compliant interrupt */ | |
379 | <81>, /* TX interrupt */ | |
380 | <82>; /* RX interrupt */ | |
381 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
382 | ti,buffer-size = <128>; |
383 | ti,hwmods = "mcbsp5"; | |
4e4ead73 SG |
384 | dmas = <&sdma 21>, |
385 | <&sdma 22>; | |
386 | dma-names = "tx", "rx"; | |
0be484bf | 387 | }; |
fab8ad0b JH |
388 | |
389 | timer1: timer@48318000 { | |
002e1ec5 | 390 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
391 | reg = <0x48318000 0x400>; |
392 | interrupts = <37>; | |
393 | ti,hwmods = "timer1"; | |
394 | ti,timer-alwon; | |
395 | }; | |
396 | ||
397 | timer2: timer@49032000 { | |
002e1ec5 | 398 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
399 | reg = <0x49032000 0x400>; |
400 | interrupts = <38>; | |
401 | ti,hwmods = "timer2"; | |
402 | }; | |
403 | ||
404 | timer3: timer@49034000 { | |
002e1ec5 | 405 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
406 | reg = <0x49034000 0x400>; |
407 | interrupts = <39>; | |
408 | ti,hwmods = "timer3"; | |
409 | }; | |
410 | ||
411 | timer4: timer@49036000 { | |
002e1ec5 | 412 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
413 | reg = <0x49036000 0x400>; |
414 | interrupts = <40>; | |
415 | ti,hwmods = "timer4"; | |
416 | }; | |
417 | ||
418 | timer5: timer@49038000 { | |
002e1ec5 | 419 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
420 | reg = <0x49038000 0x400>; |
421 | interrupts = <41>; | |
422 | ti,hwmods = "timer5"; | |
423 | ti,timer-dsp; | |
424 | }; | |
425 | ||
426 | timer6: timer@4903a000 { | |
002e1ec5 | 427 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
428 | reg = <0x4903a000 0x400>; |
429 | interrupts = <42>; | |
430 | ti,hwmods = "timer6"; | |
431 | ti,timer-dsp; | |
432 | }; | |
433 | ||
434 | timer7: timer@4903c000 { | |
002e1ec5 | 435 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
436 | reg = <0x4903c000 0x400>; |
437 | interrupts = <43>; | |
438 | ti,hwmods = "timer7"; | |
439 | ti,timer-dsp; | |
440 | }; | |
441 | ||
442 | timer8: timer@4903e000 { | |
002e1ec5 | 443 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
444 | reg = <0x4903e000 0x400>; |
445 | interrupts = <44>; | |
446 | ti,hwmods = "timer8"; | |
447 | ti,timer-pwm; | |
448 | ti,timer-dsp; | |
449 | }; | |
450 | ||
451 | timer9: timer@49040000 { | |
002e1ec5 | 452 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
453 | reg = <0x49040000 0x400>; |
454 | interrupts = <45>; | |
455 | ti,hwmods = "timer9"; | |
456 | ti,timer-pwm; | |
457 | }; | |
458 | ||
459 | timer10: timer@48086000 { | |
002e1ec5 | 460 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
461 | reg = <0x48086000 0x400>; |
462 | interrupts = <46>; | |
463 | ti,hwmods = "timer10"; | |
464 | ti,timer-pwm; | |
465 | }; | |
466 | ||
467 | timer11: timer@48088000 { | |
002e1ec5 | 468 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
469 | reg = <0x48088000 0x400>; |
470 | interrupts = <47>; | |
471 | ti,hwmods = "timer11"; | |
472 | ti,timer-pwm; | |
473 | }; | |
474 | ||
475 | timer12: timer@48304000 { | |
002e1ec5 | 476 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
477 | reg = <0x48304000 0x400>; |
478 | interrupts = <95>; | |
479 | ti,hwmods = "timer12"; | |
480 | ti,timer-alwon; | |
481 | ti,timer-secure; | |
482 | }; | |
af3eb366 RQ |
483 | |
484 | usbhstll: usbhstll@48062000 { | |
485 | compatible = "ti,usbhs-tll"; | |
486 | reg = <0x48062000 0x1000>; | |
487 | interrupts = <78>; | |
488 | ti,hwmods = "usb_tll_hs"; | |
489 | }; | |
490 | ||
491 | usbhshost: usbhshost@48064000 { | |
492 | compatible = "ti,usbhs-host"; | |
493 | reg = <0x48064000 0x400>; | |
494 | ti,hwmods = "usb_host_hs"; | |
495 | #address-cells = <1>; | |
496 | #size-cells = <1>; | |
497 | ranges; | |
498 | ||
499 | usbhsohci: ohci@48064400 { | |
500 | compatible = "ti,ohci-omap3", "usb-ohci"; | |
501 | reg = <0x48064400 0x400>; | |
502 | interrupt-parent = <&intc>; | |
503 | interrupts = <76>; | |
504 | }; | |
505 | ||
506 | usbhsehci: ehci@48064800 { | |
507 | compatible = "ti,ehci-omap", "usb-ehci"; | |
508 | reg = <0x48064800 0x400>; | |
509 | interrupt-parent = <&intc>; | |
510 | interrupts = <77>; | |
511 | }; | |
512 | }; | |
513 | ||
6e8489df FV |
514 | gpmc: gpmc@6e000000 { |
515 | compatible = "ti,omap3430-gpmc"; | |
516 | ti,hwmods = "gpmc"; | |
41644e75 | 517 | reg = <0x6e000000 0x02d0>; |
6e8489df FV |
518 | interrupts = <20>; |
519 | gpmc,num-cs = <8>; | |
520 | gpmc,num-waitpins = <4>; | |
521 | #address-cells = <2>; | |
522 | #size-cells = <1>; | |
523 | }; | |
ad871c10 KVA |
524 | |
525 | usb_otg_hs: usb_otg_hs@480ab000 { | |
526 | compatible = "ti,omap3-musb"; | |
527 | reg = <0x480ab000 0x1000>; | |
304e71e0 | 528 | interrupts = <92>, <93>; |
ad871c10 KVA |
529 | interrupt-names = "mc", "dma"; |
530 | ti,hwmods = "usb_otg_hs"; | |
ad871c10 KVA |
531 | multipoint = <1>; |
532 | num-eps = <16>; | |
533 | ram-bits = <12>; | |
534 | }; | |
189892f4 BC |
535 | }; |
536 | }; |