Commit | Line | Data |
---|---|---|
189892f4 BC |
1 | /* |
2 | * Device Tree Source for OMAP3 SoC | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
13 | / { | |
14 | compatible = "ti,omap3430", "ti,omap3"; | |
4c94ac29 | 15 | interrupt-parent = <&intc>; |
189892f4 | 16 | |
cf3c79de RN |
17 | aliases { |
18 | serial0 = &uart1; | |
19 | serial1 = &uart2; | |
20 | serial2 = &uart3; | |
cf3c79de RN |
21 | }; |
22 | ||
476b679a BC |
23 | cpus { |
24 | cpu@0 { | |
25 | compatible = "arm,cortex-a8"; | |
26 | }; | |
27 | }; | |
28 | ||
9b07b477 JH |
29 | pmu { |
30 | compatible = "arm,cortex-a8-pmu"; | |
31 | interrupts = <3>; | |
32 | ti,hwmods = "debugss"; | |
33 | }; | |
34 | ||
189892f4 BC |
35 | /* |
36 | * The soc node represents the soc top level view. It is uses for IPs | |
37 | * that are not memory mapped in the MPU view or for the MPU itself. | |
38 | */ | |
39 | soc { | |
40 | compatible = "ti,omap-infra"; | |
476b679a BC |
41 | mpu { |
42 | compatible = "ti,omap3-mpu"; | |
43 | ti,hwmods = "mpu"; | |
44 | }; | |
45 | ||
46 | iva { | |
47 | compatible = "ti,iva2.2"; | |
48 | ti,hwmods = "iva"; | |
49 | ||
50 | dsp { | |
51 | compatible = "ti,omap3-c64"; | |
52 | }; | |
53 | }; | |
189892f4 BC |
54 | }; |
55 | ||
56 | /* | |
57 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
58 | * The real OMAP interconnect network is quite complex. | |
59 | * Since that will not bring real advantage to represent that in DT for | |
60 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
61 | * hierarchy. | |
62 | */ | |
63 | ocp { | |
64 | compatible = "simple-bus"; | |
65 | #address-cells = <1>; | |
66 | #size-cells = <1>; | |
67 | ranges; | |
68 | ti,hwmods = "l3_main"; | |
69 | ||
510c0ffd JH |
70 | counter32k: counter@48320000 { |
71 | compatible = "ti,omap-counter32k"; | |
72 | reg = <0x48320000 0x20>; | |
73 | ti,hwmods = "counter_32k"; | |
74 | }; | |
75 | ||
d65c5423 BC |
76 | intc: interrupt-controller@48200000 { |
77 | compatible = "ti,omap2-intc"; | |
189892f4 BC |
78 | interrupt-controller; |
79 | #interrupt-cells = <1>; | |
d65c5423 BC |
80 | ti,intc-size = <96>; |
81 | reg = <0x48200000 0x1000>; | |
189892f4 | 82 | }; |
cf3c79de | 83 | |
2c2dc545 JH |
84 | sdma: dma-controller@48056000 { |
85 | compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; | |
86 | reg = <0x48056000 0x1000>; | |
87 | interrupts = <12>, | |
88 | <13>, | |
89 | <14>, | |
90 | <15>; | |
91 | #dma-cells = <1>; | |
92 | #dma-channels = <32>; | |
93 | #dma-requests = <96>; | |
94 | }; | |
95 | ||
679e3310 TL |
96 | omap3_pmx_core: pinmux@48002030 { |
97 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
98 | reg = <0x48002030 0x05cc>; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <0>; | |
101 | pinctrl-single,register-width = <16>; | |
102 | pinctrl-single,function-mask = <0x7fff>; | |
103 | }; | |
104 | ||
105 | omap3_pmx_wkup: pinmux@0x48002a58 { | |
106 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
107 | reg = <0x48002a58 0x5c>; | |
108 | #address-cells = <1>; | |
109 | #size-cells = <0>; | |
110 | pinctrl-single,register-width = <16>; | |
111 | pinctrl-single,function-mask = <0x7fff>; | |
112 | }; | |
113 | ||
385a64bb BC |
114 | gpio1: gpio@48310000 { |
115 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
116 | reg = <0x48310000 0x200>; |
117 | interrupts = <29>; | |
385a64bb BC |
118 | ti,hwmods = "gpio1"; |
119 | gpio-controller; | |
120 | #gpio-cells = <2>; | |
121 | interrupt-controller; | |
ff5c9059 | 122 | #interrupt-cells = <2>; |
385a64bb BC |
123 | }; |
124 | ||
125 | gpio2: gpio@49050000 { | |
126 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
127 | reg = <0x49050000 0x200>; |
128 | interrupts = <30>; | |
385a64bb BC |
129 | ti,hwmods = "gpio2"; |
130 | gpio-controller; | |
131 | #gpio-cells = <2>; | |
132 | interrupt-controller; | |
ff5c9059 | 133 | #interrupt-cells = <2>; |
385a64bb BC |
134 | }; |
135 | ||
136 | gpio3: gpio@49052000 { | |
137 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
138 | reg = <0x49052000 0x200>; |
139 | interrupts = <31>; | |
385a64bb BC |
140 | ti,hwmods = "gpio3"; |
141 | gpio-controller; | |
142 | #gpio-cells = <2>; | |
143 | interrupt-controller; | |
ff5c9059 | 144 | #interrupt-cells = <2>; |
385a64bb BC |
145 | }; |
146 | ||
147 | gpio4: gpio@49054000 { | |
148 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
149 | reg = <0x49054000 0x200>; |
150 | interrupts = <32>; | |
385a64bb BC |
151 | ti,hwmods = "gpio4"; |
152 | gpio-controller; | |
153 | #gpio-cells = <2>; | |
154 | interrupt-controller; | |
ff5c9059 | 155 | #interrupt-cells = <2>; |
385a64bb BC |
156 | }; |
157 | ||
158 | gpio5: gpio@49056000 { | |
159 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
160 | reg = <0x49056000 0x200>; |
161 | interrupts = <33>; | |
385a64bb BC |
162 | ti,hwmods = "gpio5"; |
163 | gpio-controller; | |
164 | #gpio-cells = <2>; | |
165 | interrupt-controller; | |
ff5c9059 | 166 | #interrupt-cells = <2>; |
385a64bb BC |
167 | }; |
168 | ||
169 | gpio6: gpio@49058000 { | |
170 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
171 | reg = <0x49058000 0x200>; |
172 | interrupts = <34>; | |
385a64bb BC |
173 | ti,hwmods = "gpio6"; |
174 | gpio-controller; | |
175 | #gpio-cells = <2>; | |
176 | interrupt-controller; | |
ff5c9059 | 177 | #interrupt-cells = <2>; |
385a64bb BC |
178 | }; |
179 | ||
19bfb76c | 180 | uart1: serial@4806a000 { |
cf3c79de RN |
181 | compatible = "ti,omap3-uart"; |
182 | ti,hwmods = "uart1"; | |
183 | clock-frequency = <48000000>; | |
184 | }; | |
185 | ||
19bfb76c | 186 | uart2: serial@4806c000 { |
cf3c79de RN |
187 | compatible = "ti,omap3-uart"; |
188 | ti,hwmods = "uart2"; | |
189 | clock-frequency = <48000000>; | |
190 | }; | |
191 | ||
19bfb76c | 192 | uart3: serial@49020000 { |
cf3c79de RN |
193 | compatible = "ti,omap3-uart"; |
194 | ti,hwmods = "uart3"; | |
195 | clock-frequency = <48000000>; | |
196 | }; | |
197 | ||
ca59a5c1 BC |
198 | i2c1: i2c@48070000 { |
199 | compatible = "ti,omap3-i2c"; | |
200 | #address-cells = <1>; | |
201 | #size-cells = <0>; | |
202 | ti,hwmods = "i2c1"; | |
203 | }; | |
204 | ||
205 | i2c2: i2c@48072000 { | |
206 | compatible = "ti,omap3-i2c"; | |
207 | #address-cells = <1>; | |
208 | #size-cells = <0>; | |
209 | ti,hwmods = "i2c2"; | |
210 | }; | |
211 | ||
212 | i2c3: i2c@48060000 { | |
213 | compatible = "ti,omap3-i2c"; | |
214 | #address-cells = <1>; | |
215 | #size-cells = <0>; | |
216 | ti,hwmods = "i2c3"; | |
217 | }; | |
fc72d248 BC |
218 | |
219 | mcspi1: spi@48098000 { | |
220 | compatible = "ti,omap2-mcspi"; | |
221 | #address-cells = <1>; | |
222 | #size-cells = <0>; | |
223 | ti,hwmods = "mcspi1"; | |
224 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
225 | dmas = <&sdma 35>, |
226 | <&sdma 36>, | |
227 | <&sdma 37>, | |
228 | <&sdma 38>, | |
229 | <&sdma 39>, | |
230 | <&sdma 40>, | |
231 | <&sdma 41>, | |
232 | <&sdma 42>; | |
233 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
234 | "tx2", "rx2", "tx3", "rx3"; | |
fc72d248 BC |
235 | }; |
236 | ||
237 | mcspi2: spi@4809a000 { | |
238 | compatible = "ti,omap2-mcspi"; | |
239 | #address-cells = <1>; | |
240 | #size-cells = <0>; | |
241 | ti,hwmods = "mcspi2"; | |
242 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
243 | dmas = <&sdma 43>, |
244 | <&sdma 44>, | |
245 | <&sdma 45>, | |
246 | <&sdma 46>; | |
247 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
248 | }; |
249 | ||
250 | mcspi3: spi@480b8000 { | |
251 | compatible = "ti,omap2-mcspi"; | |
252 | #address-cells = <1>; | |
253 | #size-cells = <0>; | |
254 | ti,hwmods = "mcspi3"; | |
255 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
256 | dmas = <&sdma 15>, |
257 | <&sdma 16>, | |
258 | <&sdma 23>, | |
259 | <&sdma 24>; | |
260 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
261 | }; |
262 | ||
263 | mcspi4: spi@480ba000 { | |
264 | compatible = "ti,omap2-mcspi"; | |
265 | #address-cells = <1>; | |
266 | #size-cells = <0>; | |
267 | ti,hwmods = "mcspi4"; | |
268 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
269 | dmas = <&sdma 70>, <&sdma 71>; |
270 | dma-names = "tx0", "rx0"; | |
fc72d248 | 271 | }; |
b3431f5b RN |
272 | |
273 | mmc1: mmc@4809c000 { | |
274 | compatible = "ti,omap3-hsmmc"; | |
275 | ti,hwmods = "mmc1"; | |
276 | ti,dual-volt; | |
2c2dc545 JH |
277 | dmas = <&sdma 61>, <&sdma 62>; |
278 | dma-names = "tx", "rx"; | |
b3431f5b RN |
279 | }; |
280 | ||
281 | mmc2: mmc@480b4000 { | |
282 | compatible = "ti,omap3-hsmmc"; | |
283 | ti,hwmods = "mmc2"; | |
2c2dc545 JH |
284 | dmas = <&sdma 47>, <&sdma 48>; |
285 | dma-names = "tx", "rx"; | |
b3431f5b RN |
286 | }; |
287 | ||
288 | mmc3: mmc@480ad000 { | |
289 | compatible = "ti,omap3-hsmmc"; | |
290 | ti,hwmods = "mmc3"; | |
2c2dc545 JH |
291 | dmas = <&sdma 77>, <&sdma 78>; |
292 | dma-names = "tx", "rx"; | |
b3431f5b | 293 | }; |
94c30732 XJ |
294 | |
295 | wdt2: wdt@48314000 { | |
296 | compatible = "ti,omap3-wdt"; | |
297 | ti,hwmods = "wd_timer2"; | |
298 | }; | |
0be484bf PU |
299 | |
300 | mcbsp1: mcbsp@48074000 { | |
301 | compatible = "ti,omap3-mcbsp"; | |
302 | reg = <0x48074000 0xff>; | |
303 | reg-names = "mpu"; | |
304 | interrupts = <16>, /* OCP compliant interrupt */ | |
305 | <59>, /* TX interrupt */ | |
306 | <60>; /* RX interrupt */ | |
307 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
308 | ti,buffer-size = <128>; |
309 | ti,hwmods = "mcbsp1"; | |
310 | }; | |
311 | ||
312 | mcbsp2: mcbsp@49022000 { | |
313 | compatible = "ti,omap3-mcbsp"; | |
314 | reg = <0x49022000 0xff>, | |
315 | <0x49028000 0xff>; | |
316 | reg-names = "mpu", "sidetone"; | |
317 | interrupts = <17>, /* OCP compliant interrupt */ | |
318 | <62>, /* TX interrupt */ | |
319 | <63>, /* RX interrupt */ | |
320 | <4>; /* Sidetone */ | |
321 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 322 | ti,buffer-size = <1280>; |
eef6fcaa | 323 | ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; |
0be484bf PU |
324 | }; |
325 | ||
326 | mcbsp3: mcbsp@49024000 { | |
327 | compatible = "ti,omap3-mcbsp"; | |
328 | reg = <0x49024000 0xff>, | |
329 | <0x4902a000 0xff>; | |
330 | reg-names = "mpu", "sidetone"; | |
331 | interrupts = <22>, /* OCP compliant interrupt */ | |
332 | <89>, /* TX interrupt */ | |
333 | <90>, /* RX interrupt */ | |
334 | <5>; /* Sidetone */ | |
335 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 336 | ti,buffer-size = <128>; |
eef6fcaa | 337 | ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; |
0be484bf PU |
338 | }; |
339 | ||
340 | mcbsp4: mcbsp@49026000 { | |
341 | compatible = "ti,omap3-mcbsp"; | |
342 | reg = <0x49026000 0xff>; | |
343 | reg-names = "mpu"; | |
344 | interrupts = <23>, /* OCP compliant interrupt */ | |
345 | <54>, /* TX interrupt */ | |
346 | <55>; /* RX interrupt */ | |
347 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
348 | ti,buffer-size = <128>; |
349 | ti,hwmods = "mcbsp4"; | |
350 | }; | |
351 | ||
352 | mcbsp5: mcbsp@48096000 { | |
353 | compatible = "ti,omap3-mcbsp"; | |
354 | reg = <0x48096000 0xff>; | |
355 | reg-names = "mpu"; | |
356 | interrupts = <27>, /* OCP compliant interrupt */ | |
357 | <81>, /* TX interrupt */ | |
358 | <82>; /* RX interrupt */ | |
359 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
360 | ti,buffer-size = <128>; |
361 | ti,hwmods = "mcbsp5"; | |
362 | }; | |
fab8ad0b JH |
363 | |
364 | timer1: timer@48318000 { | |
365 | compatible = "ti,omap2-timer"; | |
366 | reg = <0x48318000 0x400>; | |
367 | interrupts = <37>; | |
368 | ti,hwmods = "timer1"; | |
369 | ti,timer-alwon; | |
370 | }; | |
371 | ||
372 | timer2: timer@49032000 { | |
373 | compatible = "ti,omap2-timer"; | |
374 | reg = <0x49032000 0x400>; | |
375 | interrupts = <38>; | |
376 | ti,hwmods = "timer2"; | |
377 | }; | |
378 | ||
379 | timer3: timer@49034000 { | |
380 | compatible = "ti,omap2-timer"; | |
381 | reg = <0x49034000 0x400>; | |
382 | interrupts = <39>; | |
383 | ti,hwmods = "timer3"; | |
384 | }; | |
385 | ||
386 | timer4: timer@49036000 { | |
387 | compatible = "ti,omap2-timer"; | |
388 | reg = <0x49036000 0x400>; | |
389 | interrupts = <40>; | |
390 | ti,hwmods = "timer4"; | |
391 | }; | |
392 | ||
393 | timer5: timer@49038000 { | |
394 | compatible = "ti,omap2-timer"; | |
395 | reg = <0x49038000 0x400>; | |
396 | interrupts = <41>; | |
397 | ti,hwmods = "timer5"; | |
398 | ti,timer-dsp; | |
399 | }; | |
400 | ||
401 | timer6: timer@4903a000 { | |
402 | compatible = "ti,omap2-timer"; | |
403 | reg = <0x4903a000 0x400>; | |
404 | interrupts = <42>; | |
405 | ti,hwmods = "timer6"; | |
406 | ti,timer-dsp; | |
407 | }; | |
408 | ||
409 | timer7: timer@4903c000 { | |
410 | compatible = "ti,omap2-timer"; | |
411 | reg = <0x4903c000 0x400>; | |
412 | interrupts = <43>; | |
413 | ti,hwmods = "timer7"; | |
414 | ti,timer-dsp; | |
415 | }; | |
416 | ||
417 | timer8: timer@4903e000 { | |
418 | compatible = "ti,omap2-timer"; | |
419 | reg = <0x4903e000 0x400>; | |
420 | interrupts = <44>; | |
421 | ti,hwmods = "timer8"; | |
422 | ti,timer-pwm; | |
423 | ti,timer-dsp; | |
424 | }; | |
425 | ||
426 | timer9: timer@49040000 { | |
427 | compatible = "ti,omap2-timer"; | |
428 | reg = <0x49040000 0x400>; | |
429 | interrupts = <45>; | |
430 | ti,hwmods = "timer9"; | |
431 | ti,timer-pwm; | |
432 | }; | |
433 | ||
434 | timer10: timer@48086000 { | |
435 | compatible = "ti,omap2-timer"; | |
436 | reg = <0x48086000 0x400>; | |
437 | interrupts = <46>; | |
438 | ti,hwmods = "timer10"; | |
439 | ti,timer-pwm; | |
440 | }; | |
441 | ||
442 | timer11: timer@48088000 { | |
443 | compatible = "ti,omap2-timer"; | |
444 | reg = <0x48088000 0x400>; | |
445 | interrupts = <47>; | |
446 | ti,hwmods = "timer11"; | |
447 | ti,timer-pwm; | |
448 | }; | |
449 | ||
450 | timer12: timer@48304000 { | |
451 | compatible = "ti,omap2-timer"; | |
452 | reg = <0x48304000 0x400>; | |
453 | interrupts = <95>; | |
454 | ti,hwmods = "timer12"; | |
455 | ti,timer-alwon; | |
456 | ti,timer-secure; | |
457 | }; | |
af3eb366 RQ |
458 | |
459 | usbhstll: usbhstll@48062000 { | |
460 | compatible = "ti,usbhs-tll"; | |
461 | reg = <0x48062000 0x1000>; | |
462 | interrupts = <78>; | |
463 | ti,hwmods = "usb_tll_hs"; | |
464 | }; | |
465 | ||
466 | usbhshost: usbhshost@48064000 { | |
467 | compatible = "ti,usbhs-host"; | |
468 | reg = <0x48064000 0x400>; | |
469 | ti,hwmods = "usb_host_hs"; | |
470 | #address-cells = <1>; | |
471 | #size-cells = <1>; | |
472 | ranges; | |
473 | ||
474 | usbhsohci: ohci@48064400 { | |
475 | compatible = "ti,ohci-omap3", "usb-ohci"; | |
476 | reg = <0x48064400 0x400>; | |
477 | interrupt-parent = <&intc>; | |
478 | interrupts = <76>; | |
479 | }; | |
480 | ||
481 | usbhsehci: ehci@48064800 { | |
482 | compatible = "ti,ehci-omap", "usb-ehci"; | |
483 | reg = <0x48064800 0x400>; | |
484 | interrupt-parent = <&intc>; | |
485 | interrupts = <77>; | |
486 | }; | |
487 | }; | |
488 | ||
6e8489df FV |
489 | gpmc: gpmc@6e000000 { |
490 | compatible = "ti,omap3430-gpmc"; | |
491 | ti,hwmods = "gpmc"; | |
41644e75 | 492 | reg = <0x6e000000 0x02d0>; |
6e8489df FV |
493 | interrupts = <20>; |
494 | gpmc,num-cs = <8>; | |
495 | gpmc,num-waitpins = <4>; | |
496 | #address-cells = <2>; | |
497 | #size-cells = <1>; | |
498 | }; | |
ad871c10 KVA |
499 | |
500 | usb_otg_hs: usb_otg_hs@480ab000 { | |
501 | compatible = "ti,omap3-musb"; | |
502 | reg = <0x480ab000 0x1000>; | |
503 | interrupts = <0 92 0x4>, <0 93 0x4>; | |
504 | interrupt-names = "mc", "dma"; | |
505 | ti,hwmods = "usb_otg_hs"; | |
506 | usb-phy = <&usb2_phy>; | |
507 | multipoint = <1>; | |
508 | num-eps = <16>; | |
509 | ram-bits = <12>; | |
510 | }; | |
189892f4 BC |
511 | }; |
512 | }; |