[deliverable/linux.git] / arch / arm / boot / dts / omap3.dtsi

/*
 * Device Tree Source for OMAP3 SoC
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap3430", "ti,omap3";

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a8";
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};

		iva {
			compatible = "ti,iva2.2";
			ti,hwmods = "iva";

			dsp {
				compatible = "ti,omap3-c64";
			};
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		intc: interrupt-controller@48200000 {
			compatible = "ti,omap2-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <96>;
			reg = <0x48200000 0x1000>;
		};

		gpio1: gpio@48310000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@49050000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@49052000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@49054000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@49056000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@49058000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@49020000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@49042000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap3-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap3-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap3-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
		};
	};
};
Commit	Line	Data
189892f4 BC	1	/*
	2	* Device Tree Source for OMAP3 SoC
	3	*
	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	/include/ "skeleton.dtsi"
	12
	13	/ {
	14	compatible = "ti,omap3430", "ti,omap3";
	15
cf3c79de RN	16	aliases {
	17	serial0 = &uart1;
	18	serial1 = &uart2;
	19	serial2 = &uart3;
	20	serial3 = &uart4;
	21	};
	22
476b679a BC	23	cpus {
	24	cpu@0 {
	25	compatible = "arm,cortex-a8";
	26	};
	27	};
	28
189892f4 BC	29	/*
	30	* The soc node represents the soc top level view. It is uses for IPs
	31	* that are not memory mapped in the MPU view or for the MPU itself.
	32	*/
	33	soc {
	34	compatible = "ti,omap-infra";
476b679a BC	35	mpu {
	36	compatible = "ti,omap3-mpu";
	37	ti,hwmods = "mpu";
	38	};
	39
	40	iva {
	41	compatible = "ti,iva2.2";
	42	ti,hwmods = "iva";
	43
	44	dsp {
	45	compatible = "ti,omap3-c64";
	46	};
	47	};
189892f4 BC	48	};
	49
	50	/*
	51	* XXX: Use a flat representation of the OMAP3 interconnect.
	52	* The real OMAP interconnect network is quite complex.
	53	* Since that will not bring real advantage to represent that in DT for
	54	* the moment, just use a fake OCP bus entry to represent the whole bus
	55	* hierarchy.
	56	*/
	57	ocp {
	58	compatible = "simple-bus";
	59	#address-cells = <1>;
	60	#size-cells = <1>;
	61	ranges;
	62	ti,hwmods = "l3_main";
	63
d65c5423 BC	64	intc: interrupt-controller@48200000 {
d65c5423 BC	65	compatible = "ti,omap2-intc";
189892f4 BC	66	interrupt-controller;
189892f4 BC	67	#interrupt-cells = <1>;
d65c5423 BC	68	ti,intc-size = <96>;
d65c5423 BC	69	reg = <0x48200000 0x1000>;
189892f4	70	};
cf3c79de	71
385a64bb BC	72	gpio1: gpio@48310000 {
	73	compatible = "ti,omap3-gpio";
	74	ti,hwmods = "gpio1";
	75	gpio-controller;
	76	#gpio-cells = <2>;
	77	interrupt-controller;
	78	#interrupt-cells = <1>;
	79	};
	80
	81	gpio2: gpio@49050000 {
	82	compatible = "ti,omap3-gpio";
	83	ti,hwmods = "gpio2";
	84	gpio-controller;
	85	#gpio-cells = <2>;
	86	interrupt-controller;
	87	#interrupt-cells = <1>;
	88	};
	89
	90	gpio3: gpio@49052000 {
	91	compatible = "ti,omap3-gpio";
	92	ti,hwmods = "gpio3";
	93	gpio-controller;
	94	#gpio-cells = <2>;
	95	interrupt-controller;
	96	#interrupt-cells = <1>;
	97	};
	98
	99	gpio4: gpio@49054000 {
	100	compatible = "ti,omap3-gpio";
	101	ti,hwmods = "gpio4";
	102	gpio-controller;
	103	#gpio-cells = <2>;
	104	interrupt-controller;
	105	#interrupt-cells = <1>;
	106	};
	107
	108	gpio5: gpio@49056000 {
	109	compatible = "ti,omap3-gpio";
	110	ti,hwmods = "gpio5";
	111	gpio-controller;
	112	#gpio-cells = <2>;
	113	interrupt-controller;
	114	#interrupt-cells = <1>;
	115	};
	116
	117	gpio6: gpio@49058000 {
	118	compatible = "ti,omap3-gpio";
	119	ti,hwmods = "gpio6";
	120	gpio-controller;
	121	#gpio-cells = <2>;
	122	interrupt-controller;
	123	#interrupt-cells = <1>;
	124	};
	125
19bfb76c	126	uart1: serial@4806a000 {
cf3c79de RN	127	compatible = "ti,omap3-uart";
	128	ti,hwmods = "uart1";
	129	clock-frequency = <48000000>;
	130	};
	131
19bfb76c	132	uart2: serial@4806c000 {
cf3c79de RN	133	compatible = "ti,omap3-uart";
	134	ti,hwmods = "uart2";
	135	clock-frequency = <48000000>;
	136	};
	137
19bfb76c	138	uart3: serial@49020000 {
cf3c79de RN	139	compatible = "ti,omap3-uart";
	140	ti,hwmods = "uart3";
	141	clock-frequency = <48000000>;
	142	};
	143
19bfb76c	144	uart4: serial@49042000 {
cf3c79de RN	145	compatible = "ti,omap3-uart";
	146	ti,hwmods = "uart4";
	147	clock-frequency = <48000000>;
	148	};
ca59a5c1 BC	149
	150	i2c1: i2c@48070000 {
	151	compatible = "ti,omap3-i2c";
	152	#address-cells = <1>;
	153	#size-cells = <0>;
	154	ti,hwmods = "i2c1";
	155	};
	156
	157	i2c2: i2c@48072000 {
	158	compatible = "ti,omap3-i2c";
	159	#address-cells = <1>;
	160	#size-cells = <0>;
	161	ti,hwmods = "i2c2";
	162	};
	163
	164	i2c3: i2c@48060000 {
	165	compatible = "ti,omap3-i2c";
	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168	ti,hwmods = "i2c3";
	169	};
fc72d248 BC	170
	171	mcspi1: spi@48098000 {
	172	compatible = "ti,omap2-mcspi";
	173	#address-cells = <1>;
	174	#size-cells = <0>;
	175	ti,hwmods = "mcspi1";
	176	ti,spi-num-cs = <4>;
	177	};
	178
	179	mcspi2: spi@4809a000 {
	180	compatible = "ti,omap2-mcspi";
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183	ti,hwmods = "mcspi2";
	184	ti,spi-num-cs = <2>;
	185	};
	186
	187	mcspi3: spi@480b8000 {
	188	compatible = "ti,omap2-mcspi";
	189	#address-cells = <1>;
	190	#size-cells = <0>;
	191	ti,hwmods = "mcspi3";
	192	ti,spi-num-cs = <2>;
	193	};
	194
	195	mcspi4: spi@480ba000 {
	196	compatible = "ti,omap2-mcspi";
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	ti,hwmods = "mcspi4";
	200	ti,spi-num-cs = <1>;
	201	};
189892f4 BC	202	};
189892f4 BC	203	};