[deliverable/linux.git] / arch / arm / boot / dts / omap3.dtsi

/*
 * Device Tree Source for OMAP3 SoC
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,omap3430", "ti,omap3";
	interrupt-parent = <&intc>;

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a8";
			device_type = "cpu";
			reg = <0x0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a8-pmu";
		reg = <0x54000000 0x800000>;
		interrupts = <3>;
		ti,hwmods = "debugss";
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};

		iva {
			compatible = "ti,iva2.2";
			ti,hwmods = "iva";

			dsp {
				compatible = "ti,omap3-c64";
			};
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "simple-bus";
		reg = <0x68000000 0x10000>;
		interrupts = <9 10>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		counter32k: counter@48320000 {
			compatible = "ti,omap-counter32k";
			reg = <0x48320000 0x20>;
			ti,hwmods = "counter_32k";
		};

		intc: interrupt-controller@48200000 {
			compatible = "ti,omap2-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <96>;
			reg = <0x48200000 0x1000>;
		};

		sdma: dma-controller@48056000 {
			compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
			reg = <0x48056000 0x1000>;
			interrupts = <12>,
				     <13>,
				     <14>,
				     <15>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <96>;
		};

		omap3_pmx_core: pinmux@48002030 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x48002030 0x05cc>;
			#address-cells = <1>;
			#size-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		omap3_pmx_wkup: pinmux@48002a00 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x48002a00 0x5c>;
			#address-cells = <1>;
			#size-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		gpio1: gpio@48310000 {
			compatible = "ti,omap3-gpio";
			reg = <0x48310000 0x200>;
			interrupts = <29>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@49050000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49050000 0x200>;
			interrupts = <30>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@49052000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49052000 0x200>;
			interrupts = <31>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@49054000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49054000 0x200>;
			interrupts = <32>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@49056000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49056000 0x200>;
			interrupts = <33>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@49058000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49058000 0x200>;
			interrupts = <34>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap3-uart";
			reg = <0x4806a000 0x2000>;
			interrupts = <72>;
			dmas = <&sdma 49 &sdma 50>;
			dma-names = "tx", "rx";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap3-uart";
			reg = <0x4806c000 0x400>;
			interrupts = <73>;
			dmas = <&sdma 51 &sdma 52>;
			dma-names = "tx", "rx";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@49020000 {
			compatible = "ti,omap3-uart";
			reg = <0x49020000 0x400>;
			interrupts = <74>;
			dmas = <&sdma 53 &sdma 54>;
			dma-names = "tx", "rx";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap3-i2c";
			reg = <0x48070000 0x80>;
			interrupts = <56>;
			dmas = <&sdma 27 &sdma 28>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap3-i2c";
			reg = <0x48072000 0x80>;
			interrupts = <57>;
			dmas = <&sdma 29 &sdma 30>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap3-i2c";
			reg = <0x48060000 0x80>;
			interrupts = <61>;
			dmas = <&sdma 25 &sdma 26>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x48098000 0x100>;
			interrupts = <65>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x4809a000 0x100>;
			interrupts = <66>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x480b8000 0x100>;
			interrupts = <91>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>,
			       <&sdma 16>,
			       <&sdma 23>,
			       <&sdma 24>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x480ba000 0x100>;
			interrupts = <48>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
		};

		hdqw1w: 1w@480b2000 {
			compatible = "ti,omap3-1w";
			reg = <0x480b2000 0x1000>;
			interrupts = <58>;
			ti,hwmods = "hdq1w";
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap3-hsmmc";
			reg = <0x4809c000 0x200>;
			interrupts = <83>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap3-hsmmc";
			reg = <0x480b4000 0x200>;
			interrupts = <86>;
			ti,hwmods = "mmc2";
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap3-hsmmc";
			reg = <0x480ad000 0x200>;
			interrupts = <94>;
			ti,hwmods = "mmc3";
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		wdt2: wdt@48314000 {
			compatible = "ti,omap3-wdt";
			reg = <0x48314000 0x80>;
			ti,hwmods = "wd_timer2";
		};

		mcbsp1: mcbsp@48074000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x48074000 0xff>;
			reg-names = "mpu";
			interrupts = <16>, /* OCP compliant interrupt */
				     <59>, /* TX interrupt */
				     <60>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 31>,
			       <&sdma 32>;
			dma-names = "tx", "rx";
		};

		mcbsp2: mcbsp@49022000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49022000 0xff>,
			      <0x49028000 0xff>;
			reg-names = "mpu", "sidetone";
			interrupts = <17>, /* OCP compliant interrupt */
				     <62>, /* TX interrupt */
				     <63>, /* RX interrupt */
				     <4>;  /* Sidetone */
			interrupt-names = "common", "tx", "rx", "sidetone";
			ti,buffer-size = <1280>;
			ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
		};

		mcbsp3: mcbsp@49024000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49024000 0xff>,
			      <0x4902a000 0xff>;
			reg-names = "mpu", "sidetone";
			interrupts = <22>, /* OCP compliant interrupt */
				     <89>, /* TX interrupt */
				     <90>, /* RX interrupt */
				     <5>;  /* Sidetone */
			interrupt-names = "common", "tx", "rx", "sidetone";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
		};

		mcbsp4: mcbsp@49026000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49026000 0xff>;
			reg-names = "mpu";
			interrupts = <23>, /* OCP compliant interrupt */
				     <54>, /* TX interrupt */
				     <55>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp4";
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
		};

		mcbsp5: mcbsp@48096000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x48096000 0xff>;
			reg-names = "mpu";
			interrupts = <27>, /* OCP compliant interrupt */
				     <81>, /* TX interrupt */
				     <82>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp5";
			dmas = <&sdma 21>,
			       <&sdma 22>;
			dma-names = "tx", "rx";
		};

		timer1: timer@48318000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48318000 0x400>;
			interrupts = <37>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@49032000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49032000 0x400>;
			interrupts = <38>;
			ti,hwmods = "timer2";
		};

		timer3: timer@49034000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49034000 0x400>;
			interrupts = <39>;
			ti,hwmods = "timer3";
		};

		timer4: timer@49036000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49036000 0x400>;
			interrupts = <40>;
			ti,hwmods = "timer4";
		};

		timer5: timer@49038000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49038000 0x400>;
			interrupts = <41>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@4903a000 {
			compatible = "ti,omap3430-timer";
			reg = <0x4903a000 0x400>;
			interrupts = <42>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
		};

		timer7: timer@4903c000 {
			compatible = "ti,omap3430-timer";
			reg = <0x4903c000 0x400>;
			interrupts = <43>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4903e000 {
			compatible = "ti,omap3430-timer";
			reg = <0x4903e000 0x400>;
			interrupts = <44>;
			ti,hwmods = "timer8";
			ti,timer-pwm;
			ti,timer-dsp;
		};

		timer9: timer@49040000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49040000 0x400>;
			interrupts = <45>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48086000 0x400>;
			interrupts = <46>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48088000 0x400>;
			interrupts = <47>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		timer12: timer@48304000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48304000 0x400>;
			interrupts = <95>;
			ti,hwmods = "timer12";
			ti,timer-alwon;
			ti,timer-secure;
		};

		usbhstll: usbhstll@48062000 {
			compatible = "ti,usbhs-tll";
			reg = <0x48062000 0x1000>;
			interrupts = <78>;
			ti,hwmods = "usb_tll_hs";
		};

		usbhshost: usbhshost@48064000 {
			compatible = "ti,usbhs-host";
			reg = <0x48064000 0x400>;
			ti,hwmods = "usb_host_hs";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			usbhsohci: ohci@48064400 {
				compatible = "ti,ohci-omap3", "usb-ohci";
				reg = <0x48064400 0x400>;
				interrupt-parent = <&intc>;
				interrupts = <76>;
			};

			usbhsehci: ehci@48064800 {
				compatible = "ti,ehci-omap", "usb-ehci";
				reg = <0x48064800 0x400>;
				interrupt-parent = <&intc>;
				interrupts = <77>;
			};
		};

		gpmc: gpmc@6e000000 {
			compatible = "ti,omap3430-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x6e000000 0x02d0>;
			interrupts = <20>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		usb_otg_hs: usb_otg_hs@480ab000 {
			compatible = "ti,omap3-musb";
			reg = <0x480ab000 0x1000>;
			interrupts = <92>, <93>;
			interrupt-names = "mc", "dma";
			ti,hwmods = "usb_otg_hs";
			multipoint = <1>;
			num-eps = <16>;
			ram-bits = <12>;
		};
	};
};
Commit	Line	Data
189892f4 BC	1	/*
	2	* Device Tree Source for OMAP3 SoC
	3	*
	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
6d624eab	11	#include <dt-bindings/gpio/gpio.h>
71fdc6e4	12	#include <dt-bindings/interrupt-controller/irq.h>
bcd3cca7	13	#include <dt-bindings/pinctrl/omap.h>
6d624eab	14
98ef7957	15	#include "skeleton.dtsi"
189892f4 BC	16
	17	/ {
	18	compatible = "ti,omap3430", "ti,omap3";
4c94ac29	19	interrupt-parent = <&intc>;
189892f4	20
cf3c79de	21	aliases {
20b80942 NM	22	i2c0 = &i2c1;
	23	i2c1 = &i2c2;
	24	i2c2 = &i2c3;
cf3c79de RN	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
cf3c79de RN	28	};
cf3c79de RN	29
476b679a	30	cpus {
eeb25fd5 LP	31	#address-cells = <1>;
	32	#size-cells = <0>;
	33
476b679a BC	34	cpu@0 {
476b679a BC	35	compatible = "arm,cortex-a8";
eeb25fd5 LP	36	device_type = "cpu";
eeb25fd5 LP	37	reg = <0x0>;
476b679a BC	38	};
	39	};
	40
9b07b477 JH	41	pmu {
9b07b477 JH	42	compatible = "arm,cortex-a8-pmu";
d7c8f259	43	reg = <0x54000000 0x800000>;
9b07b477 JH	44	interrupts = <3>;
	45	ti,hwmods = "debugss";
	46	};
	47
189892f4	48	/*
161e89a6	49	* The soc node represents the soc top level view. It is used for IPs
189892f4 BC	50	* that are not memory mapped in the MPU view or for the MPU itself.
	51	*/
	52	soc {
	53	compatible = "ti,omap-infra";
476b679a BC	54	mpu {
	55	compatible = "ti,omap3-mpu";
	56	ti,hwmods = "mpu";
	57	};
	58
	59	iva {
	60	compatible = "ti,iva2.2";
	61	ti,hwmods = "iva";
	62
	63	dsp {
	64	compatible = "ti,omap3-c64";
	65	};
	66	};
189892f4 BC	67	};
	68
	69	/*
	70	* XXX: Use a flat representation of the OMAP3 interconnect.
	71	* The real OMAP interconnect network is quite complex.
	72	* Since that will not bring real advantage to represent that in DT for
	73	* the moment, just use a fake OCP bus entry to represent the whole bus
	74	* hierarchy.
	75	*/
	76	ocp {
	77	compatible = "simple-bus";
d7c8f259 TL	78	reg = <0x68000000 0x10000>;
d7c8f259 TL	79	interrupts = <9 10>;
189892f4 BC	80	#address-cells = <1>;
	81	#size-cells = <1>;
	82	ranges;
	83	ti,hwmods = "l3_main";
	84
510c0ffd JH	85	counter32k: counter@48320000 {
	86	compatible = "ti,omap-counter32k";
	87	reg = <0x48320000 0x20>;
	88	ti,hwmods = "counter_32k";
	89	};
	90
d65c5423 BC	91	intc: interrupt-controller@48200000 {
d65c5423 BC	92	compatible = "ti,omap2-intc";
189892f4 BC	93	interrupt-controller;
189892f4 BC	94	#interrupt-cells = <1>;
d65c5423 BC	95	ti,intc-size = <96>;
d65c5423 BC	96	reg = <0x48200000 0x1000>;
189892f4	97	};
cf3c79de	98
2c2dc545 JH	99	sdma: dma-controller@48056000 {
	100	compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
	101	reg = <0x48056000 0x1000>;
	102	interrupts = <12>,
	103	<13>,
	104	<14>,
	105	<15>;
	106	#dma-cells = <1>;
	107	#dma-channels = <32>;
	108	#dma-requests = <96>;
	109	};
	110
679e3310 TL	111	omap3_pmx_core: pinmux@48002030 {
	112	compatible = "ti,omap3-padconf", "pinctrl-single";
	113	reg = <0x48002030 0x05cc>;
	114	#address-cells = <1>;
	115	#size-cells = <0>;
30a69ef7 TL	116	#interrupt-cells = <1>;
30a69ef7 TL	117	interrupt-controller;
679e3310	118	pinctrl-single,register-width = <16>;
d623a0e1	119	pinctrl-single,function-mask = <0xff1f>;
679e3310 TL	120	};
679e3310 TL	121
b7317777	122	omap3_pmx_wkup: pinmux@48002a00 {
679e3310	123	compatible = "ti,omap3-padconf", "pinctrl-single";
161e89a6	124	reg = <0x48002a00 0x5c>;
679e3310 TL	125	#address-cells = <1>;
679e3310 TL	126	#size-cells = <0>;
30a69ef7 TL	127	#interrupt-cells = <1>;
30a69ef7 TL	128	interrupt-controller;
679e3310	129	pinctrl-single,register-width = <16>;
d623a0e1	130	pinctrl-single,function-mask = <0xff1f>;
679e3310 TL	131	};
679e3310 TL	132
385a64bb BC	133	gpio1: gpio@48310000 {
385a64bb BC	134	compatible = "ti,omap3-gpio";
e299185a JH	135	reg = <0x48310000 0x200>;
e299185a JH	136	interrupts = <29>;
385a64bb	137	ti,hwmods = "gpio1";
e4b9b9f3	138	ti,gpio-always-on;
385a64bb BC	139	gpio-controller;
	140	#gpio-cells = <2>;
	141	interrupt-controller;
ff5c9059	142	#interrupt-cells = <2>;
385a64bb BC	143	};
	144
	145	gpio2: gpio@49050000 {
	146	compatible = "ti,omap3-gpio";
e299185a JH	147	reg = <0x49050000 0x200>;
e299185a JH	148	interrupts = <30>;
385a64bb BC	149	ti,hwmods = "gpio2";
	150	gpio-controller;
	151	#gpio-cells = <2>;
	152	interrupt-controller;
ff5c9059	153	#interrupt-cells = <2>;
385a64bb BC	154	};
	155
	156	gpio3: gpio@49052000 {
	157	compatible = "ti,omap3-gpio";
e299185a JH	158	reg = <0x49052000 0x200>;
e299185a JH	159	interrupts = <31>;
385a64bb BC	160	ti,hwmods = "gpio3";
	161	gpio-controller;
	162	#gpio-cells = <2>;
	163	interrupt-controller;
ff5c9059	164	#interrupt-cells = <2>;
385a64bb BC	165	};
	166
	167	gpio4: gpio@49054000 {
	168	compatible = "ti,omap3-gpio";
e299185a JH	169	reg = <0x49054000 0x200>;
e299185a JH	170	interrupts = <32>;
385a64bb BC	171	ti,hwmods = "gpio4";
	172	gpio-controller;
	173	#gpio-cells = <2>;
	174	interrupt-controller;
ff5c9059	175	#interrupt-cells = <2>;
385a64bb BC	176	};
	177
	178	gpio5: gpio@49056000 {
	179	compatible = "ti,omap3-gpio";
e299185a JH	180	reg = <0x49056000 0x200>;
e299185a JH	181	interrupts = <33>;
385a64bb BC	182	ti,hwmods = "gpio5";
	183	gpio-controller;
	184	#gpio-cells = <2>;
	185	interrupt-controller;
ff5c9059	186	#interrupt-cells = <2>;
385a64bb BC	187	};
	188
	189	gpio6: gpio@49058000 {
	190	compatible = "ti,omap3-gpio";
e299185a JH	191	reg = <0x49058000 0x200>;
e299185a JH	192	interrupts = <34>;
385a64bb BC	193	ti,hwmods = "gpio6";
	194	gpio-controller;
	195	#gpio-cells = <2>;
	196	interrupt-controller;
ff5c9059	197	#interrupt-cells = <2>;
385a64bb BC	198	};
385a64bb BC	199
19bfb76c	200	uart1: serial@4806a000 {
cf3c79de	201	compatible = "ti,omap3-uart";
d7c8f259 TL	202	reg = <0x4806a000 0x2000>;
	203	interrupts = <72>;
	204	dmas = <&sdma 49 &sdma 50>;
	205	dma-names = "tx", "rx";
cf3c79de RN	206	ti,hwmods = "uart1";
	207	clock-frequency = <48000000>;
	208	};
	209
19bfb76c	210	uart2: serial@4806c000 {
cf3c79de	211	compatible = "ti,omap3-uart";
d7c8f259 TL	212	reg = <0x4806c000 0x400>;
	213	interrupts = <73>;
	214	dmas = <&sdma 51 &sdma 52>;
	215	dma-names = "tx", "rx";
cf3c79de RN	216	ti,hwmods = "uart2";
	217	clock-frequency = <48000000>;
	218	};
	219
19bfb76c	220	uart3: serial@49020000 {
cf3c79de	221	compatible = "ti,omap3-uart";
d7c8f259 TL	222	reg = <0x49020000 0x400>;
	223	interrupts = <74>;
	224	dmas = <&sdma 53 &sdma 54>;
	225	dma-names = "tx", "rx";
cf3c79de RN	226	ti,hwmods = "uart3";
	227	clock-frequency = <48000000>;
	228	};
	229
ca59a5c1 BC	230	i2c1: i2c@48070000 {
ca59a5c1 BC	231	compatible = "ti,omap3-i2c";
d7c8f259 TL	232	reg = <0x48070000 0x80>;
	233	interrupts = <56>;
	234	dmas = <&sdma 27 &sdma 28>;
	235	dma-names = "tx", "rx";
ca59a5c1 BC	236	#address-cells = <1>;
	237	#size-cells = <0>;
	238	ti,hwmods = "i2c1";
	239	};
	240
	241	i2c2: i2c@48072000 {
	242	compatible = "ti,omap3-i2c";
d7c8f259 TL	243	reg = <0x48072000 0x80>;
	244	interrupts = <57>;
	245	dmas = <&sdma 29 &sdma 30>;
	246	dma-names = "tx", "rx";
ca59a5c1 BC	247	#address-cells = <1>;
	248	#size-cells = <0>;
	249	ti,hwmods = "i2c2";
	250	};
	251
	252	i2c3: i2c@48060000 {
	253	compatible = "ti,omap3-i2c";
d7c8f259 TL	254	reg = <0x48060000 0x80>;
	255	interrupts = <61>;
	256	dmas = <&sdma 25 &sdma 26>;
	257	dma-names = "tx", "rx";
ca59a5c1 BC	258	#address-cells = <1>;
	259	#size-cells = <0>;
	260	ti,hwmods = "i2c3";
	261	};
fc72d248 BC	262
	263	mcspi1: spi@48098000 {
	264	compatible = "ti,omap2-mcspi";
d7c8f259 TL	265	reg = <0x48098000 0x100>;
d7c8f259 TL	266	interrupts = <65>;
fc72d248 BC	267	#address-cells = <1>;
	268	#size-cells = <0>;
	269	ti,hwmods = "mcspi1";
	270	ti,spi-num-cs = <4>;
2c2dc545 JH	271	dmas = <&sdma 35>,
	272	<&sdma 36>,
	273	<&sdma 37>,
	274	<&sdma 38>,
	275	<&sdma 39>,
	276	<&sdma 40>,
	277	<&sdma 41>,
	278	<&sdma 42>;
	279	dma-names = "tx0", "rx0", "tx1", "rx1",
	280	"tx2", "rx2", "tx3", "rx3";
fc72d248 BC	281	};
	282
	283	mcspi2: spi@4809a000 {
	284	compatible = "ti,omap2-mcspi";
d7c8f259 TL	285	reg = <0x4809a000 0x100>;
d7c8f259 TL	286	interrupts = <66>;
fc72d248 BC	287	#address-cells = <1>;
	288	#size-cells = <0>;
	289	ti,hwmods = "mcspi2";
	290	ti,spi-num-cs = <2>;
2c2dc545 JH	291	dmas = <&sdma 43>,
	292	<&sdma 44>,
	293	<&sdma 45>,
	294	<&sdma 46>;
	295	dma-names = "tx0", "rx0", "tx1", "rx1";
fc72d248 BC	296	};
	297
	298	mcspi3: spi@480b8000 {
	299	compatible = "ti,omap2-mcspi";
d7c8f259 TL	300	reg = <0x480b8000 0x100>;
d7c8f259 TL	301	interrupts = <91>;
fc72d248 BC	302	#address-cells = <1>;
	303	#size-cells = <0>;
	304	ti,hwmods = "mcspi3";
	305	ti,spi-num-cs = <2>;
2c2dc545 JH	306	dmas = <&sdma 15>,
	307	<&sdma 16>,
	308	<&sdma 23>,
	309	<&sdma 24>;
	310	dma-names = "tx0", "rx0", "tx1", "rx1";
fc72d248 BC	311	};
	312
	313	mcspi4: spi@480ba000 {
	314	compatible = "ti,omap2-mcspi";
d7c8f259 TL	315	reg = <0x480ba000 0x100>;
d7c8f259 TL	316	interrupts = <48>;
fc72d248 BC	317	#address-cells = <1>;
	318	#size-cells = <0>;
	319	ti,hwmods = "mcspi4";
	320	ti,spi-num-cs = <1>;
2c2dc545 JH	321	dmas = <&sdma 70>, <&sdma 71>;
2c2dc545 JH	322	dma-names = "tx0", "rx0";
fc72d248	323	};
b3431f5b	324
d7c8f259 TL	325	hdqw1w: 1w@480b2000 {
	326	compatible = "ti,omap3-1w";
	327	reg = <0x480b2000 0x1000>;
	328	interrupts = <58>;
	329	ti,hwmods = "hdq1w";
	330	};
	331
b3431f5b RN	332	mmc1: mmc@4809c000 {
b3431f5b RN	333	compatible = "ti,omap3-hsmmc";
d7c8f259 TL	334	reg = <0x4809c000 0x200>;
d7c8f259 TL	335	interrupts = <83>;
b3431f5b RN	336	ti,hwmods = "mmc1";
b3431f5b RN	337	ti,dual-volt;
2c2dc545 JH	338	dmas = <&sdma 61>, <&sdma 62>;
2c2dc545 JH	339	dma-names = "tx", "rx";
b3431f5b RN	340	};
	341
	342	mmc2: mmc@480b4000 {
	343	compatible = "ti,omap3-hsmmc";
d7c8f259 TL	344	reg = <0x480b4000 0x200>;
d7c8f259 TL	345	interrupts = <86>;
b3431f5b	346	ti,hwmods = "mmc2";
2c2dc545 JH	347	dmas = <&sdma 47>, <&sdma 48>;
2c2dc545 JH	348	dma-names = "tx", "rx";
b3431f5b RN	349	};
	350
	351	mmc3: mmc@480ad000 {
	352	compatible = "ti,omap3-hsmmc";
d7c8f259 TL	353	reg = <0x480ad000 0x200>;
d7c8f259 TL	354	interrupts = <94>;
b3431f5b	355	ti,hwmods = "mmc3";
2c2dc545 JH	356	dmas = <&sdma 77>, <&sdma 78>;
2c2dc545 JH	357	dma-names = "tx", "rx";
b3431f5b	358	};
94c30732 XJ	359
	360	wdt2: wdt@48314000 {
	361	compatible = "ti,omap3-wdt";
d7c8f259	362	reg = <0x48314000 0x80>;
94c30732 XJ	363	ti,hwmods = "wd_timer2";
94c30732 XJ	364	};
0be484bf PU	365
	366	mcbsp1: mcbsp@48074000 {
	367	compatible = "ti,omap3-mcbsp";
	368	reg = <0x48074000 0xff>;
	369	reg-names = "mpu";
	370	interrupts = <16>, /* OCP compliant interrupt */
	371	<59>, /* TX interrupt */
	372	<60>; /* RX interrupt */
	373	interrupt-names = "common", "tx", "rx";
0be484bf PU	374	ti,buffer-size = <128>;
0be484bf PU	375	ti,hwmods = "mcbsp1";
4e4ead73 SG	376	dmas = <&sdma 31>,
	377	<&sdma 32>;
	378	dma-names = "tx", "rx";
0be484bf PU	379	};
	380
	381	mcbsp2: mcbsp@49022000 {
	382	compatible = "ti,omap3-mcbsp";
	383	reg = <0x49022000 0xff>,
	384	<0x49028000 0xff>;
	385	reg-names = "mpu", "sidetone";
	386	interrupts = <17>, /* OCP compliant interrupt */
	387	<62>, /* TX interrupt */
	388	<63>, /* RX interrupt */
	389	<4>; /* Sidetone */
	390	interrupt-names = "common", "tx", "rx", "sidetone";
0be484bf	391	ti,buffer-size = <1280>;
eef6fcaa	392	ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
4e4ead73 SG	393	dmas = <&sdma 33>,
	394	<&sdma 34>;
	395	dma-names = "tx", "rx";
0be484bf PU	396	};
	397
	398	mcbsp3: mcbsp@49024000 {
	399	compatible = "ti,omap3-mcbsp";
	400	reg = <0x49024000 0xff>,
	401	<0x4902a000 0xff>;
	402	reg-names = "mpu", "sidetone";
	403	interrupts = <22>, /* OCP compliant interrupt */
	404	<89>, /* TX interrupt */
	405	<90>, /* RX interrupt */
	406	<5>; /* Sidetone */
	407	interrupt-names = "common", "tx", "rx", "sidetone";
0be484bf	408	ti,buffer-size = <128>;
eef6fcaa	409	ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
4e4ead73 SG	410	dmas = <&sdma 17>,
	411	<&sdma 18>;
	412	dma-names = "tx", "rx";
0be484bf PU	413	};
	414
	415	mcbsp4: mcbsp@49026000 {
	416	compatible = "ti,omap3-mcbsp";
	417	reg = <0x49026000 0xff>;
	418	reg-names = "mpu";
	419	interrupts = <23>, /* OCP compliant interrupt */
	420	<54>, /* TX interrupt */
	421	<55>; /* RX interrupt */
	422	interrupt-names = "common", "tx", "rx";
0be484bf PU	423	ti,buffer-size = <128>;
0be484bf PU	424	ti,hwmods = "mcbsp4";
4e4ead73 SG	425	dmas = <&sdma 19>,
	426	<&sdma 20>;
	427	dma-names = "tx", "rx";
0be484bf PU	428	};
	429
	430	mcbsp5: mcbsp@48096000 {
	431	compatible = "ti,omap3-mcbsp";
	432	reg = <0x48096000 0xff>;
	433	reg-names = "mpu";
	434	interrupts = <27>, /* OCP compliant interrupt */
	435	<81>, /* TX interrupt */
	436	<82>; /* RX interrupt */
	437	interrupt-names = "common", "tx", "rx";
0be484bf PU	438	ti,buffer-size = <128>;
0be484bf PU	439	ti,hwmods = "mcbsp5";
4e4ead73 SG	440	dmas = <&sdma 21>,
	441	<&sdma 22>;
	442	dma-names = "tx", "rx";
0be484bf	443	};
fab8ad0b JH	444
fab8ad0b JH	445	timer1: timer@48318000 {
002e1ec5	446	compatible = "ti,omap3430-timer";
fab8ad0b JH	447	reg = <0x48318000 0x400>;
	448	interrupts = <37>;
	449	ti,hwmods = "timer1";
	450	ti,timer-alwon;
	451	};
	452
	453	timer2: timer@49032000 {
002e1ec5	454	compatible = "ti,omap3430-timer";
fab8ad0b JH	455	reg = <0x49032000 0x400>;
	456	interrupts = <38>;
	457	ti,hwmods = "timer2";
	458	};
	459
	460	timer3: timer@49034000 {
002e1ec5	461	compatible = "ti,omap3430-timer";
fab8ad0b JH	462	reg = <0x49034000 0x400>;
	463	interrupts = <39>;
	464	ti,hwmods = "timer3";
	465	};
	466
	467	timer4: timer@49036000 {
002e1ec5	468	compatible = "ti,omap3430-timer";
fab8ad0b JH	469	reg = <0x49036000 0x400>;
	470	interrupts = <40>;
	471	ti,hwmods = "timer4";
	472	};
	473
	474	timer5: timer@49038000 {
002e1ec5	475	compatible = "ti,omap3430-timer";
fab8ad0b JH	476	reg = <0x49038000 0x400>;
	477	interrupts = <41>;
	478	ti,hwmods = "timer5";
	479	ti,timer-dsp;
	480	};
	481
	482	timer6: timer@4903a000 {
002e1ec5	483	compatible = "ti,omap3430-timer";
fab8ad0b JH	484	reg = <0x4903a000 0x400>;
	485	interrupts = <42>;
	486	ti,hwmods = "timer6";
	487	ti,timer-dsp;
	488	};
	489
	490	timer7: timer@4903c000 {
002e1ec5	491	compatible = "ti,omap3430-timer";
fab8ad0b JH	492	reg = <0x4903c000 0x400>;
	493	interrupts = <43>;
	494	ti,hwmods = "timer7";
	495	ti,timer-dsp;
	496	};
	497
	498	timer8: timer@4903e000 {
002e1ec5	499	compatible = "ti,omap3430-timer";
fab8ad0b JH	500	reg = <0x4903e000 0x400>;
	501	interrupts = <44>;
	502	ti,hwmods = "timer8";
	503	ti,timer-pwm;
	504	ti,timer-dsp;
	505	};
	506
	507	timer9: timer@49040000 {
002e1ec5	508	compatible = "ti,omap3430-timer";
fab8ad0b JH	509	reg = <0x49040000 0x400>;
	510	interrupts = <45>;
	511	ti,hwmods = "timer9";
	512	ti,timer-pwm;
	513	};
	514
	515	timer10: timer@48086000 {
002e1ec5	516	compatible = "ti,omap3430-timer";
fab8ad0b JH	517	reg = <0x48086000 0x400>;
	518	interrupts = <46>;
	519	ti,hwmods = "timer10";
	520	ti,timer-pwm;
	521	};
	522
	523	timer11: timer@48088000 {
002e1ec5	524	compatible = "ti,omap3430-timer";
fab8ad0b JH	525	reg = <0x48088000 0x400>;
	526	interrupts = <47>;
	527	ti,hwmods = "timer11";
	528	ti,timer-pwm;
	529	};
	530
	531	timer12: timer@48304000 {
002e1ec5	532	compatible = "ti,omap3430-timer";
fab8ad0b JH	533	reg = <0x48304000 0x400>;
	534	interrupts = <95>;
	535	ti,hwmods = "timer12";
	536	ti,timer-alwon;
	537	ti,timer-secure;
	538	};
af3eb366 RQ	539
	540	usbhstll: usbhstll@48062000 {
	541	compatible = "ti,usbhs-tll";
	542	reg = <0x48062000 0x1000>;
	543	interrupts = <78>;
	544	ti,hwmods = "usb_tll_hs";
	545	};
	546
	547	usbhshost: usbhshost@48064000 {
	548	compatible = "ti,usbhs-host";
	549	reg = <0x48064000 0x400>;
	550	ti,hwmods = "usb_host_hs";
	551	#address-cells = <1>;
	552	#size-cells = <1>;
	553	ranges;
	554
	555	usbhsohci: ohci@48064400 {
	556	compatible = "ti,ohci-omap3", "usb-ohci";
	557	reg = <0x48064400 0x400>;
	558	interrupt-parent = <&intc>;
	559	interrupts = <76>;
	560	};
	561
	562	usbhsehci: ehci@48064800 {
	563	compatible = "ti,ehci-omap", "usb-ehci";
	564	reg = <0x48064800 0x400>;
	565	interrupt-parent = <&intc>;
	566	interrupts = <77>;
	567	};
	568	};
	569
6e8489df FV	570	gpmc: gpmc@6e000000 {
	571	compatible = "ti,omap3430-gpmc";
	572	ti,hwmods = "gpmc";
41644e75	573	reg = <0x6e000000 0x02d0>;
6e8489df FV	574	interrupts = <20>;
	575	gpmc,num-cs = <8>;
	576	gpmc,num-waitpins = <4>;
	577	#address-cells = <2>;
	578	#size-cells = <1>;
	579	};
ad871c10 KVA	580
	581	usb_otg_hs: usb_otg_hs@480ab000 {
	582	compatible = "ti,omap3-musb";
	583	reg = <0x480ab000 0x1000>;
304e71e0	584	interrupts = <92>, <93>;
ad871c10 KVA	585	interrupt-names = "mc", "dma";
ad871c10 KVA	586	ti,hwmods = "usb_otg_hs";
ad871c10 KVA	587	multipoint = <1>;
	588	num-eps = <16>;
	589	ram-bits = <12>;
	590	};
189892f4 BC	591	};
189892f4 BC	592	};