projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 189892f4 BC |
1 | /* |
| 2 | * Device Tree Source for OMAP3 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | /include/ "skeleton.dtsi" | |
| 12 | ||
| 13 | / { | |
| 14 | compatible = "ti,omap3430", "ti,omap3"; | |
| 15 | ||
| cf3c79de RN |
16 | aliases { |
| 17 | serial0 = &uart1; | |
| 18 | serial1 = &uart2; | |
| 19 | serial2 = &uart3; | |
| 20 | serial3 = &uart4; | |
| 21 | }; | |
| 22 | ||
| 476b679a BC |
23 | cpus { |
| 24 | cpu@0 { | |
| 25 | compatible = "arm,cortex-a8"; | |
| 26 | }; | |
| 27 | }; | |
| 28 | ||
| 189892f4 BC |
29 | /* |
| 30 | * The soc node represents the soc top level view. It is uses for IPs | |
| 31 | * that are not memory mapped in the MPU view or for the MPU itself. | |
| 32 | */ | |
| 33 | soc { | |
| 34 | compatible = "ti,omap-infra"; | |
| 476b679a BC |
35 | mpu { |
| 36 | compatible = "ti,omap3-mpu"; | |
| 37 | ti,hwmods = "mpu"; | |
| 38 | }; | |
| 39 | ||
| 40 | iva { | |
| 41 | compatible = "ti,iva2.2"; | |
| 42 | ti,hwmods = "iva"; | |
| 43 | ||
| 44 | dsp { | |
| 45 | compatible = "ti,omap3-c64"; | |
| 46 | }; | |
| 47 | }; | |
| 189892f4 BC |
48 | }; |
| 49 | ||
| 50 | /* | |
| 51 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
| 52 | * The real OMAP interconnect network is quite complex. | |
| 53 | * Since that will not bring real advantage to represent that in DT for | |
| 54 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
| 55 | * hierarchy. | |
| 56 | */ | |
| 57 | ocp { | |
| 58 | compatible = "simple-bus"; | |
| 59 | #address-cells = <1>; | |
| 60 | #size-cells = <1>; | |
| 61 | ranges; | |
| 62 | ti,hwmods = "l3_main"; | |
| 63 | ||
| d65c5423 BC |
64 | intc: interrupt-controller@48200000 { |
| 65 | compatible = "ti,omap2-intc"; | |
| 189892f4 BC |
66 | interrupt-controller; |
| 67 | #interrupt-cells = <1>; | |
| d65c5423 BC |
68 | ti,intc-size = <96>; |
| 69 | reg = <0x48200000 0x1000>; | |
| 189892f4 | 70 | }; |
| cf3c79de | 71 | |
| 19bfb76c | 72 | uart1: serial@4806a000 { |
| cf3c79de RN |
73 | compatible = "ti,omap3-uart"; |
| 74 | ti,hwmods = "uart1"; | |
| 75 | clock-frequency = <48000000>; | |
| 76 | }; | |
| 77 | ||
| 19bfb76c | 78 | uart2: serial@4806c000 { |
| cf3c79de RN |
79 | compatible = "ti,omap3-uart"; |
| 80 | ti,hwmods = "uart2"; | |
| 81 | clock-frequency = <48000000>; | |
| 82 | }; | |
| 83 | ||
| 19bfb76c | 84 | uart3: serial@49020000 { |
| cf3c79de RN |
85 | compatible = "ti,omap3-uart"; |
| 86 | ti,hwmods = "uart3"; | |
| 87 | clock-frequency = <48000000>; | |
| 88 | }; | |
| 89 | ||
| 19bfb76c | 90 | uart4: serial@49042000 { |
| cf3c79de RN |
91 | compatible = "ti,omap3-uart"; |
| 92 | ti,hwmods = "uart4"; | |
| 93 | clock-frequency = <48000000>; | |
| 94 | }; | |
| ca59a5c1 BC |
95 | |
| 96 | i2c1: i2c@48070000 { | |
| 97 | compatible = "ti,omap3-i2c"; | |
| 98 | #address-cells = <1>; | |
| 99 | #size-cells = <0>; | |
| 100 | ti,hwmods = "i2c1"; | |
| 101 | }; | |
| 102 | ||
| 103 | i2c2: i2c@48072000 { | |
| 104 | compatible = "ti,omap3-i2c"; | |
| 105 | #address-cells = <1>; | |
| 106 | #size-cells = <0>; | |
| 107 | ti,hwmods = "i2c2"; | |
| 108 | }; | |
| 109 | ||
| 110 | i2c3: i2c@48060000 { | |
| 111 | compatible = "ti,omap3-i2c"; | |
| 112 | #address-cells = <1>; | |
| 113 | #size-cells = <0>; | |
| 114 | ti,hwmods = "i2c3"; | |
| 115 | }; | |
| 189892f4 BC |
116 | }; |
| 117 | }; |