Commit | Line | Data |
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657fc11c TK |
1 | /* |
2 | * Device Tree Source for OMAP36xx clock data | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | &cm_clocks { | |
b5b5340d | 11 | dpll4_ck: dpll4_ck@d00 { |
657fc11c TK |
12 | #clock-cells = <0>; |
13 | compatible = "ti,omap3-dpll-per-j-type-clock"; | |
14 | clocks = <&sys_ck>, <&sys_ck>; | |
15 | reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; | |
16 | }; | |
17 | ||
b5b5340d | 18 | dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { |
657fc11c TK |
19 | #clock-cells = <0>; |
20 | compatible = "ti,hsdiv-gate-clock"; | |
21 | clocks = <&dpll4_m5x2_mul_ck>; | |
22 | ti,bit-shift = <0x1e>; | |
23 | reg = <0x0d00>; | |
24 | ti,set-rate-parent; | |
25 | ti,set-bit-to-disable; | |
26 | }; | |
27 | ||
b5b5340d | 28 | dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { |
657fc11c TK |
29 | #clock-cells = <0>; |
30 | compatible = "ti,hsdiv-gate-clock"; | |
31 | clocks = <&dpll4_m2x2_mul_ck>; | |
32 | ti,bit-shift = <0x1b>; | |
33 | reg = <0x0d00>; | |
34 | ti,set-bit-to-disable; | |
35 | }; | |
36 | ||
b5b5340d | 37 | dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { |
657fc11c TK |
38 | #clock-cells = <0>; |
39 | compatible = "ti,hsdiv-gate-clock"; | |
40 | clocks = <&dpll3_m3x2_mul_ck>; | |
41 | ti,bit-shift = <0xc>; | |
42 | reg = <0x0d00>; | |
43 | ti,set-bit-to-disable; | |
44 | }; | |
45 | ||
b5b5340d | 46 | dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { |
657fc11c TK |
47 | #clock-cells = <0>; |
48 | compatible = "ti,hsdiv-gate-clock"; | |
49 | clocks = <&dpll4_m3x2_mul_ck>; | |
50 | ti,bit-shift = <0x1c>; | |
51 | reg = <0x0d00>; | |
52 | ti,set-bit-to-disable; | |
53 | }; | |
54 | ||
b5b5340d | 55 | dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { |
657fc11c TK |
56 | #clock-cells = <0>; |
57 | compatible = "ti,hsdiv-gate-clock"; | |
58 | clocks = <&dpll4_m6x2_mul_ck>; | |
59 | ti,bit-shift = <0x1f>; | |
60 | reg = <0x0d00>; | |
61 | ti,set-bit-to-disable; | |
62 | }; | |
63 | ||
b5b5340d | 64 | uart4_fck: uart4_fck@1000 { |
657fc11c TK |
65 | #clock-cells = <0>; |
66 | compatible = "ti,wait-gate-clock"; | |
67 | clocks = <&per_48m_fck>; | |
68 | reg = <0x1000>; | |
69 | ti,bit-shift = <18>; | |
70 | }; | |
71 | }; | |
72 | ||
64a900ff TV |
73 | &dpll4_m2x2_mul_ck { |
74 | clock-mult = <1>; | |
75 | }; | |
76 | ||
77 | &dpll4_m3x2_mul_ck { | |
78 | clock-mult = <1>; | |
79 | }; | |
80 | ||
81 | &dpll4_m4x2_mul_ck { | |
c368dbe2 | 82 | ti,clock-mult = <1>; |
64a900ff TV |
83 | }; |
84 | ||
85 | &dpll4_m5x2_mul_ck { | |
e21a4ea3 | 86 | ti,clock-mult = <1>; |
64a900ff TV |
87 | }; |
88 | ||
89 | &dpll4_m6x2_mul_ck { | |
90 | clock-mult = <1>; | |
91 | }; | |
92 | ||
657fc11c TK |
93 | &cm_clockdomains { |
94 | dpll4_clkdm: dpll4_clkdm { | |
95 | compatible = "ti,clockdomain"; | |
96 | clocks = <&dpll4_ck>; | |
97 | }; | |
98 | ||
99 | per_clkdm: per_clkdm { | |
100 | compatible = "ti,clockdomain"; | |
101 | clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, | |
102 | <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, | |
103 | <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, | |
104 | <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, | |
105 | <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, | |
106 | <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, | |
107 | <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, | |
108 | <&mcbsp4_ick>, <&uart4_fck>; | |
109 | }; | |
110 | }; |