Commit | Line | Data |
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642f12b4 TL |
1 | /* |
2 | * Device Tree Source for OMAP3 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
e5211763 SA |
11 | #include <dt-bindings/media/omap3-isp.h> |
12 | ||
98ef7957 | 13 | #include "omap3.dtsi" |
642f12b4 TL |
14 | |
15 | / { | |
16 | aliases { | |
17 | serial3 = &uart4; | |
18 | }; | |
19 | ||
3027e267 NM |
20 | cpus { |
21 | /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ | |
22 | cpu@0 { | |
23 | operating-points = < | |
24 | /* kHz uV */ | |
e011cf69 NM |
25 | 300000 1012500 |
26 | 600000 1200000 | |
27 | 800000 1325000 | |
3027e267 NM |
28 | >; |
29 | clock-latency = <300000>; /* From legacy driver */ | |
30 | }; | |
31 | }; | |
32 | ||
642f12b4 TL |
33 | ocp { |
34 | uart4: serial@49042000 { | |
35 | compatible = "ti,omap3-uart"; | |
d7c8f259 TL |
36 | reg = <0x49042000 0x400>; |
37 | interrupts = <80>; | |
38 | dmas = <&sdma 81 &sdma 82>; | |
39 | dma-names = "tx", "rx"; | |
642f12b4 TL |
40 | ti,hwmods = "uart4"; |
41 | clock-frequency = <48000000>; | |
42 | }; | |
3d495383 | 43 | |
b391d387 AT |
44 | abb_mpu_iva: regulator-abb-mpu { |
45 | compatible = "ti,abb-v1"; | |
46 | regulator-name = "abb_mpu_iva"; | |
47 | #address-cell = <0>; | |
48 | #size-cells = <0>; | |
49 | reg = <0x483072f0 0x8>, <0x48306818 0x4>; | |
50 | reg-names = "base-address", "int-address"; | |
51 | ti,tranxdone-status-mask = <0x4000000>; | |
52 | clocks = <&sys_ck>; | |
53 | ti,settling-time = <30>; | |
54 | ti,clock-cycles = <8>; | |
55 | ti,abb_info = < | |
56 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
57 | 1012500 0 0 0 0 0 | |
58 | 1200000 0 0 0 0 0 | |
59 | 1325000 0 0 0 0 0 | |
60 | 1375000 1 0 0 0 0 | |
61 | >; | |
62 | }; | |
63 | ||
3d495383 LP |
64 | omap3_pmx_core2: pinmux@480025a0 { |
65 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
66 | reg = <0x480025a0 0x5c>; | |
67 | #address-cells = <1>; | |
68 | #size-cells = <0>; | |
69 | #interrupt-cells = <1>; | |
70 | interrupt-controller; | |
71 | pinctrl-single,register-width = <16>; | |
72 | pinctrl-single,function-mask = <0xff1f>; | |
73 | }; | |
e5211763 SA |
74 | |
75 | isp: isp@480bc000 { | |
76 | compatible = "ti,omap3-isp"; | |
77 | reg = <0x480bc000 0x12fc | |
78 | 0x480bd800 0x0600>; | |
79 | interrupts = <24>; | |
80 | iommus = <&mmu_isp>; | |
30ecc84e | 81 | syscon = <&scm_conf 0x2f0>; |
e5211763 SA |
82 | ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; |
83 | #clock-cells = <1>; | |
84 | ports { | |
85 | #address-cells = <1>; | |
86 | #size-cells = <0>; | |
87 | }; | |
88 | }; | |
642f12b4 TL |
89 | }; |
90 | }; | |
657fc11c | 91 | |
b8a7e42b TV |
92 | /* OMAP3630 needs dss_96m_fck for VENC */ |
93 | &venc { | |
94 | clocks = <&dss_tv_fck>, <&dss_96m_fck>; | |
95 | clock-names = "fck", "tv_dac_clk"; | |
96 | }; | |
97 | ||
782e25a4 SR |
98 | &ssi { |
99 | status = "ok"; | |
100 | ||
101 | clocks = <&ssi_ssr_fck>, | |
102 | <&ssi_sst_fck>, | |
103 | <&ssi_ick>; | |
104 | clock-names = "ssi_ssr_fck", | |
105 | "ssi_sst_fck", | |
106 | "ssi_ick"; | |
107 | }; | |
108 | ||
657fc11c TK |
109 | /include/ "omap34xx-omap36xx-clocks.dtsi" |
110 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" | |
d30492ad | 111 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |
64a900ff | 112 | /include/ "omap36xx-clocks.dtsi" |