Commit | Line | Data |
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d9fda07a BC |
1 | /* |
2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
6d624eab | 9 | #include <dt-bindings/gpio/gpio.h> |
8fea7d5a | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
bcd3cca7 | 11 | #include <dt-bindings/pinctrl/omap.h> |
d9fda07a | 12 | |
98ef7957 | 13 | #include "skeleton.dtsi" |
d9fda07a BC |
14 | |
15 | / { | |
16 | compatible = "ti,omap4430", "ti,omap4"; | |
17 | interrupt-parent = <&gic>; | |
18 | ||
19 | aliases { | |
20b80942 NM |
20 | i2c0 = &i2c1; |
21 | i2c1 = &i2c2; | |
22 | i2c2 = &i2c3; | |
23 | i2c3 = &i2c4; | |
cf3c79de RN |
24 | serial0 = &uart1; |
25 | serial1 = &uart2; | |
26 | serial2 = &uart3; | |
27 | serial3 = &uart4; | |
d9fda07a BC |
28 | }; |
29 | ||
476b679a | 30 | cpus { |
eeb25fd5 LP |
31 | #address-cells = <1>; |
32 | #size-cells = <0>; | |
33 | ||
476b679a BC |
34 | cpu@0 { |
35 | compatible = "arm,cortex-a9"; | |
eeb25fd5 | 36 | device_type = "cpu"; |
926fd45b | 37 | next-level-cache = <&L2>; |
eeb25fd5 | 38 | reg = <0x0>; |
476b679a BC |
39 | }; |
40 | cpu@1 { | |
41 | compatible = "arm,cortex-a9"; | |
eeb25fd5 | 42 | device_type = "cpu"; |
926fd45b | 43 | next-level-cache = <&L2>; |
eeb25fd5 | 44 | reg = <0x1>; |
476b679a BC |
45 | }; |
46 | }; | |
47 | ||
5635121e BC |
48 | gic: interrupt-controller@48241000 { |
49 | compatible = "arm,cortex-a9-gic"; | |
50 | interrupt-controller; | |
51 | #interrupt-cells = <3>; | |
52 | reg = <0x48241000 0x1000>, | |
53 | <0x48240100 0x0100>; | |
54 | }; | |
55 | ||
926fd45b SS |
56 | L2: l2-cache-controller@48242000 { |
57 | compatible = "arm,pl310-cache"; | |
58 | reg = <0x48242000 0x1000>; | |
59 | cache-unified; | |
60 | cache-level = <2>; | |
61 | }; | |
62 | ||
75d71d46 | 63 | local-timer@48240600 { |
eed0de27 SS |
64 | compatible = "arm,cortex-a9-twd-timer"; |
65 | reg = <0x48240600 0x20>; | |
8fea7d5a | 66 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; |
eed0de27 SS |
67 | }; |
68 | ||
d9fda07a BC |
69 | /* |
70 | * The soc node represents the soc top level view. It is uses for IPs | |
71 | * that are not memory mapped in the MPU view or for the MPU itself. | |
72 | */ | |
73 | soc { | |
74 | compatible = "ti,omap-infra"; | |
476b679a BC |
75 | mpu { |
76 | compatible = "ti,omap4-mpu"; | |
77 | ti,hwmods = "mpu"; | |
78 | }; | |
79 | ||
80 | dsp { | |
81 | compatible = "ti,omap3-c64"; | |
82 | ti,hwmods = "dsp"; | |
83 | }; | |
84 | ||
85 | iva { | |
86 | compatible = "ti,ivahd"; | |
87 | ti,hwmods = "iva"; | |
88 | }; | |
d9fda07a BC |
89 | }; |
90 | ||
91 | /* | |
92 | * XXX: Use a flat representation of the OMAP4 interconnect. | |
93 | * The real OMAP interconnect network is quite complex. | |
d9fda07a BC |
94 | * Since that will not bring real advantage to represent that in DT for |
95 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
96 | * hierarchy. | |
97 | */ | |
98 | ocp { | |
ad8dfac6 | 99 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
d9fda07a BC |
100 | #address-cells = <1>; |
101 | #size-cells = <1>; | |
102 | ranges; | |
ad8dfac6 | 103 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
20a60eaa SS |
104 | reg = <0x44000000 0x1000>, |
105 | <0x44800000 0x2000>, | |
106 | <0x45000000 0x1000>; | |
8fea7d5a FV |
107 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
108 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
d9fda07a | 109 | |
2488ff6c TK |
110 | cm1: cm1@4a004000 { |
111 | compatible = "ti,omap4-cm1"; | |
112 | reg = <0x4a004000 0x2000>; | |
113 | ||
114 | cm1_clocks: clocks { | |
115 | #address-cells = <1>; | |
116 | #size-cells = <0>; | |
117 | }; | |
118 | ||
119 | cm1_clockdomains: clockdomains { | |
120 | }; | |
121 | }; | |
122 | ||
123 | prm: prm@4a306000 { | |
124 | compatible = "ti,omap4-prm"; | |
125 | reg = <0x4a306000 0x3000>; | |
126 | ||
127 | prm_clocks: clocks { | |
128 | #address-cells = <1>; | |
129 | #size-cells = <0>; | |
130 | }; | |
131 | ||
132 | prm_clockdomains: clockdomains { | |
133 | }; | |
134 | }; | |
135 | ||
136 | cm2: cm2@4a008000 { | |
137 | compatible = "ti,omap4-cm2"; | |
138 | reg = <0x4a008000 0x3000>; | |
139 | ||
140 | cm2_clocks: clocks { | |
141 | #address-cells = <1>; | |
142 | #size-cells = <0>; | |
143 | }; | |
144 | ||
145 | cm2_clockdomains: clockdomains { | |
146 | }; | |
147 | }; | |
148 | ||
149 | scrm: scrm@4a30a000 { | |
150 | compatible = "ti,omap4-scrm"; | |
151 | reg = <0x4a30a000 0x2000>; | |
152 | ||
153 | scrm_clocks: clocks { | |
154 | #address-cells = <1>; | |
155 | #size-cells = <0>; | |
156 | }; | |
157 | ||
158 | scrm_clockdomains: clockdomains { | |
159 | }; | |
160 | }; | |
161 | ||
510c0ffd JH |
162 | counter32k: counter@4a304000 { |
163 | compatible = "ti,omap-counter32k"; | |
164 | reg = <0x4a304000 0x20>; | |
165 | ti,hwmods = "counter_32k"; | |
166 | }; | |
167 | ||
679e3310 TL |
168 | omap4_pmx_core: pinmux@4a100040 { |
169 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
170 | reg = <0x4a100040 0x0196>; | |
171 | #address-cells = <1>; | |
172 | #size-cells = <0>; | |
30a69ef7 TL |
173 | #interrupt-cells = <1>; |
174 | interrupt-controller; | |
679e3310 TL |
175 | pinctrl-single,register-width = <16>; |
176 | pinctrl-single,function-mask = <0x7fff>; | |
177 | }; | |
178 | omap4_pmx_wkup: pinmux@4a31e040 { | |
179 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
180 | reg = <0x4a31e040 0x0038>; | |
181 | #address-cells = <1>; | |
182 | #size-cells = <0>; | |
30a69ef7 TL |
183 | #interrupt-cells = <1>; |
184 | interrupt-controller; | |
679e3310 TL |
185 | pinctrl-single,register-width = <16>; |
186 | pinctrl-single,function-mask = <0x7fff>; | |
187 | }; | |
188 | ||
2c2dc545 JH |
189 | sdma: dma-controller@4a056000 { |
190 | compatible = "ti,omap4430-sdma"; | |
191 | reg = <0x4a056000 0x1000>; | |
8fea7d5a FV |
192 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
193 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
194 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
195 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
2c2dc545 JH |
196 | #dma-cells = <1>; |
197 | #dma-channels = <32>; | |
198 | #dma-requests = <127>; | |
199 | }; | |
200 | ||
e3e5a92d BC |
201 | gpio1: gpio@4a310000 { |
202 | compatible = "ti,omap4-gpio"; | |
48420dbc | 203 | reg = <0x4a310000 0x200>; |
8fea7d5a | 204 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d | 205 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 206 | ti,gpio-always-on; |
e3e5a92d BC |
207 | gpio-controller; |
208 | #gpio-cells = <2>; | |
209 | interrupt-controller; | |
ff5c9059 | 210 | #interrupt-cells = <2>; |
e3e5a92d BC |
211 | }; |
212 | ||
213 | gpio2: gpio@48055000 { | |
214 | compatible = "ti,omap4-gpio"; | |
48420dbc | 215 | reg = <0x48055000 0x200>; |
8fea7d5a | 216 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
217 | ti,hwmods = "gpio2"; |
218 | gpio-controller; | |
219 | #gpio-cells = <2>; | |
220 | interrupt-controller; | |
ff5c9059 | 221 | #interrupt-cells = <2>; |
e3e5a92d BC |
222 | }; |
223 | ||
224 | gpio3: gpio@48057000 { | |
225 | compatible = "ti,omap4-gpio"; | |
48420dbc | 226 | reg = <0x48057000 0x200>; |
8fea7d5a | 227 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
228 | ti,hwmods = "gpio3"; |
229 | gpio-controller; | |
230 | #gpio-cells = <2>; | |
231 | interrupt-controller; | |
ff5c9059 | 232 | #interrupt-cells = <2>; |
e3e5a92d BC |
233 | }; |
234 | ||
235 | gpio4: gpio@48059000 { | |
236 | compatible = "ti,omap4-gpio"; | |
48420dbc | 237 | reg = <0x48059000 0x200>; |
8fea7d5a | 238 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
239 | ti,hwmods = "gpio4"; |
240 | gpio-controller; | |
241 | #gpio-cells = <2>; | |
242 | interrupt-controller; | |
ff5c9059 | 243 | #interrupt-cells = <2>; |
e3e5a92d BC |
244 | }; |
245 | ||
246 | gpio5: gpio@4805b000 { | |
247 | compatible = "ti,omap4-gpio"; | |
48420dbc | 248 | reg = <0x4805b000 0x200>; |
8fea7d5a | 249 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
250 | ti,hwmods = "gpio5"; |
251 | gpio-controller; | |
252 | #gpio-cells = <2>; | |
253 | interrupt-controller; | |
ff5c9059 | 254 | #interrupt-cells = <2>; |
e3e5a92d BC |
255 | }; |
256 | ||
257 | gpio6: gpio@4805d000 { | |
258 | compatible = "ti,omap4-gpio"; | |
48420dbc | 259 | reg = <0x4805d000 0x200>; |
8fea7d5a | 260 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
261 | ti,hwmods = "gpio6"; |
262 | gpio-controller; | |
263 | #gpio-cells = <2>; | |
264 | interrupt-controller; | |
ff5c9059 | 265 | #interrupt-cells = <2>; |
e3e5a92d | 266 | }; |
cf3c79de | 267 | |
1c7dbb55 JH |
268 | gpmc: gpmc@50000000 { |
269 | compatible = "ti,omap4430-gpmc"; | |
270 | reg = <0x50000000 0x1000>; | |
271 | #address-cells = <2>; | |
272 | #size-cells = <1>; | |
8fea7d5a | 273 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
1c7dbb55 JH |
274 | gpmc,num-cs = <8>; |
275 | gpmc,num-waitpins = <4>; | |
276 | ti,hwmods = "gpmc"; | |
f12ecbe2 | 277 | ti,no-idle-on-init; |
1c7dbb55 JH |
278 | }; |
279 | ||
19bfb76c | 280 | uart1: serial@4806a000 { |
cf3c79de | 281 | compatible = "ti,omap4-uart"; |
48420dbc | 282 | reg = <0x4806a000 0x100>; |
8fea7d5a | 283 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
284 | ti,hwmods = "uart1"; |
285 | clock-frequency = <48000000>; | |
286 | }; | |
287 | ||
19bfb76c | 288 | uart2: serial@4806c000 { |
cf3c79de | 289 | compatible = "ti,omap4-uart"; |
48420dbc | 290 | reg = <0x4806c000 0x100>; |
8fea7d5a | 291 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
292 | ti,hwmods = "uart2"; |
293 | clock-frequency = <48000000>; | |
294 | }; | |
295 | ||
19bfb76c | 296 | uart3: serial@48020000 { |
cf3c79de | 297 | compatible = "ti,omap4-uart"; |
48420dbc | 298 | reg = <0x48020000 0x100>; |
8fea7d5a | 299 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
300 | ti,hwmods = "uart3"; |
301 | clock-frequency = <48000000>; | |
302 | }; | |
303 | ||
19bfb76c | 304 | uart4: serial@4806e000 { |
cf3c79de | 305 | compatible = "ti,omap4-uart"; |
48420dbc | 306 | reg = <0x4806e000 0x100>; |
8fea7d5a | 307 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
308 | ti,hwmods = "uart4"; |
309 | clock-frequency = <48000000>; | |
310 | }; | |
58e778f9 | 311 | |
04c7d924 SA |
312 | hwspinlock: spinlock@4a0f6000 { |
313 | compatible = "ti,omap4-hwspinlock"; | |
314 | reg = <0x4a0f6000 0x1000>; | |
315 | ti,hwmods = "spinlock"; | |
316 | }; | |
317 | ||
58e778f9 BC |
318 | i2c1: i2c@48070000 { |
319 | compatible = "ti,omap4-i2c"; | |
48420dbc | 320 | reg = <0x48070000 0x100>; |
8fea7d5a | 321 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
322 | #address-cells = <1>; |
323 | #size-cells = <0>; | |
324 | ti,hwmods = "i2c1"; | |
325 | }; | |
326 | ||
327 | i2c2: i2c@48072000 { | |
328 | compatible = "ti,omap4-i2c"; | |
48420dbc | 329 | reg = <0x48072000 0x100>; |
8fea7d5a | 330 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
331 | #address-cells = <1>; |
332 | #size-cells = <0>; | |
333 | ti,hwmods = "i2c2"; | |
334 | }; | |
335 | ||
336 | i2c3: i2c@48060000 { | |
337 | compatible = "ti,omap4-i2c"; | |
48420dbc | 338 | reg = <0x48060000 0x100>; |
8fea7d5a | 339 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
340 | #address-cells = <1>; |
341 | #size-cells = <0>; | |
342 | ti,hwmods = "i2c3"; | |
343 | }; | |
344 | ||
345 | i2c4: i2c@48350000 { | |
346 | compatible = "ti,omap4-i2c"; | |
48420dbc | 347 | reg = <0x48350000 0x100>; |
8fea7d5a | 348 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
349 | #address-cells = <1>; |
350 | #size-cells = <0>; | |
351 | ti,hwmods = "i2c4"; | |
352 | }; | |
efcf1e50 BC |
353 | |
354 | mcspi1: spi@48098000 { | |
355 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 356 | reg = <0x48098000 0x200>; |
8fea7d5a | 357 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
358 | #address-cells = <1>; |
359 | #size-cells = <0>; | |
360 | ti,hwmods = "mcspi1"; | |
361 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
362 | dmas = <&sdma 35>, |
363 | <&sdma 36>, | |
364 | <&sdma 37>, | |
365 | <&sdma 38>, | |
366 | <&sdma 39>, | |
367 | <&sdma 40>, | |
368 | <&sdma 41>, | |
369 | <&sdma 42>; | |
370 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
371 | "tx2", "rx2", "tx3", "rx3"; | |
efcf1e50 BC |
372 | }; |
373 | ||
374 | mcspi2: spi@4809a000 { | |
375 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 376 | reg = <0x4809a000 0x200>; |
8fea7d5a | 377 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
378 | #address-cells = <1>; |
379 | #size-cells = <0>; | |
380 | ti,hwmods = "mcspi2"; | |
381 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
382 | dmas = <&sdma 43>, |
383 | <&sdma 44>, | |
384 | <&sdma 45>, | |
385 | <&sdma 46>; | |
386 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
efcf1e50 BC |
387 | }; |
388 | ||
389 | mcspi3: spi@480b8000 { | |
390 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 391 | reg = <0x480b8000 0x200>; |
8fea7d5a | 392 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
393 | #address-cells = <1>; |
394 | #size-cells = <0>; | |
395 | ti,hwmods = "mcspi3"; | |
396 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
397 | dmas = <&sdma 15>, <&sdma 16>; |
398 | dma-names = "tx0", "rx0"; | |
efcf1e50 BC |
399 | }; |
400 | ||
401 | mcspi4: spi@480ba000 { | |
402 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 403 | reg = <0x480ba000 0x200>; |
8fea7d5a | 404 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
405 | #address-cells = <1>; |
406 | #size-cells = <0>; | |
407 | ti,hwmods = "mcspi4"; | |
408 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
409 | dmas = <&sdma 70>, <&sdma 71>; |
410 | dma-names = "tx0", "rx0"; | |
efcf1e50 | 411 | }; |
74981768 RN |
412 | |
413 | mmc1: mmc@4809c000 { | |
414 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 415 | reg = <0x4809c000 0x400>; |
8fea7d5a | 416 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
417 | ti,hwmods = "mmc1"; |
418 | ti,dual-volt; | |
419 | ti,needs-special-reset; | |
2c2dc545 JH |
420 | dmas = <&sdma 61>, <&sdma 62>; |
421 | dma-names = "tx", "rx"; | |
74981768 RN |
422 | }; |
423 | ||
424 | mmc2: mmc@480b4000 { | |
425 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 426 | reg = <0x480b4000 0x400>; |
8fea7d5a | 427 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
428 | ti,hwmods = "mmc2"; |
429 | ti,needs-special-reset; | |
2c2dc545 JH |
430 | dmas = <&sdma 47>, <&sdma 48>; |
431 | dma-names = "tx", "rx"; | |
74981768 RN |
432 | }; |
433 | ||
434 | mmc3: mmc@480ad000 { | |
435 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 436 | reg = <0x480ad000 0x400>; |
8fea7d5a | 437 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
438 | ti,hwmods = "mmc3"; |
439 | ti,needs-special-reset; | |
2c2dc545 JH |
440 | dmas = <&sdma 77>, <&sdma 78>; |
441 | dma-names = "tx", "rx"; | |
74981768 RN |
442 | }; |
443 | ||
444 | mmc4: mmc@480d1000 { | |
445 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 446 | reg = <0x480d1000 0x400>; |
8fea7d5a | 447 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
448 | ti,hwmods = "mmc4"; |
449 | ti,needs-special-reset; | |
2c2dc545 JH |
450 | dmas = <&sdma 57>, <&sdma 58>; |
451 | dma-names = "tx", "rx"; | |
74981768 RN |
452 | }; |
453 | ||
454 | mmc5: mmc@480d5000 { | |
455 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 456 | reg = <0x480d5000 0x400>; |
8fea7d5a | 457 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
458 | ti,hwmods = "mmc5"; |
459 | ti,needs-special-reset; | |
2c2dc545 JH |
460 | dmas = <&sdma 59>, <&sdma 60>; |
461 | dma-names = "tx", "rx"; | |
74981768 | 462 | }; |
94c30732 XJ |
463 | |
464 | wdt2: wdt@4a314000 { | |
465 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | |
48420dbc | 466 | reg = <0x4a314000 0x80>; |
8fea7d5a | 467 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
94c30732 XJ |
468 | ti,hwmods = "wd_timer2"; |
469 | }; | |
4f4b5c74 PU |
470 | |
471 | mcpdm: mcpdm@40132000 { | |
472 | compatible = "ti,omap4-mcpdm"; | |
473 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
474 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 475 | reg-names = "mpu", "dma"; |
8fea7d5a | 476 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
4f4b5c74 | 477 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
478 | dmas = <&sdma 65>, |
479 | <&sdma 66>; | |
480 | dma-names = "up_link", "dn_link"; | |
4f4b5c74 | 481 | }; |
a4c38319 PU |
482 | |
483 | dmic: dmic@4012e000 { | |
484 | compatible = "ti,omap4-dmic"; | |
485 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
486 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 487 | reg-names = "mpu", "dma"; |
8fea7d5a | 488 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
a4c38319 | 489 | ti,hwmods = "dmic"; |
4e4ead73 SG |
490 | dmas = <&sdma 67>; |
491 | dma-names = "up_link"; | |
a4c38319 | 492 | }; |
61bc3544 | 493 | |
2995a100 PU |
494 | mcbsp1: mcbsp@40122000 { |
495 | compatible = "ti,omap4-mcbsp"; | |
496 | reg = <0x40122000 0xff>, /* MPU private access */ | |
497 | <0x49022000 0xff>; /* L3 Interconnect */ | |
498 | reg-names = "mpu", "dma"; | |
8fea7d5a | 499 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 500 | interrupt-names = "common"; |
2995a100 PU |
501 | ti,buffer-size = <128>; |
502 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
503 | dmas = <&sdma 33>, |
504 | <&sdma 34>; | |
505 | dma-names = "tx", "rx"; | |
2995a100 PU |
506 | }; |
507 | ||
508 | mcbsp2: mcbsp@40124000 { | |
509 | compatible = "ti,omap4-mcbsp"; | |
510 | reg = <0x40124000 0xff>, /* MPU private access */ | |
511 | <0x49024000 0xff>; /* L3 Interconnect */ | |
512 | reg-names = "mpu", "dma"; | |
8fea7d5a | 513 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 514 | interrupt-names = "common"; |
2995a100 PU |
515 | ti,buffer-size = <128>; |
516 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
517 | dmas = <&sdma 17>, |
518 | <&sdma 18>; | |
519 | dma-names = "tx", "rx"; | |
2995a100 PU |
520 | }; |
521 | ||
522 | mcbsp3: mcbsp@40126000 { | |
523 | compatible = "ti,omap4-mcbsp"; | |
524 | reg = <0x40126000 0xff>, /* MPU private access */ | |
525 | <0x49026000 0xff>; /* L3 Interconnect */ | |
526 | reg-names = "mpu", "dma"; | |
8fea7d5a | 527 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 528 | interrupt-names = "common"; |
2995a100 PU |
529 | ti,buffer-size = <128>; |
530 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
531 | dmas = <&sdma 19>, |
532 | <&sdma 20>; | |
533 | dma-names = "tx", "rx"; | |
2995a100 PU |
534 | }; |
535 | ||
536 | mcbsp4: mcbsp@48096000 { | |
537 | compatible = "ti,omap4-mcbsp"; | |
538 | reg = <0x48096000 0xff>; /* L4 Interconnect */ | |
539 | reg-names = "mpu"; | |
8fea7d5a | 540 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 541 | interrupt-names = "common"; |
2995a100 PU |
542 | ti,buffer-size = <128>; |
543 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
544 | dmas = <&sdma 31>, |
545 | <&sdma 32>; | |
546 | dma-names = "tx", "rx"; | |
2995a100 PU |
547 | }; |
548 | ||
61bc3544 SP |
549 | keypad: keypad@4a31c000 { |
550 | compatible = "ti,omap4-keypad"; | |
48420dbc | 551 | reg = <0x4a31c000 0x80>; |
8fea7d5a | 552 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
48420dbc | 553 | reg-names = "mpu"; |
61bc3544 SP |
554 | ti,hwmods = "kbd"; |
555 | }; | |
11c27069 A |
556 | |
557 | emif1: emif@4c000000 { | |
558 | compatible = "ti,emif-4d"; | |
48420dbc | 559 | reg = <0x4c000000 0x100>; |
8fea7d5a | 560 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
11c27069 | 561 | ti,hwmods = "emif1"; |
f12ecbe2 | 562 | ti,no-idle-on-init; |
11c27069 A |
563 | phy-type = <1>; |
564 | hw-caps-read-idle-ctrl; | |
565 | hw-caps-ll-interface; | |
566 | hw-caps-temp-alert; | |
567 | }; | |
568 | ||
569 | emif2: emif@4d000000 { | |
570 | compatible = "ti,emif-4d"; | |
48420dbc | 571 | reg = <0x4d000000 0x100>; |
8fea7d5a | 572 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
11c27069 | 573 | ti,hwmods = "emif2"; |
f12ecbe2 | 574 | ti,no-idle-on-init; |
11c27069 A |
575 | phy-type = <1>; |
576 | hw-caps-read-idle-ctrl; | |
577 | hw-caps-ll-interface; | |
578 | hw-caps-temp-alert; | |
579 | }; | |
8f446a7a | 580 | |
3ce0a99c | 581 | ocp2scp@4a0ad000 { |
59bafcf6 | 582 | compatible = "ti,omap-ocp2scp"; |
3ce0a99c | 583 | reg = <0x4a0ad000 0x1f>; |
59bafcf6 KVA |
584 | #address-cells = <1>; |
585 | #size-cells = <1>; | |
586 | ranges; | |
587 | ti,hwmods = "ocp2scp_usb_phy"; | |
cf0d869e KVA |
588 | usb2_phy: usb2phy@4a0ad080 { |
589 | compatible = "ti,omap-usb2"; | |
590 | reg = <0x4a0ad080 0x58>; | |
470019a4 | 591 | ctrl-module = <&omap_control_usb2phy>; |
975d963e | 592 | #phy-cells = <0>; |
cf0d869e | 593 | }; |
59bafcf6 | 594 | }; |
fab8ad0b JH |
595 | |
596 | timer1: timer@4a318000 { | |
002e1ec5 | 597 | compatible = "ti,omap3430-timer"; |
fab8ad0b | 598 | reg = <0x4a318000 0x80>; |
8fea7d5a | 599 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
600 | ti,hwmods = "timer1"; |
601 | ti,timer-alwon; | |
602 | }; | |
603 | ||
604 | timer2: timer@48032000 { | |
002e1ec5 | 605 | compatible = "ti,omap3430-timer"; |
fab8ad0b | 606 | reg = <0x48032000 0x80>; |
8fea7d5a | 607 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
608 | ti,hwmods = "timer2"; |
609 | }; | |
610 | ||
611 | timer3: timer@48034000 { | |
002e1ec5 | 612 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 613 | reg = <0x48034000 0x80>; |
8fea7d5a | 614 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
615 | ti,hwmods = "timer3"; |
616 | }; | |
617 | ||
618 | timer4: timer@48036000 { | |
002e1ec5 | 619 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 620 | reg = <0x48036000 0x80>; |
8fea7d5a | 621 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
622 | ti,hwmods = "timer4"; |
623 | }; | |
624 | ||
d03a93bb | 625 | timer5: timer@40138000 { |
002e1ec5 | 626 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
627 | reg = <0x40138000 0x80>, |
628 | <0x49038000 0x80>; | |
8fea7d5a | 629 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
630 | ti,hwmods = "timer5"; |
631 | ti,timer-dsp; | |
632 | }; | |
633 | ||
d03a93bb | 634 | timer6: timer@4013a000 { |
002e1ec5 | 635 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
636 | reg = <0x4013a000 0x80>, |
637 | <0x4903a000 0x80>; | |
8fea7d5a | 638 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
639 | ti,hwmods = "timer6"; |
640 | ti,timer-dsp; | |
641 | }; | |
642 | ||
d03a93bb | 643 | timer7: timer@4013c000 { |
002e1ec5 | 644 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
645 | reg = <0x4013c000 0x80>, |
646 | <0x4903c000 0x80>; | |
8fea7d5a | 647 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
648 | ti,hwmods = "timer7"; |
649 | ti,timer-dsp; | |
650 | }; | |
651 | ||
d03a93bb | 652 | timer8: timer@4013e000 { |
002e1ec5 | 653 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
654 | reg = <0x4013e000 0x80>, |
655 | <0x4903e000 0x80>; | |
8fea7d5a | 656 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
657 | ti,hwmods = "timer8"; |
658 | ti,timer-pwm; | |
659 | ti,timer-dsp; | |
660 | }; | |
661 | ||
662 | timer9: timer@4803e000 { | |
002e1ec5 | 663 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 664 | reg = <0x4803e000 0x80>; |
8fea7d5a | 665 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
666 | ti,hwmods = "timer9"; |
667 | ti,timer-pwm; | |
668 | }; | |
669 | ||
670 | timer10: timer@48086000 { | |
002e1ec5 | 671 | compatible = "ti,omap3430-timer"; |
fab8ad0b | 672 | reg = <0x48086000 0x80>; |
8fea7d5a | 673 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
674 | ti,hwmods = "timer10"; |
675 | ti,timer-pwm; | |
676 | }; | |
677 | ||
678 | timer11: timer@48088000 { | |
002e1ec5 | 679 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 680 | reg = <0x48088000 0x80>; |
8fea7d5a | 681 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
682 | ti,hwmods = "timer11"; |
683 | ti,timer-pwm; | |
684 | }; | |
f17c8994 RQ |
685 | |
686 | usbhstll: usbhstll@4a062000 { | |
687 | compatible = "ti,usbhs-tll"; | |
688 | reg = <0x4a062000 0x1000>; | |
8fea7d5a | 689 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
f17c8994 RQ |
690 | ti,hwmods = "usb_tll_hs"; |
691 | }; | |
692 | ||
693 | usbhshost: usbhshost@4a064000 { | |
694 | compatible = "ti,usbhs-host"; | |
695 | reg = <0x4a064000 0x800>; | |
696 | ti,hwmods = "usb_host_hs"; | |
697 | #address-cells = <1>; | |
698 | #size-cells = <1>; | |
699 | ranges; | |
700 | ||
701 | usbhsohci: ohci@4a064800 { | |
702 | compatible = "ti,ohci-omap3", "usb-ohci"; | |
703 | reg = <0x4a064800 0x400>; | |
704 | interrupt-parent = <&gic>; | |
8fea7d5a | 705 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
f17c8994 RQ |
706 | }; |
707 | ||
708 | usbhsehci: ehci@4a064c00 { | |
709 | compatible = "ti,ehci-omap", "usb-ehci"; | |
710 | reg = <0x4a064c00 0x400>; | |
711 | interrupt-parent = <&gic>; | |
8fea7d5a | 712 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
f17c8994 RQ |
713 | }; |
714 | }; | |
840e5fd8 | 715 | |
470019a4 RQ |
716 | omap_control_usb2phy: control-phy@4a002300 { |
717 | compatible = "ti,control-phy-usb2"; | |
718 | reg = <0x4a002300 0x4>; | |
719 | reg-names = "power"; | |
720 | }; | |
721 | ||
722 | omap_control_usbotg: control-phy@4a00233c { | |
723 | compatible = "ti,control-phy-otghs"; | |
724 | reg = <0x4a00233c 0x4>; | |
725 | reg-names = "otghs_control"; | |
840e5fd8 | 726 | }; |
ad871c10 KVA |
727 | |
728 | usb_otg_hs: usb_otg_hs@4a0ab000 { | |
729 | compatible = "ti,omap4-musb"; | |
730 | reg = <0x4a0ab000 0x7ff>; | |
8fea7d5a | 731 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
ad871c10 KVA |
732 | interrupt-names = "mc", "dma"; |
733 | ti,hwmods = "usb_otg_hs"; | |
734 | usb-phy = <&usb2_phy>; | |
975d963e KVA |
735 | phys = <&usb2_phy>; |
736 | phy-names = "usb2-phy"; | |
ad871c10 KVA |
737 | multipoint = <1>; |
738 | num-eps = <16>; | |
739 | ram-bits = <12>; | |
470019a4 | 740 | ctrl-module = <&omap_control_usbotg>; |
ad871c10 | 741 | }; |
dd6317df JF |
742 | |
743 | aes: aes@4b501000 { | |
744 | compatible = "ti,omap4-aes"; | |
745 | ti,hwmods = "aes"; | |
746 | reg = <0x4b501000 0xa0>; | |
747 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
748 | dmas = <&sdma 111>, <&sdma 110>; | |
749 | dma-names = "tx", "rx"; | |
750 | }; | |
806e9431 JF |
751 | |
752 | des: des@480a5000 { | |
753 | compatible = "ti,omap4-des"; | |
754 | ti,hwmods = "des"; | |
755 | reg = <0x480a5000 0xa0>; | |
756 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
757 | dmas = <&sdma 117>, <&sdma 116>; | |
758 | dma-names = "tx", "rx"; | |
759 | }; | |
d9fda07a BC |
760 | }; |
761 | }; | |
2488ff6c TK |
762 | |
763 | /include/ "omap44xx-clocks.dtsi" |