[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

/*
 * Carveout for multimedia usecases
 * It should be the last 48MB of the first 512MB memory part
 * In theory, it should not even exist. That zone should be reserved
 * dynamically during the .reserve callback.
 */
/memreserve/ 0x9d000000 0x03000000;

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
			timer {
				compatible = "arm,armv7-timer";
				/* 14th PPI IRQ, active low level-sensitive */
				interrupts = <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
			timer {
				compatible = "arm,armv7-timer";
				/* 14th PPI IRQ, active low level-sensitive */
				interrupts = <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";

		counter32k: counter@4ae04000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4ae04000 0x40>;
			ti,hwmods = "counter_32k";
		};

		omap5_pmx_core: pinmux@4a002840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a002840 0x01b6>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap5_pmx_wkup: pinmux@4ae0c840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4ae0c840 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

		gic: interrupt-controller@48211000 {
			compatible = "arm,cortex-a15-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x48211000 0x1000>,
			      <0x48212000 0x1000>;
		};

		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0 12 0x4>,
				     <0 13 0x4>,
				     <0 14 0x4>,
				     <0 15 0x4>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <127>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0 29 0x4>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0 30 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0 31 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0 32 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0 33 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0 34 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0 35 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0 121 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0 56 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0 57 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0 61 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0 62 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0 60 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0 65 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0 66 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0 91 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0 48 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <0 72 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0 73 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0 74 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0 70 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0 105 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0 106 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <0 83 0x4>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <0 86 0x4>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <0 94 0x4>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <0 96 0x4>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d5000 0x400>;
			interrupts = <0 59 0x4>;
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
			dmas = <&sdma 59>, <&sdma 60>;
			dma-names = "tx", "rx";
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			ti,hwmods = "kbd";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			ti,hwmods = "mcpdm";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			ti,hwmods = "dmic";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
		};

		timer1: timer@4ae18000 {
			compatible = "ti,omap2-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0 37 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap2-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0 38 0x4>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap2-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0 39 0x4>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap2-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0 40 0x4>;
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
			compatible = "ti,omap2-timer";
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
			interrupts = <0 41 0x4>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@4013a000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
			interrupts = <0 42 0x4>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@4013c000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
			interrupts = <0 43 0x4>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
			interrupts = <0 44 0x4>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap2-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0 45 0x4>;
			ti,hwmods = "timer9";
		};

		timer10: timer@48086000 {
			compatible = "ti,omap2-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0 46 0x4>;
			ti,hwmods = "timer10";
		};

		timer11: timer@48088000 {
			compatible = "ti,omap2-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0 47 0x4>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		emif1: emif@0x4c000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
			interrupts = <0 110 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@0x4d000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
			interrupts = <0 111 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		omap_control_usb: omap-control-usb@4a002300 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002300 0x4>,
			      <0x4a002370 0x4>;
			reg-names = "control_dev_conf", "phy_power_usb";
			ti,type = <2>;
		};

		omap_dwc3@4a020000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss";
			reg = <0x4a020000 0x1000>;
			interrupts = <0 93 4>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
			dwc3@4a030000 {
				compatible = "synopsys,dwc3";
				reg = <0x4a030000 0x1000>;
				interrupts = <0 92 4>;
				usb-phy = <&usb2_phy>, <&usb3_phy>;
				tx-fifo-resize;
			};
		};

		ocp2scp {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp1";
			usb2_phy: usb2phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
				ctrl-module = <&omap_control_usb>;
			};

			usb3_phy: usb3phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80>,
				      <0x4a084800 0x64>,
				      <0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <&omap_control_usb>;
			};
		};
	};
};
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
	10	/*
	11	* Carveout for multimedia usecases
	12	* It should be the last 48MB of the first 512MB memory part
	13	* In theory, it should not even exist. That zone should be reserved
	14	* dynamically during the .reserve callback.
	15	*/
	16	/memreserve/ 0x9d000000 0x03000000;
	17
	18	/include/ "skeleton.dtsi"
	19
	20	/ {
	21	compatible = "ti,omap5";
	22	interrupt-parent = <&gic>;
	23
	24	aliases {
	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
	28	serial3 = &uart4;
	29	serial4 = &uart5;
	30	serial5 = &uart6;
	31	};
	32
	33	cpus {
	34	cpu@0 {
	35	compatible = "arm,cortex-a15";
3c7c5dab SS	36	timer {
	37	compatible = "arm,armv7-timer";
	38	/* 14th PPI IRQ, active low level-sensitive */
	39	interrupts = <1 14 0x308>;
	40	clock-frequency = <6144000>;
	41	};
6b5de091 S	42	};
	43	cpu@1 {
	44	compatible = "arm,cortex-a15";
3c7c5dab SS	45	timer {
	46	compatible = "arm,armv7-timer";
	47	/* 14th PPI IRQ, active low level-sensitive */
	48	interrupts = <1 14 0x308>;
	49	clock-frequency = <6144000>;
	50	};
6b5de091 S	51	};
	52	};
	53
	54	/*
	55	* The soc node represents the soc top level view. It is uses for IPs
	56	* that are not memory mapped in the MPU view or for the MPU itself.
	57	*/
	58	soc {
	59	compatible = "ti,omap-infra";
	60	mpu {
	61	compatible = "ti,omap5-mpu";
	62	ti,hwmods = "mpu";
	63	};
	64	};
	65
	66	/*
	67	* XXX: Use a flat representation of the OMAP3 interconnect.
	68	* The real OMAP interconnect network is quite complex.
	69	* Since that will not bring real advantage to represent that in DT for
	70	* the moment, just use a fake OCP bus entry to represent the whole bus
	71	* hierarchy.
	72	*/
	73	ocp {
	74	compatible = "ti,omap4-l3-noc", "simple-bus";
	75	#address-cells = <1>;
	76	#size-cells = <1>;
	77	ranges;
	78	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
	79
3b3132f7 JH	80	counter32k: counter@4ae04000 {
	81	compatible = "ti,omap-counter32k";
	82	reg = <0x4ae04000 0x40>;
	83	ti,hwmods = "counter_32k";
	84	};
	85
5da6a2d5 PU	86	omap5_pmx_core: pinmux@4a002840 {
	87	compatible = "ti,omap4-padconf", "pinctrl-single";
	88	reg = <0x4a002840 0x01b6>;
	89	#address-cells = <1>;
	90	#size-cells = <0>;
	91	pinctrl-single,register-width = <16>;
	92	pinctrl-single,function-mask = <0x7fff>;
	93	};
	94	omap5_pmx_wkup: pinmux@4ae0c840 {
	95	compatible = "ti,omap4-padconf", "pinctrl-single";
	96	reg = <0x4ae0c840 0x0038>;
	97	#address-cells = <1>;
	98	#size-cells = <0>;
	99	pinctrl-single,register-width = <16>;
	100	pinctrl-single,function-mask = <0x7fff>;
	101	};
	102
6b5de091 S	103	gic: interrupt-controller@48211000 {
	104	compatible = "arm,cortex-a15-gic";
	105	interrupt-controller;
	106	#interrupt-cells = <3>;
	107	reg = <0x48211000 0x1000>,
	108	<0x48212000 0x1000>;
	109	};
	110
2c2dc545 JH	111	sdma: dma-controller@4a056000 {
	112	compatible = "ti,omap4430-sdma";
	113	reg = <0x4a056000 0x1000>;
	114	interrupts = <0 12 0x4>,
	115	<0 13 0x4>,
	116	<0 14 0x4>,
	117	<0 15 0x4>;
	118	#dma-cells = <1>;
	119	#dma-channels = <32>;
	120	#dma-requests = <127>;
	121	};
	122
6b5de091 S	123	gpio1: gpio@4ae10000 {
6b5de091 S	124	compatible = "ti,omap4-gpio";
f4b224f2 SG	125	reg = <0x4ae10000 0x200>;
f4b224f2 SG	126	interrupts = <0 29 0x4>;
6b5de091 S	127	ti,hwmods = "gpio1";
	128	gpio-controller;
	129	#gpio-cells = <2>;
	130	interrupt-controller;
	131	#interrupt-cells = <1>;
	132	};
	133
	134	gpio2: gpio@48055000 {
	135	compatible = "ti,omap4-gpio";
f4b224f2 SG	136	reg = <0x48055000 0x200>;
f4b224f2 SG	137	interrupts = <0 30 0x4>;
6b5de091 S	138	ti,hwmods = "gpio2";
	139	gpio-controller;
	140	#gpio-cells = <2>;
	141	interrupt-controller;
	142	#interrupt-cells = <1>;
	143	};
	144
	145	gpio3: gpio@48057000 {
	146	compatible = "ti,omap4-gpio";
f4b224f2 SG	147	reg = <0x48057000 0x200>;
f4b224f2 SG	148	interrupts = <0 31 0x4>;
6b5de091 S	149	ti,hwmods = "gpio3";
	150	gpio-controller;
	151	#gpio-cells = <2>;
	152	interrupt-controller;
	153	#interrupt-cells = <1>;
	154	};
	155
	156	gpio4: gpio@48059000 {
	157	compatible = "ti,omap4-gpio";
f4b224f2 SG	158	reg = <0x48059000 0x200>;
f4b224f2 SG	159	interrupts = <0 32 0x4>;
6b5de091 S	160	ti,hwmods = "gpio4";
	161	gpio-controller;
	162	#gpio-cells = <2>;
	163	interrupt-controller;
	164	#interrupt-cells = <1>;
	165	};
	166
	167	gpio5: gpio@4805b000 {
	168	compatible = "ti,omap4-gpio";
f4b224f2 SG	169	reg = <0x4805b000 0x200>;
f4b224f2 SG	170	interrupts = <0 33 0x4>;
6b5de091 S	171	ti,hwmods = "gpio5";
	172	gpio-controller;
	173	#gpio-cells = <2>;
	174	interrupt-controller;
	175	#interrupt-cells = <1>;
	176	};
	177
	178	gpio6: gpio@4805d000 {
	179	compatible = "ti,omap4-gpio";
f4b224f2 SG	180	reg = <0x4805d000 0x200>;
f4b224f2 SG	181	interrupts = <0 34 0x4>;
6b5de091 S	182	ti,hwmods = "gpio6";
	183	gpio-controller;
	184	#gpio-cells = <2>;
	185	interrupt-controller;
	186	#interrupt-cells = <1>;
	187	};
	188
	189	gpio7: gpio@48051000 {
	190	compatible = "ti,omap4-gpio";
f4b224f2 SG	191	reg = <0x48051000 0x200>;
f4b224f2 SG	192	interrupts = <0 35 0x4>;
6b5de091 S	193	ti,hwmods = "gpio7";
	194	gpio-controller;
	195	#gpio-cells = <2>;
	196	interrupt-controller;
	197	#interrupt-cells = <1>;
	198	};
	199
	200	gpio8: gpio@48053000 {
	201	compatible = "ti,omap4-gpio";
f4b224f2 SG	202	reg = <0x48053000 0x200>;
f4b224f2 SG	203	interrupts = <0 121 0x4>;
6b5de091 S	204	ti,hwmods = "gpio8";
	205	gpio-controller;
	206	#gpio-cells = <2>;
	207	interrupt-controller;
	208	#interrupt-cells = <1>;
	209	};
	210
6e6a9a50 SP	211	i2c1: i2c@48070000 {
6e6a9a50 SP	212	compatible = "ti,omap4-i2c";
d7118bbd SG	213	reg = <0x48070000 0x100>;
d7118bbd SG	214	interrupts = <0 56 0x4>;
6e6a9a50 SP	215	#address-cells = <1>;
	216	#size-cells = <0>;
	217	ti,hwmods = "i2c1";
	218	};
	219
	220	i2c2: i2c@48072000 {
	221	compatible = "ti,omap4-i2c";
d7118bbd SG	222	reg = <0x48072000 0x100>;
d7118bbd SG	223	interrupts = <0 57 0x4>;
6e6a9a50 SP	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	ti,hwmods = "i2c2";
	227	};
	228
	229	i2c3: i2c@48060000 {
	230	compatible = "ti,omap4-i2c";
d7118bbd SG	231	reg = <0x48060000 0x100>;
d7118bbd SG	232	interrupts = <0 61 0x4>;
6e6a9a50 SP	233	#address-cells = <1>;
	234	#size-cells = <0>;
	235	ti,hwmods = "i2c3";
	236	};
	237
d7118bbd	238	i2c4: i2c@4807a000 {
6e6a9a50	239	compatible = "ti,omap4-i2c";
d7118bbd SG	240	reg = <0x4807a000 0x100>;
d7118bbd SG	241	interrupts = <0 62 0x4>;
6e6a9a50 SP	242	#address-cells = <1>;
	243	#size-cells = <0>;
	244	ti,hwmods = "i2c4";
	245	};
	246
d7118bbd	247	i2c5: i2c@4807c000 {
6e6a9a50	248	compatible = "ti,omap4-i2c";
d7118bbd SG	249	reg = <0x4807c000 0x100>;
d7118bbd SG	250	interrupts = <0 60 0x4>;
6e6a9a50 SP	251	#address-cells = <1>;
	252	#size-cells = <0>;
	253	ti,hwmods = "i2c5";
	254	};
	255
43286b11 FB	256	mcspi1: spi@48098000 {
	257	compatible = "ti,omap4-mcspi";
	258	reg = <0x48098000 0x200>;
	259	interrupts = <0 65 0x4>;
	260	#address-cells = <1>;
	261	#size-cells = <0>;
	262	ti,hwmods = "mcspi1";
	263	ti,spi-num-cs = <4>;
2c2dc545 JH	264	dmas = <&sdma 35>,
	265	<&sdma 36>,
	266	<&sdma 37>,
	267	<&sdma 38>,
	268	<&sdma 39>,
	269	<&sdma 40>,
	270	<&sdma 41>,
	271	<&sdma 42>;
	272	dma-names = "tx0", "rx0", "tx1", "rx1",
	273	"tx2", "rx2", "tx3", "rx3";
43286b11 FB	274	};
	275
	276	mcspi2: spi@4809a000 {
	277	compatible = "ti,omap4-mcspi";
	278	reg = <0x4809a000 0x200>;
	279	interrupts = <0 66 0x4>;
	280	#address-cells = <1>;
	281	#size-cells = <0>;
	282	ti,hwmods = "mcspi2";
	283	ti,spi-num-cs = <2>;
2c2dc545 JH	284	dmas = <&sdma 43>,
	285	<&sdma 44>,
	286	<&sdma 45>,
	287	<&sdma 46>;
	288	dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11 FB	289	};
	290
	291	mcspi3: spi@480b8000 {
	292	compatible = "ti,omap4-mcspi";
	293	reg = <0x480b8000 0x200>;
	294	interrupts = <0 91 0x4>;
	295	#address-cells = <1>;
	296	#size-cells = <0>;
	297	ti,hwmods = "mcspi3";
	298	ti,spi-num-cs = <2>;
2c2dc545 JH	299	dmas = <&sdma 15>, <&sdma 16>;
2c2dc545 JH	300	dma-names = "tx0", "rx0";
43286b11 FB	301	};
	302
	303	mcspi4: spi@480ba000 {
	304	compatible = "ti,omap4-mcspi";
	305	reg = <0x480ba000 0x200>;
	306	interrupts = <0 48 0x4>;
	307	#address-cells = <1>;
	308	#size-cells = <0>;
	309	ti,hwmods = "mcspi4";
	310	ti,spi-num-cs = <1>;
2c2dc545 JH	311	dmas = <&sdma 70>, <&sdma 71>;
2c2dc545 JH	312	dma-names = "tx0", "rx0";
43286b11 FB	313	};
43286b11 FB	314
6b5de091 S	315	uart1: serial@4806a000 {
6b5de091 S	316	compatible = "ti,omap4-uart";
8e80f660 SG	317	reg = <0x4806a000 0x100>;
8e80f660 SG	318	interrupts = <0 72 0x4>;
6b5de091 S	319	ti,hwmods = "uart1";
	320	clock-frequency = <48000000>;
	321	};
	322
	323	uart2: serial@4806c000 {
	324	compatible = "ti,omap4-uart";
8e80f660 SG	325	reg = <0x4806c000 0x100>;
8e80f660 SG	326	interrupts = <0 73 0x4>;
6b5de091 S	327	ti,hwmods = "uart2";
	328	clock-frequency = <48000000>;
	329	};
	330
	331	uart3: serial@48020000 {
	332	compatible = "ti,omap4-uart";
8e80f660 SG	333	reg = <0x48020000 0x100>;
8e80f660 SG	334	interrupts = <0 74 0x4>;
6b5de091 S	335	ti,hwmods = "uart3";
	336	clock-frequency = <48000000>;
	337	};
	338
	339	uart4: serial@4806e000 {
	340	compatible = "ti,omap4-uart";
8e80f660 SG	341	reg = <0x4806e000 0x100>;
8e80f660 SG	342	interrupts = <0 70 0x4>;
6b5de091 S	343	ti,hwmods = "uart4";
	344	clock-frequency = <48000000>;
	345	};
	346
	347	uart5: serial@48066000 {
8e80f660 SG	348	compatible = "ti,omap4-uart";
	349	reg = <0x48066000 0x100>;
	350	interrupts = <0 105 0x4>;
6b5de091 S	351	ti,hwmods = "uart5";
	352	clock-frequency = <48000000>;
	353	};
	354
	355	uart6: serial@48068000 {
8e80f660 SG	356	compatible = "ti,omap4-uart";
	357	reg = <0x48068000 0x100>;
	358	interrupts = <0 106 0x4>;
6b5de091 S	359	ti,hwmods = "uart6";
	360	clock-frequency = <48000000>;
	361	};
5dd18b01 B	362
	363	mmc1: mmc@4809c000 {
	364	compatible = "ti,omap4-hsmmc";
9a642362 SG	365	reg = <0x4809c000 0x400>;
9a642362 SG	366	interrupts = <0 83 0x4>;
5dd18b01 B	367	ti,hwmods = "mmc1";
	368	ti,dual-volt;
	369	ti,needs-special-reset;
2c2dc545 JH	370	dmas = <&sdma 61>, <&sdma 62>;
2c2dc545 JH	371	dma-names = "tx", "rx";
5dd18b01 B	372	};
	373
	374	mmc2: mmc@480b4000 {
	375	compatible = "ti,omap4-hsmmc";
9a642362 SG	376	reg = <0x480b4000 0x400>;
9a642362 SG	377	interrupts = <0 86 0x4>;
5dd18b01 B	378	ti,hwmods = "mmc2";
5dd18b01 B	379	ti,needs-special-reset;
2c2dc545 JH	380	dmas = <&sdma 47>, <&sdma 48>;
2c2dc545 JH	381	dma-names = "tx", "rx";
5dd18b01 B	382	};
	383
	384	mmc3: mmc@480ad000 {
	385	compatible = "ti,omap4-hsmmc";
9a642362 SG	386	reg = <0x480ad000 0x400>;
9a642362 SG	387	interrupts = <0 94 0x4>;
5dd18b01 B	388	ti,hwmods = "mmc3";
5dd18b01 B	389	ti,needs-special-reset;
2c2dc545 JH	390	dmas = <&sdma 77>, <&sdma 78>;
2c2dc545 JH	391	dma-names = "tx", "rx";
5dd18b01 B	392	};
	393
	394	mmc4: mmc@480d1000 {
	395	compatible = "ti,omap4-hsmmc";
9a642362 SG	396	reg = <0x480d1000 0x400>;
9a642362 SG	397	interrupts = <0 96 0x4>;
5dd18b01 B	398	ti,hwmods = "mmc4";
5dd18b01 B	399	ti,needs-special-reset;
2c2dc545 JH	400	dmas = <&sdma 57>, <&sdma 58>;
2c2dc545 JH	401	dma-names = "tx", "rx";
5dd18b01 B	402	};
	403
	404	mmc5: mmc@480d5000 {
	405	compatible = "ti,omap4-hsmmc";
9a642362 SG	406	reg = <0x480d5000 0x400>;
9a642362 SG	407	interrupts = <0 59 0x4>;
5dd18b01 B	408	ti,hwmods = "mmc5";
5dd18b01 B	409	ti,needs-special-reset;
2c2dc545 JH	410	dmas = <&sdma 59>, <&sdma 60>;
2c2dc545 JH	411	dma-names = "tx", "rx";
5dd18b01	412	};
5449fbc2 SP	413
	414	keypad: keypad@4ae1c000 {
	415	compatible = "ti,omap4-keypad";
	416	ti,hwmods = "kbd";
	417	};
ffd5db24	418
cbb57f07 PU	419	mcpdm: mcpdm@40132000 {
	420	compatible = "ti,omap4-mcpdm";
	421	reg = <0x40132000 0x7f>, /* MPU private access */
	422	<0x49032000 0x7f>; /* L3 Interconnect */
	423	reg-names = "mpu", "dma";
	424	interrupts = <0 112 0x4>;
cbb57f07 PU	425	ti,hwmods = "mcpdm";
	426	};
	427
	428	dmic: dmic@4012e000 {
	429	compatible = "ti,omap4-dmic";
	430	reg = <0x4012e000 0x7f>, /* MPU private access */
	431	<0x4902e000 0x7f>; /* L3 Interconnect */
	432	reg-names = "mpu", "dma";
	433	interrupts = <0 114 0x4>;
cbb57f07 PU	434	ti,hwmods = "dmic";
	435	};
	436
ffd5db24 PU	437	mcbsp1: mcbsp@40122000 {
	438	compatible = "ti,omap4-mcbsp";
	439	reg = <0x40122000 0xff>, /* MPU private access */
	440	<0x49022000 0xff>; /* L3 Interconnect */
	441	reg-names = "mpu", "dma";
	442	interrupts = <0 17 0x4>;
	443	interrupt-names = "common";
ffd5db24 PU	444	ti,buffer-size = <128>;
	445	ti,hwmods = "mcbsp1";
	446	};
	447
	448	mcbsp2: mcbsp@40124000 {
	449	compatible = "ti,omap4-mcbsp";
	450	reg = <0x40124000 0xff>, /* MPU private access */
	451	<0x49024000 0xff>; /* L3 Interconnect */
	452	reg-names = "mpu", "dma";
	453	interrupts = <0 22 0x4>;
	454	interrupt-names = "common";
ffd5db24 PU	455	ti,buffer-size = <128>;
	456	ti,hwmods = "mcbsp2";
	457	};
	458
	459	mcbsp3: mcbsp@40126000 {
	460	compatible = "ti,omap4-mcbsp";
	461	reg = <0x40126000 0xff>, /* MPU private access */
	462	<0x49026000 0xff>; /* L3 Interconnect */
	463	reg-names = "mpu", "dma";
	464	interrupts = <0 23 0x4>;
	465	interrupt-names = "common";
ffd5db24 PU	466	ti,buffer-size = <128>;
	467	ti,hwmods = "mcbsp3";
	468	};
df692a92 JH	469
	470	timer1: timer@4ae18000 {
	471	compatible = "ti,omap2-timer";
	472	reg = <0x4ae18000 0x80>;
	473	interrupts = <0 37 0x4>;
	474	ti,hwmods = "timer1";
	475	ti,timer-alwon;
	476	};
	477
	478	timer2: timer@48032000 {
	479	compatible = "ti,omap2-timer";
	480	reg = <0x48032000 0x80>;
	481	interrupts = <0 38 0x4>;
	482	ti,hwmods = "timer2";
	483	};
	484
	485	timer3: timer@48034000 {
	486	compatible = "ti,omap2-timer";
	487	reg = <0x48034000 0x80>;
	488	interrupts = <0 39 0x4>;
	489	ti,hwmods = "timer3";
	490	};
	491
	492	timer4: timer@48036000 {
	493	compatible = "ti,omap2-timer";
	494	reg = <0x48036000 0x80>;
	495	interrupts = <0 40 0x4>;
	496	ti,hwmods = "timer4";
	497	};
	498
	499	timer5: timer@40138000 {
	500	compatible = "ti,omap2-timer";
	501	reg = <0x40138000 0x80>,
	502	<0x49038000 0x80>;
	503	interrupts = <0 41 0x4>;
	504	ti,hwmods = "timer5";
	505	ti,timer-dsp;
	506	};
	507
	508	timer6: timer@4013a000 {
	509	compatible = "ti,omap2-timer";
	510	reg = <0x4013a000 0x80>,
	511	<0x4903a000 0x80>;
	512	interrupts = <0 42 0x4>;
	513	ti,hwmods = "timer6";
	514	ti,timer-dsp;
	515	ti,timer-pwm;
	516	};
	517
	518	timer7: timer@4013c000 {
	519	compatible = "ti,omap2-timer";
	520	reg = <0x4013c000 0x80>,
	521	<0x4903c000 0x80>;
	522	interrupts = <0 43 0x4>;
	523	ti,hwmods = "timer7";
	524	ti,timer-dsp;
	525	};
	526
	527	timer8: timer@4013e000 {
	528	compatible = "ti,omap2-timer";
	529	reg = <0x4013e000 0x80>,
	530	<0x4903e000 0x80>;
	531	interrupts = <0 44 0x4>;
	532	ti,hwmods = "timer8";
533	ti,timer-dsp;
534	ti,timer-pwm;
535	};
536
537	timer9: timer@4803e000 {
538	compatible = "ti,omap2-timer";
539	reg = <0x4803e000 0x80>;
540	interrupts = <0 45 0x4>;
541	ti,hwmods = "timer9";
542	};
543
544	timer10: timer@48086000 {
545	compatible = "ti,omap2-timer";
546	reg = <0x48086000 0x80>;
547	interrupts = <0 46 0x4>;
548	ti,hwmods = "timer10";
549	};
550
551	timer11: timer@48088000 {
552	compatible = "ti,omap2-timer";
553	reg = <0x48088000 0x80>;
554	interrupts = <0 47 0x4>;
555	ti,hwmods = "timer11";
556	ti,timer-pwm;
557	};
e6900ddf LV	558
	559	emif1: emif@0x4c000000 {
	560	compatible = "ti,emif-4d5";
	561	ti,hwmods = "emif1";
	562	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	563	reg = <0x4c000000 0x400>;
	564	interrupts = <0 110 0x4>;
	565	hw-caps-read-idle-ctrl;
	566	hw-caps-ll-interface;
	567	hw-caps-temp-alert;
	568	};
	569
	570	emif2: emif@0x4d000000 {
	571	compatible = "ti,emif-4d5";
	572	ti,hwmods = "emif2";
	573	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	574	reg = <0x4d000000 0x400>;
	575	interrupts = <0 111 0x4>;
	576	hw-caps-read-idle-ctrl;
	577	hw-caps-ll-interface;
	578	hw-caps-temp-alert;
	579	};
fedc428e KVA	580
	581	omap_control_usb: omap-control-usb@4a002300 {
	582	compatible = "ti,omap-control-usb";
	583	reg = <0x4a002300 0x4>,
	584	<0x4a002370 0x4>;
	585	reg-names = "control_dev_conf", "phy_power_usb";
	586	ti,type = <2>;
	587	};
e9831967	588
72f6f957 KVA	589	omap_dwc3@4a020000 {
	590	compatible = "ti,dwc3";
	591	ti,hwmods = "usb_otg_ss";
	592	reg = <0x4a020000 0x1000>;
	593	interrupts = <0 93 4>;
	594	#address-cells = <1>;
	595	#size-cells = <1>;
	596	utmi-mode = <2>;
	597	ranges;
	598	dwc3@4a030000 {
	599	compatible = "synopsys,dwc3";
	600	reg = <0x4a030000 0x1000>;
	601	interrupts = <0 92 4>;
	602	usb-phy = <&usb2_phy>, <&usb3_phy>;
	603	tx-fifo-resize;
	604	};
	605	};
	606
e9831967 KVA	607	ocp2scp {
	608	compatible = "ti,omap-ocp2scp";
	609	#address-cells = <1>;
	610	#size-cells = <1>;
	611	ranges;
	612	ti,hwmods = "ocp2scp1";
ae6a32d2 KVA	613	usb2_phy: usb2phy@4a084000 {
	614	compatible = "ti,omap-usb2";
	615	reg = <0x4a084000 0x7c>;
	616	ctrl-module = <&omap_control_usb>;
	617	};
	618
	619	usb3_phy: usb3phy@4a084400 {
	620	compatible = "ti,omap-usb3";
	621	reg = <0x4a084400 0x80>,
	622	<0x4a084800 0x64>,
	623	<0x4a084c00 0x40>;
	624	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
	625	ctrl-module = <&omap_control_usb>;
	626	};
e9831967	627	};
6b5de091 S	628	};
6b5de091 S	629	};