Commit | Line | Data |
---|---|---|
85dc74e9 TK |
1 | /* |
2 | * Device Tree Source for OMAP5 clock data | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | &cm_core_aon_clocks { | |
11 | pad_clks_src_ck: pad_clks_src_ck { | |
12 | #clock-cells = <0>; | |
13 | compatible = "fixed-clock"; | |
14 | clock-frequency = <12000000>; | |
15 | }; | |
16 | ||
17 | pad_clks_ck: pad_clks_ck { | |
18 | #clock-cells = <0>; | |
19 | compatible = "ti,gate-clock"; | |
20 | clocks = <&pad_clks_src_ck>; | |
21 | ti,bit-shift = <8>; | |
22 | reg = <0x0108>; | |
23 | }; | |
24 | ||
25 | secure_32k_clk_src_ck: secure_32k_clk_src_ck { | |
26 | #clock-cells = <0>; | |
27 | compatible = "fixed-clock"; | |
28 | clock-frequency = <32768>; | |
29 | }; | |
30 | ||
31 | slimbus_src_clk: slimbus_src_clk { | |
32 | #clock-cells = <0>; | |
33 | compatible = "fixed-clock"; | |
34 | clock-frequency = <12000000>; | |
35 | }; | |
36 | ||
37 | slimbus_clk: slimbus_clk { | |
38 | #clock-cells = <0>; | |
39 | compatible = "ti,gate-clock"; | |
40 | clocks = <&slimbus_src_clk>; | |
41 | ti,bit-shift = <10>; | |
42 | reg = <0x0108>; | |
43 | }; | |
44 | ||
45 | sys_32k_ck: sys_32k_ck { | |
46 | #clock-cells = <0>; | |
47 | compatible = "fixed-clock"; | |
48 | clock-frequency = <32768>; | |
49 | }; | |
50 | ||
51 | virt_12000000_ck: virt_12000000_ck { | |
52 | #clock-cells = <0>; | |
53 | compatible = "fixed-clock"; | |
54 | clock-frequency = <12000000>; | |
55 | }; | |
56 | ||
57 | virt_13000000_ck: virt_13000000_ck { | |
58 | #clock-cells = <0>; | |
59 | compatible = "fixed-clock"; | |
60 | clock-frequency = <13000000>; | |
61 | }; | |
62 | ||
63 | virt_16800000_ck: virt_16800000_ck { | |
64 | #clock-cells = <0>; | |
65 | compatible = "fixed-clock"; | |
66 | clock-frequency = <16800000>; | |
67 | }; | |
68 | ||
69 | virt_19200000_ck: virt_19200000_ck { | |
70 | #clock-cells = <0>; | |
71 | compatible = "fixed-clock"; | |
72 | clock-frequency = <19200000>; | |
73 | }; | |
74 | ||
75 | virt_26000000_ck: virt_26000000_ck { | |
76 | #clock-cells = <0>; | |
77 | compatible = "fixed-clock"; | |
78 | clock-frequency = <26000000>; | |
79 | }; | |
80 | ||
81 | virt_27000000_ck: virt_27000000_ck { | |
82 | #clock-cells = <0>; | |
83 | compatible = "fixed-clock"; | |
84 | clock-frequency = <27000000>; | |
85 | }; | |
86 | ||
87 | virt_38400000_ck: virt_38400000_ck { | |
88 | #clock-cells = <0>; | |
89 | compatible = "fixed-clock"; | |
90 | clock-frequency = <38400000>; | |
91 | }; | |
92 | ||
93 | xclk60mhsp1_ck: xclk60mhsp1_ck { | |
94 | #clock-cells = <0>; | |
95 | compatible = "fixed-clock"; | |
96 | clock-frequency = <60000000>; | |
97 | }; | |
98 | ||
99 | xclk60mhsp2_ck: xclk60mhsp2_ck { | |
100 | #clock-cells = <0>; | |
101 | compatible = "fixed-clock"; | |
102 | clock-frequency = <60000000>; | |
103 | }; | |
104 | ||
105 | dpll_abe_ck: dpll_abe_ck { | |
106 | #clock-cells = <0>; | |
107 | compatible = "ti,omap4-dpll-m4xen-clock"; | |
108 | clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; | |
109 | reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; | |
110 | }; | |
111 | ||
112 | dpll_abe_x2_ck: dpll_abe_x2_ck { | |
113 | #clock-cells = <0>; | |
114 | compatible = "ti,omap4-dpll-x2-clock"; | |
115 | clocks = <&dpll_abe_ck>; | |
116 | }; | |
117 | ||
118 | dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { | |
119 | #clock-cells = <0>; | |
120 | compatible = "ti,divider-clock"; | |
121 | clocks = <&dpll_abe_x2_ck>; | |
122 | ti,max-div = <31>; | |
123 | ti,autoidle-shift = <8>; | |
124 | reg = <0x01f0>; | |
125 | ti,index-starts-at-one; | |
126 | ti,invert-autoidle-bit; | |
127 | }; | |
128 | ||
129 | abe_24m_fclk: abe_24m_fclk { | |
130 | #clock-cells = <0>; | |
131 | compatible = "fixed-factor-clock"; | |
132 | clocks = <&dpll_abe_m2x2_ck>; | |
133 | clock-mult = <1>; | |
134 | clock-div = <8>; | |
135 | }; | |
136 | ||
137 | abe_clk: abe_clk { | |
138 | #clock-cells = <0>; | |
139 | compatible = "ti,divider-clock"; | |
140 | clocks = <&dpll_abe_m2x2_ck>; | |
141 | ti,max-div = <4>; | |
142 | reg = <0x0108>; | |
143 | ti,index-power-of-two; | |
144 | }; | |
145 | ||
146 | abe_iclk: abe_iclk { | |
147 | #clock-cells = <0>; | |
148 | compatible = "fixed-factor-clock"; | |
149 | clocks = <&abe_clk>; | |
150 | clock-mult = <1>; | |
151 | clock-div = <2>; | |
152 | }; | |
153 | ||
154 | abe_lp_clk_div: abe_lp_clk_div { | |
155 | #clock-cells = <0>; | |
156 | compatible = "fixed-factor-clock"; | |
157 | clocks = <&dpll_abe_m2x2_ck>; | |
158 | clock-mult = <1>; | |
159 | clock-div = <16>; | |
160 | }; | |
161 | ||
162 | dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { | |
163 | #clock-cells = <0>; | |
164 | compatible = "ti,divider-clock"; | |
165 | clocks = <&dpll_abe_x2_ck>; | |
166 | ti,max-div = <31>; | |
167 | ti,autoidle-shift = <8>; | |
168 | reg = <0x01f4>; | |
169 | ti,index-starts-at-one; | |
170 | ti,invert-autoidle-bit; | |
171 | }; | |
172 | ||
173 | dpll_core_ck: dpll_core_ck { | |
174 | #clock-cells = <0>; | |
175 | compatible = "ti,omap4-dpll-core-clock"; | |
176 | clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; | |
177 | reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; | |
178 | }; | |
179 | ||
180 | dpll_core_x2_ck: dpll_core_x2_ck { | |
181 | #clock-cells = <0>; | |
182 | compatible = "ti,omap4-dpll-x2-clock"; | |
183 | clocks = <&dpll_core_ck>; | |
184 | }; | |
185 | ||
186 | dpll_core_h21x2_ck: dpll_core_h21x2_ck { | |
187 | #clock-cells = <0>; | |
188 | compatible = "ti,divider-clock"; | |
189 | clocks = <&dpll_core_x2_ck>; | |
190 | ti,max-div = <63>; | |
191 | ti,autoidle-shift = <8>; | |
192 | reg = <0x0150>; | |
193 | ti,index-starts-at-one; | |
194 | ti,invert-autoidle-bit; | |
195 | }; | |
196 | ||
197 | c2c_fclk: c2c_fclk { | |
198 | #clock-cells = <0>; | |
199 | compatible = "fixed-factor-clock"; | |
200 | clocks = <&dpll_core_h21x2_ck>; | |
201 | clock-mult = <1>; | |
202 | clock-div = <1>; | |
203 | }; | |
204 | ||
205 | c2c_iclk: c2c_iclk { | |
206 | #clock-cells = <0>; | |
207 | compatible = "fixed-factor-clock"; | |
208 | clocks = <&c2c_fclk>; | |
209 | clock-mult = <1>; | |
210 | clock-div = <2>; | |
211 | }; | |
212 | ||
213 | dpll_core_h11x2_ck: dpll_core_h11x2_ck { | |
214 | #clock-cells = <0>; | |
215 | compatible = "ti,divider-clock"; | |
216 | clocks = <&dpll_core_x2_ck>; | |
217 | ti,max-div = <63>; | |
218 | ti,autoidle-shift = <8>; | |
219 | reg = <0x0138>; | |
220 | ti,index-starts-at-one; | |
221 | ti,invert-autoidle-bit; | |
222 | }; | |
223 | ||
224 | dpll_core_h12x2_ck: dpll_core_h12x2_ck { | |
225 | #clock-cells = <0>; | |
226 | compatible = "ti,divider-clock"; | |
227 | clocks = <&dpll_core_x2_ck>; | |
228 | ti,max-div = <63>; | |
229 | ti,autoidle-shift = <8>; | |
230 | reg = <0x013c>; | |
231 | ti,index-starts-at-one; | |
232 | ti,invert-autoidle-bit; | |
233 | }; | |
234 | ||
235 | dpll_core_h13x2_ck: dpll_core_h13x2_ck { | |
236 | #clock-cells = <0>; | |
237 | compatible = "ti,divider-clock"; | |
238 | clocks = <&dpll_core_x2_ck>; | |
239 | ti,max-div = <63>; | |
240 | ti,autoidle-shift = <8>; | |
241 | reg = <0x0140>; | |
242 | ti,index-starts-at-one; | |
243 | ti,invert-autoidle-bit; | |
244 | }; | |
245 | ||
246 | dpll_core_h14x2_ck: dpll_core_h14x2_ck { | |
247 | #clock-cells = <0>; | |
248 | compatible = "ti,divider-clock"; | |
249 | clocks = <&dpll_core_x2_ck>; | |
250 | ti,max-div = <63>; | |
251 | ti,autoidle-shift = <8>; | |
252 | reg = <0x0144>; | |
253 | ti,index-starts-at-one; | |
254 | ti,invert-autoidle-bit; | |
255 | }; | |
256 | ||
257 | dpll_core_h22x2_ck: dpll_core_h22x2_ck { | |
258 | #clock-cells = <0>; | |
259 | compatible = "ti,divider-clock"; | |
260 | clocks = <&dpll_core_x2_ck>; | |
261 | ti,max-div = <63>; | |
262 | ti,autoidle-shift = <8>; | |
263 | reg = <0x0154>; | |
264 | ti,index-starts-at-one; | |
265 | ti,invert-autoidle-bit; | |
266 | }; | |
267 | ||
268 | dpll_core_h23x2_ck: dpll_core_h23x2_ck { | |
269 | #clock-cells = <0>; | |
270 | compatible = "ti,divider-clock"; | |
271 | clocks = <&dpll_core_x2_ck>; | |
272 | ti,max-div = <63>; | |
273 | ti,autoidle-shift = <8>; | |
274 | reg = <0x0158>; | |
275 | ti,index-starts-at-one; | |
276 | ti,invert-autoidle-bit; | |
277 | }; | |
278 | ||
279 | dpll_core_h24x2_ck: dpll_core_h24x2_ck { | |
280 | #clock-cells = <0>; | |
281 | compatible = "ti,divider-clock"; | |
282 | clocks = <&dpll_core_x2_ck>; | |
283 | ti,max-div = <63>; | |
284 | ti,autoidle-shift = <8>; | |
285 | reg = <0x015c>; | |
286 | ti,index-starts-at-one; | |
287 | ti,invert-autoidle-bit; | |
288 | }; | |
289 | ||
290 | dpll_core_m2_ck: dpll_core_m2_ck { | |
291 | #clock-cells = <0>; | |
292 | compatible = "ti,divider-clock"; | |
293 | clocks = <&dpll_core_ck>; | |
294 | ti,max-div = <31>; | |
295 | ti,autoidle-shift = <8>; | |
296 | reg = <0x0130>; | |
297 | ti,index-starts-at-one; | |
298 | ti,invert-autoidle-bit; | |
299 | }; | |
300 | ||
301 | dpll_core_m3x2_ck: dpll_core_m3x2_ck { | |
302 | #clock-cells = <0>; | |
303 | compatible = "ti,divider-clock"; | |
304 | clocks = <&dpll_core_x2_ck>; | |
305 | ti,max-div = <31>; | |
306 | ti,autoidle-shift = <8>; | |
307 | reg = <0x0134>; | |
308 | ti,index-starts-at-one; | |
309 | ti,invert-autoidle-bit; | |
310 | }; | |
311 | ||
312 | iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { | |
313 | #clock-cells = <0>; | |
314 | compatible = "fixed-factor-clock"; | |
315 | clocks = <&dpll_core_h12x2_ck>; | |
316 | clock-mult = <1>; | |
317 | clock-div = <1>; | |
318 | }; | |
319 | ||
320 | dpll_iva_ck: dpll_iva_ck { | |
321 | #clock-cells = <0>; | |
322 | compatible = "ti,omap4-dpll-clock"; | |
323 | clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; | |
324 | reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; | |
325 | }; | |
326 | ||
327 | dpll_iva_x2_ck: dpll_iva_x2_ck { | |
328 | #clock-cells = <0>; | |
329 | compatible = "ti,omap4-dpll-x2-clock"; | |
330 | clocks = <&dpll_iva_ck>; | |
331 | }; | |
332 | ||
333 | dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { | |
334 | #clock-cells = <0>; | |
335 | compatible = "ti,divider-clock"; | |
336 | clocks = <&dpll_iva_x2_ck>; | |
337 | ti,max-div = <63>; | |
338 | ti,autoidle-shift = <8>; | |
339 | reg = <0x01b8>; | |
340 | ti,index-starts-at-one; | |
341 | ti,invert-autoidle-bit; | |
342 | }; | |
343 | ||
344 | dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { | |
345 | #clock-cells = <0>; | |
346 | compatible = "ti,divider-clock"; | |
347 | clocks = <&dpll_iva_x2_ck>; | |
348 | ti,max-div = <63>; | |
349 | ti,autoidle-shift = <8>; | |
350 | reg = <0x01bc>; | |
351 | ti,index-starts-at-one; | |
352 | ti,invert-autoidle-bit; | |
353 | }; | |
354 | ||
355 | mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { | |
356 | #clock-cells = <0>; | |
357 | compatible = "fixed-factor-clock"; | |
358 | clocks = <&dpll_core_h12x2_ck>; | |
359 | clock-mult = <1>; | |
360 | clock-div = <1>; | |
361 | }; | |
362 | ||
363 | dpll_mpu_ck: dpll_mpu_ck { | |
364 | #clock-cells = <0>; | |
365 | compatible = "ti,omap4-dpll-clock"; | |
366 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; | |
367 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | |
368 | }; | |
369 | ||
370 | dpll_mpu_m2_ck: dpll_mpu_m2_ck { | |
371 | #clock-cells = <0>; | |
372 | compatible = "ti,divider-clock"; | |
373 | clocks = <&dpll_mpu_ck>; | |
374 | ti,max-div = <31>; | |
375 | ti,autoidle-shift = <8>; | |
376 | reg = <0x0170>; | |
377 | ti,index-starts-at-one; | |
378 | ti,invert-autoidle-bit; | |
379 | }; | |
380 | ||
381 | per_dpll_hs_clk_div: per_dpll_hs_clk_div { | |
382 | #clock-cells = <0>; | |
383 | compatible = "fixed-factor-clock"; | |
384 | clocks = <&dpll_abe_m3x2_ck>; | |
385 | clock-mult = <1>; | |
386 | clock-div = <2>; | |
387 | }; | |
388 | ||
389 | usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { | |
390 | #clock-cells = <0>; | |
391 | compatible = "fixed-factor-clock"; | |
392 | clocks = <&dpll_abe_m3x2_ck>; | |
393 | clock-mult = <1>; | |
394 | clock-div = <3>; | |
395 | }; | |
396 | ||
397 | l3_iclk_div: l3_iclk_div { | |
398 | #clock-cells = <0>; | |
399 | compatible = "fixed-factor-clock"; | |
400 | clocks = <&dpll_core_h12x2_ck>; | |
401 | clock-mult = <1>; | |
402 | clock-div = <1>; | |
403 | }; | |
404 | ||
405 | gpu_l3_iclk: gpu_l3_iclk { | |
406 | #clock-cells = <0>; | |
407 | compatible = "fixed-factor-clock"; | |
408 | clocks = <&l3_iclk_div>; | |
409 | clock-mult = <1>; | |
410 | clock-div = <1>; | |
411 | }; | |
412 | ||
413 | l4_root_clk_div: l4_root_clk_div { | |
414 | #clock-cells = <0>; | |
415 | compatible = "fixed-factor-clock"; | |
416 | clocks = <&l3_iclk_div>; | |
417 | clock-mult = <1>; | |
418 | clock-div = <1>; | |
419 | }; | |
420 | ||
421 | slimbus1_slimbus_clk: slimbus1_slimbus_clk { | |
422 | #clock-cells = <0>; | |
423 | compatible = "ti,gate-clock"; | |
424 | clocks = <&slimbus_clk>; | |
425 | ti,bit-shift = <11>; | |
426 | reg = <0x0560>; | |
427 | }; | |
428 | ||
429 | aess_fclk: aess_fclk { | |
430 | #clock-cells = <0>; | |
431 | compatible = "ti,divider-clock"; | |
432 | clocks = <&abe_clk>; | |
433 | ti,bit-shift = <24>; | |
434 | ti,max-div = <2>; | |
435 | reg = <0x0528>; | |
436 | }; | |
437 | ||
438 | dmic_sync_mux_ck: dmic_sync_mux_ck { | |
439 | #clock-cells = <0>; | |
440 | compatible = "ti,mux-clock"; | |
441 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
442 | ti,bit-shift = <26>; | |
443 | reg = <0x0538>; | |
444 | }; | |
445 | ||
446 | dmic_gfclk: dmic_gfclk { | |
447 | #clock-cells = <0>; | |
448 | compatible = "ti,mux-clock"; | |
449 | clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
450 | ti,bit-shift = <24>; | |
451 | reg = <0x0538>; | |
452 | }; | |
453 | ||
454 | mcasp_sync_mux_ck: mcasp_sync_mux_ck { | |
455 | #clock-cells = <0>; | |
456 | compatible = "ti,mux-clock"; | |
457 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
458 | ti,bit-shift = <26>; | |
459 | reg = <0x0540>; | |
460 | }; | |
461 | ||
462 | mcasp_gfclk: mcasp_gfclk { | |
463 | #clock-cells = <0>; | |
464 | compatible = "ti,mux-clock"; | |
465 | clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
466 | ti,bit-shift = <24>; | |
467 | reg = <0x0540>; | |
468 | }; | |
469 | ||
470 | mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { | |
471 | #clock-cells = <0>; | |
472 | compatible = "ti,mux-clock"; | |
473 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
474 | ti,bit-shift = <26>; | |
475 | reg = <0x0548>; | |
476 | }; | |
477 | ||
478 | mcbsp1_gfclk: mcbsp1_gfclk { | |
479 | #clock-cells = <0>; | |
480 | compatible = "ti,mux-clock"; | |
481 | clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
482 | ti,bit-shift = <24>; | |
483 | reg = <0x0548>; | |
484 | }; | |
485 | ||
486 | mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { | |
487 | #clock-cells = <0>; | |
488 | compatible = "ti,mux-clock"; | |
489 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
490 | ti,bit-shift = <26>; | |
491 | reg = <0x0550>; | |
492 | }; | |
493 | ||
494 | mcbsp2_gfclk: mcbsp2_gfclk { | |
495 | #clock-cells = <0>; | |
496 | compatible = "ti,mux-clock"; | |
497 | clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
498 | ti,bit-shift = <24>; | |
499 | reg = <0x0550>; | |
500 | }; | |
501 | ||
502 | mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { | |
503 | #clock-cells = <0>; | |
504 | compatible = "ti,mux-clock"; | |
505 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
506 | ti,bit-shift = <26>; | |
507 | reg = <0x0558>; | |
508 | }; | |
509 | ||
510 | mcbsp3_gfclk: mcbsp3_gfclk { | |
511 | #clock-cells = <0>; | |
512 | compatible = "ti,mux-clock"; | |
513 | clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
514 | ti,bit-shift = <24>; | |
515 | reg = <0x0558>; | |
516 | }; | |
517 | ||
518 | timer5_gfclk_mux: timer5_gfclk_mux { | |
519 | #clock-cells = <0>; | |
520 | compatible = "ti,mux-clock"; | |
521 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
522 | ti,bit-shift = <24>; | |
523 | reg = <0x0568>; | |
524 | }; | |
525 | ||
526 | timer6_gfclk_mux: timer6_gfclk_mux { | |
527 | #clock-cells = <0>; | |
528 | compatible = "ti,mux-clock"; | |
529 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
530 | ti,bit-shift = <24>; | |
531 | reg = <0x0570>; | |
532 | }; | |
533 | ||
534 | timer7_gfclk_mux: timer7_gfclk_mux { | |
535 | #clock-cells = <0>; | |
536 | compatible = "ti,mux-clock"; | |
537 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
538 | ti,bit-shift = <24>; | |
539 | reg = <0x0578>; | |
540 | }; | |
541 | ||
542 | timer8_gfclk_mux: timer8_gfclk_mux { | |
543 | #clock-cells = <0>; | |
544 | compatible = "ti,mux-clock"; | |
545 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
546 | ti,bit-shift = <24>; | |
547 | reg = <0x0580>; | |
548 | }; | |
549 | ||
550 | dummy_ck: dummy_ck { | |
551 | #clock-cells = <0>; | |
552 | compatible = "fixed-clock"; | |
553 | clock-frequency = <0>; | |
554 | }; | |
555 | }; | |
556 | &prm_clocks { | |
557 | sys_clkin: sys_clkin { | |
558 | #clock-cells = <0>; | |
559 | compatible = "ti,mux-clock"; | |
560 | clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; | |
561 | reg = <0x0110>; | |
562 | ti,index-starts-at-one; | |
563 | }; | |
564 | ||
565 | abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { | |
566 | #clock-cells = <0>; | |
567 | compatible = "ti,mux-clock"; | |
568 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
569 | reg = <0x0108>; | |
570 | }; | |
571 | ||
572 | abe_dpll_clk_mux: abe_dpll_clk_mux { | |
573 | #clock-cells = <0>; | |
574 | compatible = "ti,mux-clock"; | |
575 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
576 | reg = <0x010c>; | |
577 | }; | |
578 | ||
579 | custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { | |
580 | #clock-cells = <0>; | |
581 | compatible = "fixed-factor-clock"; | |
582 | clocks = <&sys_clkin>; | |
583 | clock-mult = <1>; | |
584 | clock-div = <2>; | |
585 | }; | |
586 | ||
587 | dss_syc_gfclk_div: dss_syc_gfclk_div { | |
588 | #clock-cells = <0>; | |
589 | compatible = "fixed-factor-clock"; | |
590 | clocks = <&sys_clkin>; | |
591 | clock-mult = <1>; | |
592 | clock-div = <1>; | |
593 | }; | |
594 | ||
595 | wkupaon_iclk_mux: wkupaon_iclk_mux { | |
596 | #clock-cells = <0>; | |
597 | compatible = "ti,mux-clock"; | |
598 | clocks = <&sys_clkin>, <&abe_lp_clk_div>; | |
599 | reg = <0x0108>; | |
600 | }; | |
601 | ||
602 | l3instr_ts_gclk_div: l3instr_ts_gclk_div { | |
603 | #clock-cells = <0>; | |
604 | compatible = "fixed-factor-clock"; | |
605 | clocks = <&wkupaon_iclk_mux>; | |
606 | clock-mult = <1>; | |
607 | clock-div = <1>; | |
608 | }; | |
609 | ||
610 | gpio1_dbclk: gpio1_dbclk { | |
611 | #clock-cells = <0>; | |
612 | compatible = "ti,gate-clock"; | |
613 | clocks = <&sys_32k_ck>; | |
614 | ti,bit-shift = <8>; | |
615 | reg = <0x1938>; | |
616 | }; | |
617 | ||
618 | timer1_gfclk_mux: timer1_gfclk_mux { | |
619 | #clock-cells = <0>; | |
620 | compatible = "ti,mux-clock"; | |
621 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
622 | ti,bit-shift = <24>; | |
623 | reg = <0x1940>; | |
624 | }; | |
625 | }; | |
626 | &cm_core_clocks { | |
627 | dpll_per_ck: dpll_per_ck { | |
628 | #clock-cells = <0>; | |
629 | compatible = "ti,omap4-dpll-clock"; | |
630 | clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; | |
631 | reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; | |
632 | }; | |
633 | ||
634 | dpll_per_x2_ck: dpll_per_x2_ck { | |
635 | #clock-cells = <0>; | |
636 | compatible = "ti,omap4-dpll-x2-clock"; | |
637 | clocks = <&dpll_per_ck>; | |
638 | }; | |
639 | ||
640 | dpll_per_h11x2_ck: dpll_per_h11x2_ck { | |
641 | #clock-cells = <0>; | |
642 | compatible = "ti,divider-clock"; | |
643 | clocks = <&dpll_per_x2_ck>; | |
644 | ti,max-div = <63>; | |
645 | ti,autoidle-shift = <8>; | |
646 | reg = <0x0158>; | |
647 | ti,index-starts-at-one; | |
648 | ti,invert-autoidle-bit; | |
649 | }; | |
650 | ||
651 | dpll_per_h12x2_ck: dpll_per_h12x2_ck { | |
652 | #clock-cells = <0>; | |
653 | compatible = "ti,divider-clock"; | |
654 | clocks = <&dpll_per_x2_ck>; | |
655 | ti,max-div = <63>; | |
656 | ti,autoidle-shift = <8>; | |
657 | reg = <0x015c>; | |
658 | ti,index-starts-at-one; | |
659 | ti,invert-autoidle-bit; | |
660 | }; | |
661 | ||
662 | dpll_per_h14x2_ck: dpll_per_h14x2_ck { | |
663 | #clock-cells = <0>; | |
664 | compatible = "ti,divider-clock"; | |
665 | clocks = <&dpll_per_x2_ck>; | |
666 | ti,max-div = <63>; | |
667 | ti,autoidle-shift = <8>; | |
668 | reg = <0x0164>; | |
669 | ti,index-starts-at-one; | |
670 | ti,invert-autoidle-bit; | |
671 | }; | |
672 | ||
673 | dpll_per_m2_ck: dpll_per_m2_ck { | |
674 | #clock-cells = <0>; | |
675 | compatible = "ti,divider-clock"; | |
676 | clocks = <&dpll_per_ck>; | |
677 | ti,max-div = <31>; | |
678 | ti,autoidle-shift = <8>; | |
679 | reg = <0x0150>; | |
680 | ti,index-starts-at-one; | |
681 | ti,invert-autoidle-bit; | |
682 | }; | |
683 | ||
684 | dpll_per_m2x2_ck: dpll_per_m2x2_ck { | |
685 | #clock-cells = <0>; | |
686 | compatible = "ti,divider-clock"; | |
687 | clocks = <&dpll_per_x2_ck>; | |
688 | ti,max-div = <31>; | |
689 | ti,autoidle-shift = <8>; | |
690 | reg = <0x0150>; | |
691 | ti,index-starts-at-one; | |
692 | ti,invert-autoidle-bit; | |
693 | }; | |
694 | ||
695 | dpll_per_m3x2_ck: dpll_per_m3x2_ck { | |
696 | #clock-cells = <0>; | |
697 | compatible = "ti,divider-clock"; | |
698 | clocks = <&dpll_per_x2_ck>; | |
699 | ti,max-div = <31>; | |
700 | ti,autoidle-shift = <8>; | |
701 | reg = <0x0154>; | |
702 | ti,index-starts-at-one; | |
703 | ti,invert-autoidle-bit; | |
704 | }; | |
705 | ||
706 | dpll_unipro1_ck: dpll_unipro1_ck { | |
707 | #clock-cells = <0>; | |
708 | compatible = "ti,omap4-dpll-clock"; | |
709 | clocks = <&sys_clkin>, <&sys_clkin>; | |
710 | reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; | |
711 | }; | |
712 | ||
713 | dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { | |
714 | #clock-cells = <0>; | |
715 | compatible = "fixed-factor-clock"; | |
716 | clocks = <&dpll_unipro1_ck>; | |
717 | clock-mult = <1>; | |
718 | clock-div = <1>; | |
719 | }; | |
720 | ||
721 | dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { | |
722 | #clock-cells = <0>; | |
723 | compatible = "ti,divider-clock"; | |
724 | clocks = <&dpll_unipro1_ck>; | |
725 | ti,max-div = <127>; | |
726 | ti,autoidle-shift = <8>; | |
727 | reg = <0x0210>; | |
728 | ti,index-starts-at-one; | |
729 | ti,invert-autoidle-bit; | |
730 | }; | |
731 | ||
732 | dpll_unipro2_ck: dpll_unipro2_ck { | |
733 | #clock-cells = <0>; | |
734 | compatible = "ti,omap4-dpll-clock"; | |
735 | clocks = <&sys_clkin>, <&sys_clkin>; | |
736 | reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; | |
737 | }; | |
738 | ||
739 | dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { | |
740 | #clock-cells = <0>; | |
741 | compatible = "fixed-factor-clock"; | |
742 | clocks = <&dpll_unipro2_ck>; | |
743 | clock-mult = <1>; | |
744 | clock-div = <1>; | |
745 | }; | |
746 | ||
747 | dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { | |
748 | #clock-cells = <0>; | |
749 | compatible = "ti,divider-clock"; | |
750 | clocks = <&dpll_unipro2_ck>; | |
751 | ti,max-div = <127>; | |
752 | ti,autoidle-shift = <8>; | |
753 | reg = <0x01d0>; | |
754 | ti,index-starts-at-one; | |
755 | ti,invert-autoidle-bit; | |
756 | }; | |
757 | ||
758 | dpll_usb_ck: dpll_usb_ck { | |
759 | #clock-cells = <0>; | |
760 | compatible = "ti,omap4-dpll-j-type-clock"; | |
761 | clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; | |
762 | reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; | |
763 | }; | |
764 | ||
765 | dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { | |
766 | #clock-cells = <0>; | |
767 | compatible = "fixed-factor-clock"; | |
768 | clocks = <&dpll_usb_ck>; | |
769 | clock-mult = <1>; | |
770 | clock-div = <1>; | |
771 | }; | |
772 | ||
773 | dpll_usb_m2_ck: dpll_usb_m2_ck { | |
774 | #clock-cells = <0>; | |
775 | compatible = "ti,divider-clock"; | |
776 | clocks = <&dpll_usb_ck>; | |
777 | ti,max-div = <127>; | |
778 | ti,autoidle-shift = <8>; | |
779 | reg = <0x0190>; | |
780 | ti,index-starts-at-one; | |
781 | ti,invert-autoidle-bit; | |
782 | }; | |
783 | ||
784 | func_128m_clk: func_128m_clk { | |
785 | #clock-cells = <0>; | |
786 | compatible = "fixed-factor-clock"; | |
787 | clocks = <&dpll_per_h11x2_ck>; | |
788 | clock-mult = <1>; | |
789 | clock-div = <2>; | |
790 | }; | |
791 | ||
792 | func_12m_fclk: func_12m_fclk { | |
793 | #clock-cells = <0>; | |
794 | compatible = "fixed-factor-clock"; | |
795 | clocks = <&dpll_per_m2x2_ck>; | |
796 | clock-mult = <1>; | |
797 | clock-div = <16>; | |
798 | }; | |
799 | ||
800 | func_24m_clk: func_24m_clk { | |
801 | #clock-cells = <0>; | |
802 | compatible = "fixed-factor-clock"; | |
803 | clocks = <&dpll_per_m2_ck>; | |
804 | clock-mult = <1>; | |
805 | clock-div = <4>; | |
806 | }; | |
807 | ||
808 | func_48m_fclk: func_48m_fclk { | |
809 | #clock-cells = <0>; | |
810 | compatible = "fixed-factor-clock"; | |
811 | clocks = <&dpll_per_m2x2_ck>; | |
812 | clock-mult = <1>; | |
813 | clock-div = <4>; | |
814 | }; | |
815 | ||
816 | func_96m_fclk: func_96m_fclk { | |
817 | #clock-cells = <0>; | |
818 | compatible = "fixed-factor-clock"; | |
819 | clocks = <&dpll_per_m2x2_ck>; | |
820 | clock-mult = <1>; | |
821 | clock-div = <2>; | |
822 | }; | |
823 | ||
824 | l3init_60m_fclk: l3init_60m_fclk { | |
825 | #clock-cells = <0>; | |
826 | compatible = "ti,divider-clock"; | |
827 | clocks = <&dpll_usb_m2_ck>; | |
828 | reg = <0x0104>; | |
829 | ti,dividers = <1>, <8>; | |
830 | }; | |
831 | ||
832 | dss_32khz_clk: dss_32khz_clk { | |
833 | #clock-cells = <0>; | |
834 | compatible = "ti,gate-clock"; | |
835 | clocks = <&sys_32k_ck>; | |
836 | ti,bit-shift = <11>; | |
837 | reg = <0x1420>; | |
838 | }; | |
839 | ||
840 | dss_48mhz_clk: dss_48mhz_clk { | |
841 | #clock-cells = <0>; | |
842 | compatible = "ti,gate-clock"; | |
843 | clocks = <&func_48m_fclk>; | |
844 | ti,bit-shift = <9>; | |
845 | reg = <0x1420>; | |
846 | }; | |
847 | ||
848 | dss_dss_clk: dss_dss_clk { | |
849 | #clock-cells = <0>; | |
850 | compatible = "ti,gate-clock"; | |
851 | clocks = <&dpll_per_h12x2_ck>; | |
852 | ti,bit-shift = <8>; | |
853 | reg = <0x1420>; | |
854 | }; | |
855 | ||
856 | dss_sys_clk: dss_sys_clk { | |
857 | #clock-cells = <0>; | |
858 | compatible = "ti,gate-clock"; | |
859 | clocks = <&dss_syc_gfclk_div>; | |
860 | ti,bit-shift = <10>; | |
861 | reg = <0x1420>; | |
862 | }; | |
863 | ||
864 | gpio2_dbclk: gpio2_dbclk { | |
865 | #clock-cells = <0>; | |
866 | compatible = "ti,gate-clock"; | |
867 | clocks = <&sys_32k_ck>; | |
868 | ti,bit-shift = <8>; | |
869 | reg = <0x1060>; | |
870 | }; | |
871 | ||
872 | gpio3_dbclk: gpio3_dbclk { | |
873 | #clock-cells = <0>; | |
874 | compatible = "ti,gate-clock"; | |
875 | clocks = <&sys_32k_ck>; | |
876 | ti,bit-shift = <8>; | |
877 | reg = <0x1068>; | |
878 | }; | |
879 | ||
880 | gpio4_dbclk: gpio4_dbclk { | |
881 | #clock-cells = <0>; | |
882 | compatible = "ti,gate-clock"; | |
883 | clocks = <&sys_32k_ck>; | |
884 | ti,bit-shift = <8>; | |
885 | reg = <0x1070>; | |
886 | }; | |
887 | ||
888 | gpio5_dbclk: gpio5_dbclk { | |
889 | #clock-cells = <0>; | |
890 | compatible = "ti,gate-clock"; | |
891 | clocks = <&sys_32k_ck>; | |
892 | ti,bit-shift = <8>; | |
893 | reg = <0x1078>; | |
894 | }; | |
895 | ||
896 | gpio6_dbclk: gpio6_dbclk { | |
897 | #clock-cells = <0>; | |
898 | compatible = "ti,gate-clock"; | |
899 | clocks = <&sys_32k_ck>; | |
900 | ti,bit-shift = <8>; | |
901 | reg = <0x1080>; | |
902 | }; | |
903 | ||
904 | gpio7_dbclk: gpio7_dbclk { | |
905 | #clock-cells = <0>; | |
906 | compatible = "ti,gate-clock"; | |
907 | clocks = <&sys_32k_ck>; | |
908 | ti,bit-shift = <8>; | |
909 | reg = <0x1110>; | |
910 | }; | |
911 | ||
912 | gpio8_dbclk: gpio8_dbclk { | |
913 | #clock-cells = <0>; | |
914 | compatible = "ti,gate-clock"; | |
915 | clocks = <&sys_32k_ck>; | |
916 | ti,bit-shift = <8>; | |
917 | reg = <0x1118>; | |
918 | }; | |
919 | ||
920 | iss_ctrlclk: iss_ctrlclk { | |
921 | #clock-cells = <0>; | |
922 | compatible = "ti,gate-clock"; | |
923 | clocks = <&func_96m_fclk>; | |
924 | ti,bit-shift = <8>; | |
925 | reg = <0x1320>; | |
926 | }; | |
927 | ||
928 | lli_txphy_clk: lli_txphy_clk { | |
929 | #clock-cells = <0>; | |
930 | compatible = "ti,gate-clock"; | |
931 | clocks = <&dpll_unipro1_clkdcoldo>; | |
932 | ti,bit-shift = <8>; | |
933 | reg = <0x0f20>; | |
934 | }; | |
935 | ||
936 | lli_txphy_ls_clk: lli_txphy_ls_clk { | |
937 | #clock-cells = <0>; | |
938 | compatible = "ti,gate-clock"; | |
939 | clocks = <&dpll_unipro1_m2_ck>; | |
940 | ti,bit-shift = <9>; | |
941 | reg = <0x0f20>; | |
942 | }; | |
943 | ||
944 | mmc1_32khz_clk: mmc1_32khz_clk { | |
945 | #clock-cells = <0>; | |
946 | compatible = "ti,gate-clock"; | |
947 | clocks = <&sys_32k_ck>; | |
948 | ti,bit-shift = <8>; | |
949 | reg = <0x1628>; | |
950 | }; | |
951 | ||
952 | sata_ref_clk: sata_ref_clk { | |
953 | #clock-cells = <0>; | |
954 | compatible = "ti,gate-clock"; | |
955 | clocks = <&sys_clkin>; | |
956 | ti,bit-shift = <8>; | |
957 | reg = <0x1688>; | |
958 | }; | |
959 | ||
960 | usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { | |
961 | #clock-cells = <0>; | |
962 | compatible = "ti,gate-clock"; | |
963 | clocks = <&dpll_usb_m2_ck>; | |
964 | ti,bit-shift = <13>; | |
965 | reg = <0x1658>; | |
966 | }; | |
967 | ||
968 | usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { | |
969 | #clock-cells = <0>; | |
970 | compatible = "ti,gate-clock"; | |
971 | clocks = <&dpll_usb_m2_ck>; | |
972 | ti,bit-shift = <14>; | |
973 | reg = <0x1658>; | |
974 | }; | |
975 | ||
976 | usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { | |
977 | #clock-cells = <0>; | |
978 | compatible = "ti,gate-clock"; | |
979 | clocks = <&dpll_usb_m2_ck>; | |
980 | ti,bit-shift = <7>; | |
981 | reg = <0x1658>; | |
982 | }; | |
983 | ||
984 | usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { | |
985 | #clock-cells = <0>; | |
986 | compatible = "ti,gate-clock"; | |
987 | clocks = <&l3init_60m_fclk>; | |
988 | ti,bit-shift = <11>; | |
989 | reg = <0x1658>; | |
990 | }; | |
991 | ||
992 | usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { | |
993 | #clock-cells = <0>; | |
994 | compatible = "ti,gate-clock"; | |
995 | clocks = <&l3init_60m_fclk>; | |
996 | ti,bit-shift = <12>; | |
997 | reg = <0x1658>; | |
998 | }; | |
999 | ||
1000 | usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { | |
1001 | #clock-cells = <0>; | |
1002 | compatible = "ti,gate-clock"; | |
1003 | clocks = <&l3init_60m_fclk>; | |
1004 | ti,bit-shift = <6>; | |
1005 | reg = <0x1658>; | |
1006 | }; | |
1007 | ||
1008 | utmi_p1_gfclk: utmi_p1_gfclk { | |
1009 | #clock-cells = <0>; | |
1010 | compatible = "ti,mux-clock"; | |
1011 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; | |
1012 | ti,bit-shift = <24>; | |
1013 | reg = <0x1658>; | |
1014 | }; | |
1015 | ||
1016 | usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { | |
1017 | #clock-cells = <0>; | |
1018 | compatible = "ti,gate-clock"; | |
1019 | clocks = <&utmi_p1_gfclk>; | |
1020 | ti,bit-shift = <8>; | |
1021 | reg = <0x1658>; | |
1022 | }; | |
1023 | ||
1024 | utmi_p2_gfclk: utmi_p2_gfclk { | |
1025 | #clock-cells = <0>; | |
1026 | compatible = "ti,mux-clock"; | |
1027 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; | |
1028 | ti,bit-shift = <25>; | |
1029 | reg = <0x1658>; | |
1030 | }; | |
1031 | ||
1032 | usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { | |
1033 | #clock-cells = <0>; | |
1034 | compatible = "ti,gate-clock"; | |
1035 | clocks = <&utmi_p2_gfclk>; | |
1036 | ti,bit-shift = <9>; | |
1037 | reg = <0x1658>; | |
1038 | }; | |
1039 | ||
1040 | usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { | |
1041 | #clock-cells = <0>; | |
1042 | compatible = "ti,gate-clock"; | |
1043 | clocks = <&l3init_60m_fclk>; | |
1044 | ti,bit-shift = <10>; | |
1045 | reg = <0x1658>; | |
1046 | }; | |
1047 | ||
1048 | usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { | |
1049 | #clock-cells = <0>; | |
1050 | compatible = "ti,gate-clock"; | |
1051 | clocks = <&dpll_usb_clkdcoldo>; | |
1052 | ti,bit-shift = <8>; | |
1053 | reg = <0x16f0>; | |
1054 | }; | |
1055 | ||
1056 | usb_phy_cm_clk32k: usb_phy_cm_clk32k { | |
1057 | #clock-cells = <0>; | |
1058 | compatible = "ti,gate-clock"; | |
1059 | clocks = <&sys_32k_ck>; | |
1060 | ti,bit-shift = <8>; | |
1061 | reg = <0x0640>; | |
1062 | }; | |
1063 | ||
1064 | usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { | |
1065 | #clock-cells = <0>; | |
1066 | compatible = "ti,gate-clock"; | |
1067 | clocks = <&l3init_60m_fclk>; | |
1068 | ti,bit-shift = <8>; | |
1069 | reg = <0x1668>; | |
1070 | }; | |
1071 | ||
1072 | usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { | |
1073 | #clock-cells = <0>; | |
1074 | compatible = "ti,gate-clock"; | |
1075 | clocks = <&l3init_60m_fclk>; | |
1076 | ti,bit-shift = <9>; | |
1077 | reg = <0x1668>; | |
1078 | }; | |
1079 | ||
1080 | usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { | |
1081 | #clock-cells = <0>; | |
1082 | compatible = "ti,gate-clock"; | |
1083 | clocks = <&l3init_60m_fclk>; | |
1084 | ti,bit-shift = <10>; | |
1085 | reg = <0x1668>; | |
1086 | }; | |
1087 | ||
1088 | fdif_fclk: fdif_fclk { | |
1089 | #clock-cells = <0>; | |
1090 | compatible = "ti,divider-clock"; | |
1091 | clocks = <&dpll_per_h11x2_ck>; | |
1092 | ti,bit-shift = <24>; | |
1093 | ti,max-div = <2>; | |
1094 | reg = <0x1328>; | |
1095 | }; | |
1096 | ||
1097 | gpu_core_gclk_mux: gpu_core_gclk_mux { | |
1098 | #clock-cells = <0>; | |
1099 | compatible = "ti,mux-clock"; | |
1100 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
1101 | ti,bit-shift = <24>; | |
1102 | reg = <0x1520>; | |
1103 | }; | |
1104 | ||
1105 | gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { | |
1106 | #clock-cells = <0>; | |
1107 | compatible = "ti,mux-clock"; | |
1108 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
1109 | ti,bit-shift = <25>; | |
1110 | reg = <0x1520>; | |
1111 | }; | |
1112 | ||
1113 | hsi_fclk: hsi_fclk { | |
1114 | #clock-cells = <0>; | |
1115 | compatible = "ti,divider-clock"; | |
1116 | clocks = <&dpll_per_m2x2_ck>; | |
1117 | ti,bit-shift = <24>; | |
1118 | ti,max-div = <2>; | |
1119 | reg = <0x1638>; | |
1120 | }; | |
1121 | ||
1122 | mmc1_fclk_mux: mmc1_fclk_mux { | |
1123 | #clock-cells = <0>; | |
1124 | compatible = "ti,mux-clock"; | |
1125 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
1126 | ti,bit-shift = <24>; | |
1127 | reg = <0x1628>; | |
1128 | }; | |
1129 | ||
1130 | mmc1_fclk: mmc1_fclk { | |
1131 | #clock-cells = <0>; | |
1132 | compatible = "ti,divider-clock"; | |
1133 | clocks = <&mmc1_fclk_mux>; | |
1134 | ti,bit-shift = <25>; | |
1135 | ti,max-div = <2>; | |
1136 | reg = <0x1628>; | |
1137 | }; | |
1138 | ||
1139 | mmc2_fclk_mux: mmc2_fclk_mux { | |
1140 | #clock-cells = <0>; | |
1141 | compatible = "ti,mux-clock"; | |
1142 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
1143 | ti,bit-shift = <24>; | |
1144 | reg = <0x1630>; | |
1145 | }; | |
1146 | ||
1147 | mmc2_fclk: mmc2_fclk { | |
1148 | #clock-cells = <0>; | |
1149 | compatible = "ti,divider-clock"; | |
1150 | clocks = <&mmc2_fclk_mux>; | |
1151 | ti,bit-shift = <25>; | |
1152 | ti,max-div = <2>; | |
1153 | reg = <0x1630>; | |
1154 | }; | |
1155 | ||
1156 | timer10_gfclk_mux: timer10_gfclk_mux { | |
1157 | #clock-cells = <0>; | |
1158 | compatible = "ti,mux-clock"; | |
1159 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1160 | ti,bit-shift = <24>; | |
1161 | reg = <0x1028>; | |
1162 | }; | |
1163 | ||
1164 | timer11_gfclk_mux: timer11_gfclk_mux { | |
1165 | #clock-cells = <0>; | |
1166 | compatible = "ti,mux-clock"; | |
1167 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1168 | ti,bit-shift = <24>; | |
1169 | reg = <0x1030>; | |
1170 | }; | |
1171 | ||
1172 | timer2_gfclk_mux: timer2_gfclk_mux { | |
1173 | #clock-cells = <0>; | |
1174 | compatible = "ti,mux-clock"; | |
1175 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1176 | ti,bit-shift = <24>; | |
1177 | reg = <0x1038>; | |
1178 | }; | |
1179 | ||
1180 | timer3_gfclk_mux: timer3_gfclk_mux { | |
1181 | #clock-cells = <0>; | |
1182 | compatible = "ti,mux-clock"; | |
1183 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1184 | ti,bit-shift = <24>; | |
1185 | reg = <0x1040>; | |
1186 | }; | |
1187 | ||
1188 | timer4_gfclk_mux: timer4_gfclk_mux { | |
1189 | #clock-cells = <0>; | |
1190 | compatible = "ti,mux-clock"; | |
1191 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1192 | ti,bit-shift = <24>; | |
1193 | reg = <0x1048>; | |
1194 | }; | |
1195 | ||
1196 | timer9_gfclk_mux: timer9_gfclk_mux { | |
1197 | #clock-cells = <0>; | |
1198 | compatible = "ti,mux-clock"; | |
1199 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1200 | ti,bit-shift = <24>; | |
1201 | reg = <0x1050>; | |
1202 | }; | |
1203 | }; | |
1204 | ||
1205 | &cm_core_clockdomains { | |
1206 | l3init_clkdm: l3init_clkdm { | |
1207 | compatible = "ti,clockdomain"; | |
1208 | clocks = <&dpll_usb_ck>; | |
1209 | }; | |
1210 | }; | |
1211 | ||
1212 | &scrm_clocks { | |
1213 | auxclk0_src_gate_ck: auxclk0_src_gate_ck { | |
1214 | #clock-cells = <0>; | |
1215 | compatible = "ti,composite-no-wait-gate-clock"; | |
1216 | clocks = <&dpll_core_m3x2_ck>; | |
1217 | ti,bit-shift = <8>; | |
1218 | reg = <0x0310>; | |
1219 | }; | |
1220 | ||
1221 | auxclk0_src_mux_ck: auxclk0_src_mux_ck { | |
1222 | #clock-cells = <0>; | |
1223 | compatible = "ti,composite-mux-clock"; | |
1224 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1225 | ti,bit-shift = <1>; | |
1226 | reg = <0x0310>; | |
1227 | }; | |
1228 | ||
1229 | auxclk0_src_ck: auxclk0_src_ck { | |
1230 | #clock-cells = <0>; | |
1231 | compatible = "ti,composite-clock"; | |
1232 | clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; | |
1233 | }; | |
1234 | ||
1235 | auxclk0_ck: auxclk0_ck { | |
1236 | #clock-cells = <0>; | |
1237 | compatible = "ti,divider-clock"; | |
1238 | clocks = <&auxclk0_src_ck>; | |
1239 | ti,bit-shift = <16>; | |
1240 | ti,max-div = <16>; | |
1241 | reg = <0x0310>; | |
1242 | }; | |
1243 | ||
1244 | auxclk1_src_gate_ck: auxclk1_src_gate_ck { | |
1245 | #clock-cells = <0>; | |
1246 | compatible = "ti,composite-no-wait-gate-clock"; | |
1247 | clocks = <&dpll_core_m3x2_ck>; | |
1248 | ti,bit-shift = <8>; | |
1249 | reg = <0x0314>; | |
1250 | }; | |
1251 | ||
1252 | auxclk1_src_mux_ck: auxclk1_src_mux_ck { | |
1253 | #clock-cells = <0>; | |
1254 | compatible = "ti,composite-mux-clock"; | |
1255 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1256 | ti,bit-shift = <1>; | |
1257 | reg = <0x0314>; | |
1258 | }; | |
1259 | ||
1260 | auxclk1_src_ck: auxclk1_src_ck { | |
1261 | #clock-cells = <0>; | |
1262 | compatible = "ti,composite-clock"; | |
1263 | clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; | |
1264 | }; | |
1265 | ||
1266 | auxclk1_ck: auxclk1_ck { | |
1267 | #clock-cells = <0>; | |
1268 | compatible = "ti,divider-clock"; | |
1269 | clocks = <&auxclk1_src_ck>; | |
1270 | ti,bit-shift = <16>; | |
1271 | ti,max-div = <16>; | |
1272 | reg = <0x0314>; | |
1273 | }; | |
1274 | ||
1275 | auxclk2_src_gate_ck: auxclk2_src_gate_ck { | |
1276 | #clock-cells = <0>; | |
1277 | compatible = "ti,composite-no-wait-gate-clock"; | |
1278 | clocks = <&dpll_core_m3x2_ck>; | |
1279 | ti,bit-shift = <8>; | |
1280 | reg = <0x0318>; | |
1281 | }; | |
1282 | ||
1283 | auxclk2_src_mux_ck: auxclk2_src_mux_ck { | |
1284 | #clock-cells = <0>; | |
1285 | compatible = "ti,composite-mux-clock"; | |
1286 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1287 | ti,bit-shift = <1>; | |
1288 | reg = <0x0318>; | |
1289 | }; | |
1290 | ||
1291 | auxclk2_src_ck: auxclk2_src_ck { | |
1292 | #clock-cells = <0>; | |
1293 | compatible = "ti,composite-clock"; | |
1294 | clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; | |
1295 | }; | |
1296 | ||
1297 | auxclk2_ck: auxclk2_ck { | |
1298 | #clock-cells = <0>; | |
1299 | compatible = "ti,divider-clock"; | |
1300 | clocks = <&auxclk2_src_ck>; | |
1301 | ti,bit-shift = <16>; | |
1302 | ti,max-div = <16>; | |
1303 | reg = <0x0318>; | |
1304 | }; | |
1305 | ||
1306 | auxclk3_src_gate_ck: auxclk3_src_gate_ck { | |
1307 | #clock-cells = <0>; | |
1308 | compatible = "ti,composite-no-wait-gate-clock"; | |
1309 | clocks = <&dpll_core_m3x2_ck>; | |
1310 | ti,bit-shift = <8>; | |
1311 | reg = <0x031c>; | |
1312 | }; | |
1313 | ||
1314 | auxclk3_src_mux_ck: auxclk3_src_mux_ck { | |
1315 | #clock-cells = <0>; | |
1316 | compatible = "ti,composite-mux-clock"; | |
1317 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1318 | ti,bit-shift = <1>; | |
1319 | reg = <0x031c>; | |
1320 | }; | |
1321 | ||
1322 | auxclk3_src_ck: auxclk3_src_ck { | |
1323 | #clock-cells = <0>; | |
1324 | compatible = "ti,composite-clock"; | |
1325 | clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; | |
1326 | }; | |
1327 | ||
1328 | auxclk3_ck: auxclk3_ck { | |
1329 | #clock-cells = <0>; | |
1330 | compatible = "ti,divider-clock"; | |
1331 | clocks = <&auxclk3_src_ck>; | |
1332 | ti,bit-shift = <16>; | |
1333 | ti,max-div = <16>; | |
1334 | reg = <0x031c>; | |
1335 | }; | |
1336 | ||
1337 | auxclk4_src_gate_ck: auxclk4_src_gate_ck { | |
1338 | #clock-cells = <0>; | |
1339 | compatible = "ti,composite-no-wait-gate-clock"; | |
1340 | clocks = <&dpll_core_m3x2_ck>; | |
1341 | ti,bit-shift = <8>; | |
1342 | reg = <0x0320>; | |
1343 | }; | |
1344 | ||
1345 | auxclk4_src_mux_ck: auxclk4_src_mux_ck { | |
1346 | #clock-cells = <0>; | |
1347 | compatible = "ti,composite-mux-clock"; | |
1348 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1349 | ti,bit-shift = <1>; | |
1350 | reg = <0x0320>; | |
1351 | }; | |
1352 | ||
1353 | auxclk4_src_ck: auxclk4_src_ck { | |
1354 | #clock-cells = <0>; | |
1355 | compatible = "ti,composite-clock"; | |
1356 | clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; | |
1357 | }; | |
1358 | ||
1359 | auxclk4_ck: auxclk4_ck { | |
1360 | #clock-cells = <0>; | |
1361 | compatible = "ti,divider-clock"; | |
1362 | clocks = <&auxclk4_src_ck>; | |
1363 | ti,bit-shift = <16>; | |
1364 | ti,max-div = <16>; | |
1365 | reg = <0x0320>; | |
1366 | }; | |
1367 | ||
1368 | auxclkreq0_ck: auxclkreq0_ck { | |
1369 | #clock-cells = <0>; | |
1370 | compatible = "ti,mux-clock"; | |
1371 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1372 | ti,bit-shift = <2>; | |
1373 | reg = <0x0210>; | |
1374 | }; | |
1375 | ||
1376 | auxclkreq1_ck: auxclkreq1_ck { | |
1377 | #clock-cells = <0>; | |
1378 | compatible = "ti,mux-clock"; | |
1379 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1380 | ti,bit-shift = <2>; | |
1381 | reg = <0x0214>; | |
1382 | }; | |
1383 | ||
1384 | auxclkreq2_ck: auxclkreq2_ck { | |
1385 | #clock-cells = <0>; | |
1386 | compatible = "ti,mux-clock"; | |
1387 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1388 | ti,bit-shift = <2>; | |
1389 | reg = <0x0218>; | |
1390 | }; | |
1391 | ||
1392 | auxclkreq3_ck: auxclkreq3_ck { | |
1393 | #clock-cells = <0>; | |
1394 | compatible = "ti,mux-clock"; | |
1395 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1396 | ti,bit-shift = <2>; | |
1397 | reg = <0x021c>; | |
1398 | }; | |
1399 | }; |