projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e04920d9 RS |
1 | /* |
| 2 | * PHYTEC phyCORE-LPC3250 board | |
| 3 | * | |
| 4 | * Copyright 2012 Roland Stigge <stigge@antcom.de> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /dts-v1/; | |
| 1a24edd2 | 15 | #include "lpc32xx.dtsi" |
| e04920d9 RS |
16 | |
| 17 | / { | |
| 18 | model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; | |
| 19 | compatible = "phytec,phy3250", "nxp,lpc3250"; | |
| 20 | #address-cells = <1>; | |
| 21 | #size-cells = <1>; | |
| 22 | ||
| 23 | memory { | |
| 24 | device_type = "memory"; | |
| cae59490 | 25 | reg = <0x80000000 0x4000000>; |
| e04920d9 RS |
26 | }; |
| 27 | ||
| 28 | ahb { | |
| 29 | mac: ethernet@31060000 { | |
| 30 | phy-mode = "rmii"; | |
| 31 | use-iram; | |
| 32 | }; | |
| 33 | ||
| e04920d9 RS |
34 | clcd@31040000 { |
| 35 | status = "okay"; | |
| 36 | }; | |
| 37 | ||
| 38 | /* 64MB Flash via SLC NAND controller */ | |
| 39 | slc: flash@20020000 { | |
| 40 | status = "okay"; | |
| 41 | #address-cells = <1>; | |
| 42 | #size-cells = <1>; | |
| 43 | ||
| 15ab2183 RS |
44 | nxp,wdr-clks = <14>; |
| 45 | nxp,wwidth = <40000000>; | |
| 46 | nxp,whold = <100000000>; | |
| 47 | nxp,wsetup = <100000000>; | |
| 48 | nxp,rdr-clks = <14>; | |
| 49 | nxp,rwidth = <40000000>; | |
| 50 | nxp,rhold = <66666666>; | |
| 51 | nxp,rsetup = <100000000>; | |
| 52 | nand-on-flash-bbt; | |
| 53 | gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ | |
| 54 | ||
| e04920d9 RS |
55 | mtd0@00000000 { |
| 56 | label = "phy3250-boot"; | |
| 57 | reg = <0x00000000 0x00064000>; | |
| 58 | read-only; | |
| 59 | }; | |
| 60 | ||
| 61 | mtd1@00064000 { | |
| 62 | label = "phy3250-uboot"; | |
| 63 | reg = <0x00064000 0x00190000>; | |
| 64 | read-only; | |
| 65 | }; | |
| 66 | ||
| 67 | mtd2@001f4000 { | |
| 68 | label = "phy3250-ubt-prms"; | |
| 69 | reg = <0x001f4000 0x00010000>; | |
| 70 | }; | |
| 71 | ||
| 72 | mtd3@00204000 { | |
| 73 | label = "phy3250-kernel"; | |
| 74 | reg = <0x00204000 0x00400000>; | |
| 75 | }; | |
| 76 | ||
| 77 | mtd4@00604000 { | |
| 78 | label = "phy3250-rootfs"; | |
| 79 | reg = <0x00604000 0x039fc000>; | |
| 80 | }; | |
| 81 | }; | |
| 82 | ||
| 83 | apb { | |
| c70426f1 RS |
84 | uart5: serial@40090000 { |
| 85 | status = "okay"; | |
| 86 | }; | |
| 87 | ||
| 88 | uart3: serial@40080000 { | |
| 89 | status = "okay"; | |
| 90 | }; | |
| 91 | ||
| e04920d9 RS |
92 | i2c1: i2c@400A0000 { |
| 93 | clock-frequency = <100000>; | |
| 94 | ||
| 95 | pcf8563: rtc@51 { | |
| 96 | compatible = "nxp,pcf8563"; | |
| 97 | reg = <0x51>; | |
| 98 | }; | |
| 99 | ||
| 100 | uda1380: uda1380@18 { | |
| 101 | compatible = "nxp,uda1380"; | |
| 102 | reg = <0x18>; | |
| 103 | power-gpio = <&gpio 0x59 0>; | |
| 104 | reset-gpio = <&gpio 0x51 0>; | |
| 105 | dac-clk = "wspll"; | |
| 106 | }; | |
| 107 | }; | |
| 108 | ||
| 109 | i2c2: i2c@400A8000 { | |
| 110 | clock-frequency = <100000>; | |
| 111 | }; | |
| 112 | ||
| e04920d9 | 113 | ssp0: ssp@20084000 { |
| 2e0b5a37 APS |
114 | #address-cells = <1>; |
| 115 | #size-cells = <0>; | |
| 067c182f | 116 | num-cs = <1>; |
| 2e0b5a37 APS |
117 | cs-gpios = <&gpio 3 5 0>; |
| 118 | ||
| e04920d9 | 119 | eeprom: at25@0 { |
| 2e0b5a37 | 120 | pl022,interface = <0>; |
| 2e0b5a37 APS |
121 | pl022,com-mode = <0>; |
| 122 | pl022,rx-level-trig = <1>; | |
| 123 | pl022,tx-level-trig = <1>; | |
| 124 | pl022,ctrl-len = <11>; | |
| 125 | pl022,wait-state = <0>; | |
| 126 | pl022,duplex = <0>; | |
| 127 | ||
| 128 | at25,byte-len = <0x8000>; | |
| 129 | at25,addr-mode = <2>; | |
| 130 | at25,page-size = <64>; | |
| 131 | ||
| e04920d9 | 132 | compatible = "atmel,at25"; |
| 2e0b5a37 APS |
133 | reg = <0>; |
| 134 | spi-max-frequency = <5000000>; | |
| e04920d9 RS |
135 | }; |
| 136 | }; | |
| 2c7fa286 RS |
137 | |
| 138 | sd@20098000 { | |
| 139 | wp-gpios = <&gpio 3 0 0>; | |
| 140 | cd-gpios = <&gpio 3 1 0>; | |
| 141 | cd-inverted; | |
| 142 | bus-width = <4>; | |
| 143 | status = "okay"; | |
| 144 | }; | |
| e04920d9 RS |
145 | }; |
| 146 | ||
| 147 | fab { | |
| ac5ced91 RS |
148 | uart2: serial@40018000 { |
| 149 | status = "okay"; | |
| 150 | }; | |
| 151 | ||
| e04920d9 RS |
152 | tsc@40048000 { |
| 153 | status = "okay"; | |
| 154 | }; | |
| a6d1be0e RS |
155 | |
| 156 | key@40050000 { | |
| 157 | status = "okay"; | |
| 158 | keypad,num-rows = <1>; | |
| 159 | keypad,num-columns = <1>; | |
| 160 | nxp,debounce-delay-ms = <3>; | |
| 161 | nxp,scan-delay-ms = <34>; | |
| 162 | linux,keymap = <0x00000002>; | |
| 163 | }; | |
| e04920d9 RS |
164 | }; |
| 165 | }; | |
| 166 | ||
| 167 | leds { | |
| 168 | compatible = "gpio-leds"; | |
| 169 | ||
| 07c7e12c RS |
170 | led0 { /* red */ |
| 171 | gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ | |
| e04920d9 RS |
172 | default-state = "off"; |
| 173 | }; | |
| 174 | ||
| 07c7e12c RS |
175 | led1 { /* green */ |
| 176 | gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ | |
| 177 | linux,default-trigger = "heartbeat"; | |
| e04920d9 RS |
178 | }; |
| 179 | }; | |
| 180 | }; | |
| aa29efb4 VZ |
181 | |
| 182 | /* Here, choose exactly one from: ohci, usbd */ | |
| 183 | &ohci /* &usbd */ { | |
| 184 | transceiver = <&isp1301>; | |
| 185 | status = "okay"; | |
| 186 | }; | |
| 187 | ||
| 188 | &i2cusb { | |
| 189 | clock-frequency = <100000>; | |
| 190 | ||
| 191 | isp1301: usb-transceiver@2c { | |
| 192 | compatible = "nxp,isp1301"; | |
| 193 | reg = <0x2c>; | |
| 194 | }; | |
| 195 | }; |