[deliverable/linux.git] / arch / arm / boot / dts / picoxcell-pc3x2.dtsi

/*
 *  Copyright (C) 2011 Picochip, Jamie Iles
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
/include/ "skeleton.dtsi"
/ {
	model = "Picochip picoXcell PC3X2";
	compatible = "picochip,pc3x2";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			compatible = "arm,arm1176jz-s";
			device_type = "cpu";
			clock-frequency = <400000000>;
			d-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-line-size = <32>;
			i-cache-size = <32768>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pclk: clock@0 {
			compatible = "fixed-clock";
			clock-outputs = "bus", "pclk";
			clock-frequency = <200000000>;
			ref-clock = <&ref_clk>, "ref";
		};
	};

	paxi {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x80000000 0x400000>;

		emac: gem@30000 {
			compatible = "cadence,gem";
			reg = <0x30000 0x10000>;
			interrupts = <31>;
		};

		dmac1: dmac@40000 {
			compatible = "snps,dw-dmac";
			reg = <0x40000 0x10000>;
			interrupts = <25>;
		};

		dmac2: dmac@50000 {
			compatible = "snps,dw-dmac";
			reg = <0x50000 0x10000>;
			interrupts = <26>;
		};

		vic0: interrupt-controller@60000 {
			compatible = "arm,pl192-vic";
			interrupt-controller;
			reg = <0x60000 0x1000>;
			#interrupt-cells = <1>;
		};

		vic1: interrupt-controller@64000 {
			compatible = "arm,pl192-vic";
			interrupt-controller;
			reg = <0x64000 0x1000>;
			#interrupt-cells = <1>;
		};

		fuse: picoxcell-fuse@80000 {
			compatible = "picoxcell,fuse-pc3x2";
			reg = <0x80000 0x10000>;
		};

		ssi: picoxcell-spi@90000 {
			compatible = "picoxcell,spi";
			reg = <0x90000 0x10000>;
			interrupt-parent = <&vic0>;
			interrupts = <10>;
		};

		ipsec: spacc@100000 {
			compatible = "picochip,spacc-ipsec";
			reg = <0x100000 0x10000>;
			interrupt-parent = <&vic0>;
			interrupts = <24>;
			ref-clock = <&pclk>, "ref";
		};

		srtp: spacc@140000 {
			compatible = "picochip,spacc-srtp";
			reg = <0x140000 0x10000>;
			interrupt-parent = <&vic0>;
			interrupts = <23>;
		};

		l2_engine: spacc@180000 {
			compatible = "picochip,spacc-l2";
			reg = <0x180000 0x10000>;
			interrupt-parent = <&vic0>;
			interrupts = <22>;
			ref-clock = <&pclk>, "ref";
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x200000 0x80000>;

			rtc0: rtc@00000 {
				compatible = "picochip,pc3x2-rtc";
				clock-freq = <200000000>;
				reg = <0x00000 0xf>;
				interrupt-parent = <&vic1>;
				interrupts = <8>;
			};

			timer0: timer@10000 {
				compatible = "picochip,pc3x2-timer";
				interrupt-parent = <&vic0>;
				interrupts = <4>;
				clock-freq = <200000000>;
				reg = <0x10000 0x14>;
			};

			timer1: timer@10014 {
				compatible = "picochip,pc3x2-timer";
				interrupt-parent = <&vic0>;
				interrupts = <5>;
				clock-freq = <200000000>;
				reg = <0x10014 0x14>;
			};

			timer2: timer@10028 {
				compatible = "picochip,pc3x2-timer";
				interrupt-parent = <&vic0>;
				interrupts = <6>;
				clock-freq = <200000000>;
				reg = <0x10028 0x14>;
			};

			timer3: timer@1003c {
				compatible = "picochip,pc3x2-timer";
				interrupt-parent = <&vic0>;
				interrupts = <7>;
				clock-freq = <200000000>;
				reg = <0x1003c 0x14>;
			};

			gpio: gpio@20000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x20000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				reg-io-width = <4>;

				banka: gpio-controller@0 {
					compatible = "snps,dw-apb-gpio-bank";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-generic,nr-gpio = <8>;

					regoffset-dat = <0x50>;
					regoffset-set = <0x00>;
					regoffset-dirout = <0x04>;
				};

				bankb: gpio-controller@1 {
					compatible = "snps,dw-apb-gpio-bank";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-generic,nr-gpio = <8>;

					regoffset-dat = <0x54>;
					regoffset-set = <0x0c>;
					regoffset-dirout = <0x10>;
				};
			};

			uart0: uart@30000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x30000 0x1000>;
				interrupt-parent = <&vic1>;
				interrupts = <10>;
				clock-frequency = <3686400>;
				reg-shift = <2>;
				reg-io-width = <4>;
			};

			uart1: uart@40000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x40000 0x1000>;
				interrupt-parent = <&vic1>;
				interrupts = <9>;
				clock-frequency = <3686400>;
				reg-shift = <2>;
				reg-io-width = <4>;
			};

			wdog: watchdog@50000 {
				compatible = "snps,dw-apb-wdg";
				reg = <0x50000 0x10000>;
				interrupt-parent = <&vic0>;
				interrupts = <11>;
				bus-clock = <&pclk>, "bus";
			};
		};
	};

	rwid-axi {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		ebi@50000000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0 0x40000000 0x08000000
				  1 0 0x48000000 0x08000000
				  2 0 0x50000000 0x08000000
				  3 0 0x58000000 0x08000000>;
		};

		axi2pico@c0000000 {
			compatible = "picochip,axi2pico-pc3x2";
			reg = <0xc0000000 0x10000>;
			interrupts = <13 14 15 16 17 18 19 20 21>;
		};
	};
};
Commit	Line	Data
fee75656 JI	1	/*
	2	* Copyright (C) 2011 Picochip, Jamie Iles
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13	/include/ "skeleton.dtsi"
	14	/ {
	15	model = "Picochip picoXcell PC3X2";
	16	compatible = "picochip,pc3x2";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	cpus {
7021f0b8	21	#address-cells = <0>;
fee75656 JI	22	#size-cells = <0>;
fee75656 JI	23
7021f0b8 LP	24	cpu {
	25	compatible = "arm,arm1176jz-s";
	26	device_type = "cpu";
fee75656	27	clock-frequency = <400000000>;
fee75656 JI	28	d-cache-line-size = <32>;
	29	d-cache-size = <32768>;
	30	i-cache-line-size = <32>;
	31	i-cache-size = <32768>;
	32	};
	33	};
	34
	35	clocks {
	36	#address-cells = <1>;
	37	#size-cells = <1>;
	38	ranges;
	39
	40	pclk: clock@0 {
	41	compatible = "fixed-clock";
	42	clock-outputs = "bus", "pclk";
	43	clock-frequency = <200000000>;
	44	ref-clock = <&ref_clk>, "ref";
	45	};
	46	};
	47
	48	paxi {
	49	compatible = "simple-bus";
	50	#address-cells = <1>;
	51	#size-cells = <1>;
	52	ranges = <0 0x80000000 0x400000>;
	53
	54	emac: gem@30000 {
	55	compatible = "cadence,gem";
	56	reg = <0x30000 0x10000>;
	57	interrupts = <31>;
	58	};
	59
	60	dmac1: dmac@40000 {
	61	compatible = "snps,dw-dmac";
	62	reg = <0x40000 0x10000>;
	63	interrupts = <25>;
	64	};
	65
	66	dmac2: dmac@50000 {
	67	compatible = "snps,dw-dmac";
	68	reg = <0x50000 0x10000>;
	69	interrupts = <26>;
	70	};
	71
	72	vic0: interrupt-controller@60000 {
	73	compatible = "arm,pl192-vic";
	74	interrupt-controller;
	75	reg = <0x60000 0x1000>;
	76	#interrupt-cells = <1>;
	77	};
	78
	79	vic1: interrupt-controller@64000 {
	80	compatible = "arm,pl192-vic";
	81	interrupt-controller;
	82	reg = <0x64000 0x1000>;
	83	#interrupt-cells = <1>;
	84	};
	85
	86	fuse: picoxcell-fuse@80000 {
	87	compatible = "picoxcell,fuse-pc3x2";
	88	reg = <0x80000 0x10000>;
	89	};
	90
	91	ssi: picoxcell-spi@90000 {
92	compatible = "picoxcell,spi";
93	reg = <0x90000 0x10000>;
94	interrupt-parent = <&vic0>;
95	interrupts = <10>;
96	};
97
98	ipsec: spacc@100000 {
99	compatible = "picochip,spacc-ipsec";
100	reg = <0x100000 0x10000>;
101	interrupt-parent = <&vic0>;
102	interrupts = <24>;
103	ref-clock = <&pclk>, "ref";
104	};
105
106	srtp: spacc@140000 {
107	compatible = "picochip,spacc-srtp";
108	reg = <0x140000 0x10000>;
109	interrupt-parent = <&vic0>;
110	interrupts = <23>;
111	};
112
113	l2_engine: spacc@180000 {
114	compatible = "picochip,spacc-l2";
115	reg = <0x180000 0x10000>;
116	interrupt-parent = <&vic0>;
117	interrupts = <22>;
118	ref-clock = <&pclk>, "ref";
119	};
120
121	apb {
122	compatible = "simple-bus";
123	#address-cells = <1>;
124	#size-cells = <1>;
125	ranges = <0 0x200000 0x80000>;
126
127	rtc0: rtc@00000 {
128	compatible = "picochip,pc3x2-rtc";
129	clock-freq = <200000000>;
130	reg = <0x00000 0xf>;
131	interrupt-parent = <&vic1>;
132	interrupts = <8>;
133	};
134
135	timer0: timer@10000 {
136	compatible = "picochip,pc3x2-timer";
137	interrupt-parent = <&vic0>;
138	interrupts = <4>;
139	clock-freq = <200000000>;
140	reg = <0x10000 0x14>;
141	};
142
143	timer1: timer@10014 {
144	compatible = "picochip,pc3x2-timer";
145	interrupt-parent = <&vic0>;
146	interrupts = <5>;
147	clock-freq = <200000000>;
148	reg = <0x10014 0x14>;
149	};
150
151	timer2: timer@10028 {
152	compatible = "picochip,pc3x2-timer";
153	interrupt-parent = <&vic0>;
154	interrupts = <6>;
155	clock-freq = <200000000>;
156	reg = <0x10028 0x14>;
157	};
158
159	timer3: timer@1003c {
160	compatible = "picochip,pc3x2-timer";
161	interrupt-parent = <&vic0>;
162	interrupts = <7>;
163	clock-freq = <200000000>;
164	reg = <0x1003c 0x14>;
165	};
166
167	gpio: gpio@20000 {
168	compatible = "snps,dw-apb-gpio";
169	reg = <0x20000 0x1000>;
170	#address-cells = <1>;
171	#size-cells = <0>;
172	reg-io-width = <4>;
173
174	banka: gpio-controller@0 {
175	compatible = "snps,dw-apb-gpio-bank";
176	gpio-controller;
177	#gpio-cells = <2>;
178	gpio-generic,nr-gpio = <8>;
179
180	regoffset-dat = <0x50>;
181	regoffset-set = <0x00>;
182	regoffset-dirout = <0x04>;
183	};
184
185	bankb: gpio-controller@1 {
186	compatible = "snps,dw-apb-gpio-bank";
187	gpio-controller;
188	#gpio-cells = <2>;
189	gpio-generic,nr-gpio = <8>;
190
191	regoffset-dat = <0x54>;
192	regoffset-set = <0x0c>;
193	regoffset-dirout = <0x10>;
194	};
195	};
196
197	uart0: uart@30000 {
198	compatible = "snps,dw-apb-uart";
199	reg = <0x30000 0x1000>;
200	interrupt-parent = <&vic1>;
201	interrupts = <10>;
202	clock-frequency = <3686400>;
203	reg-shift = <2>;
204	reg-io-width = <4>;
205	};
206
207	uart1: uart@40000 {
208	compatible = "snps,dw-apb-uart";
209	reg = <0x40000 0x1000>;
210	interrupt-parent = <&vic1>;
211	interrupts = <9>;
212	clock-frequency = <3686400>;
213	reg-shift = <2>;
214	reg-io-width = <4>;
215	};
216
217	wdog: watchdog@50000 {
218	compatible = "snps,dw-apb-wdg";
219	reg = <0x50000 0x10000>;
220	interrupt-parent = <&vic0>;
221	interrupts = <11>;
222	bus-clock = <&pclk>, "bus";
223	};
224	};
225	};
226
227	rwid-axi {
228	#address-cells = <1>;
229	#size-cells = <1>;
230	compatible = "simple-bus";
231	ranges;
232
233	ebi@50000000 {
234	compatible = "simple-bus";
235	#address-cells = <2>;
236	#size-cells = <1>;
237	ranges = <0 0 0x40000000 0x08000000
238	1 0 0x48000000 0x08000000
239	2 0 0x50000000 0x08000000
240	3 0 0x58000000 0x08000000>;
241	};
242
243	axi2pico@c0000000 {
244	compatible = "picochip,axi2pico-pc3x2";
245	reg = <0xc0000000 0x10000>;
246	interrupts = <13 14 15 16 17 18 19 20 21>;
247	};
248	};
249	};