Commit | Line | Data |
---|---|---|
434e1c57 BS |
1 | /* |
2 | * DTS file for CSR SiRFprimaII SoC | |
3 | * | |
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
02c981c0 | 10 | / { |
434e1c57 | 11 | compatible = "sirf,prima2"; |
02c981c0 BD |
12 | #address-cells = <1>; |
13 | #size-cells = <1>; | |
14 | interrupt-parent = <&intc>; | |
15 | ||
02c981c0 BD |
16 | cpus { |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
21 | reg = <0x0>; | |
22 | d-cache-line-size = <32>; | |
23 | i-cache-line-size = <32>; | |
24 | d-cache-size = <32768>; | |
25 | i-cache-size = <32768>; | |
26 | /* from bootloader */ | |
27 | timebase-frequency = <0>; | |
28 | bus-frequency = <0>; | |
29 | clock-frequency = <0>; | |
30 | }; | |
31 | }; | |
32 | ||
33 | axi { | |
34 | compatible = "simple-bus"; | |
35 | #address-cells = <1>; | |
36 | #size-cells = <1>; | |
37 | ranges = <0x40000000 0x40000000 0x80000000>; | |
38 | ||
39 | l2-cache-controller@80040000 { | |
917d8535 | 40 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; |
02c981c0 BD |
41 | reg = <0x80040000 0x1000>; |
42 | interrupts = <59>; | |
917d8535 BS |
43 | arm,tag-latency = <1 1 1>; |
44 | arm,data-latency = <1 1 1>; | |
45 | arm,filter-ranges = <0 0x40000000>; | |
02c981c0 BD |
46 | }; |
47 | ||
48 | intc: interrupt-controller@80020000 { | |
49 | #interrupt-cells = <1>; | |
50 | interrupt-controller; | |
51 | compatible = "sirf,prima2-intc"; | |
52 | reg = <0x80020000 0x1000>; | |
53 | }; | |
54 | ||
55 | sys-iobg { | |
56 | compatible = "simple-bus"; | |
57 | #address-cells = <1>; | |
58 | #size-cells = <1>; | |
59 | ranges = <0x88000000 0x88000000 0x40000>; | |
60 | ||
eb8b8f2e | 61 | clks: clock-controller@88000000 { |
02c981c0 BD |
62 | compatible = "sirf,prima2-clkc"; |
63 | reg = <0x88000000 0x1000>; | |
64 | interrupts = <3>; | |
eb8b8f2e | 65 | #clock-cells = <1>; |
02c981c0 BD |
66 | }; |
67 | ||
68 | reset-controller@88010000 { | |
69 | compatible = "sirf,prima2-rstc"; | |
70 | reg = <0x88010000 0x1000>; | |
71 | }; | |
073adf4f BS |
72 | |
73 | rsc-controller@88020000 { | |
74 | compatible = "sirf,prima2-rsc"; | |
75 | reg = <0x88020000 0x1000>; | |
76 | }; | |
02c981c0 BD |
77 | }; |
78 | ||
79 | mem-iobg { | |
80 | compatible = "simple-bus"; | |
81 | #address-cells = <1>; | |
82 | #size-cells = <1>; | |
83 | ranges = <0x90000000 0x90000000 0x10000>; | |
84 | ||
85 | memory-controller@90000000 { | |
86 | compatible = "sirf,prima2-memc"; | |
87 | reg = <0x90000000 0x10000>; | |
88 | interrupts = <27>; | |
eb8b8f2e | 89 | clocks = <&clks 5>; |
02c981c0 BD |
90 | }; |
91 | }; | |
92 | ||
93 | disp-iobg { | |
94 | compatible = "simple-bus"; | |
95 | #address-cells = <1>; | |
96 | #size-cells = <1>; | |
97 | ranges = <0x90010000 0x90010000 0x30000>; | |
98 | ||
99 | display@90010000 { | |
100 | compatible = "sirf,prima2-lcd"; | |
101 | reg = <0x90010000 0x20000>; | |
102 | interrupts = <30>; | |
103 | }; | |
104 | ||
105 | vpp@90020000 { | |
106 | compatible = "sirf,prima2-vpp"; | |
107 | reg = <0x90020000 0x10000>; | |
108 | interrupts = <31>; | |
eb8b8f2e | 109 | clocks = <&clks 35>; |
02c981c0 BD |
110 | }; |
111 | }; | |
112 | ||
113 | graphics-iobg { | |
114 | compatible = "simple-bus"; | |
115 | #address-cells = <1>; | |
116 | #size-cells = <1>; | |
117 | ranges = <0x98000000 0x98000000 0x8000000>; | |
118 | ||
119 | graphics@98000000 { | |
120 | compatible = "powervr,sgx531"; | |
121 | reg = <0x98000000 0x8000000>; | |
122 | interrupts = <6>; | |
eb8b8f2e | 123 | clocks = <&clks 32>; |
02c981c0 BD |
124 | }; |
125 | }; | |
126 | ||
127 | multimedia-iobg { | |
128 | compatible = "simple-bus"; | |
129 | #address-cells = <1>; | |
130 | #size-cells = <1>; | |
131 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
132 | ||
133 | multimedia@a0000000 { | |
134 | compatible = "sirf,prima2-video-codec"; | |
135 | reg = <0xa0000000 0x8000000>; | |
136 | interrupts = <5>; | |
eb8b8f2e | 137 | clocks = <&clks 33>; |
02c981c0 BD |
138 | }; |
139 | }; | |
140 | ||
141 | dsp-iobg { | |
142 | compatible = "simple-bus"; | |
143 | #address-cells = <1>; | |
144 | #size-cells = <1>; | |
145 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
146 | ||
147 | dspif@a8000000 { | |
148 | compatible = "sirf,prima2-dspif"; | |
149 | reg = <0xa8000000 0x10000>; | |
150 | interrupts = <9>; | |
151 | }; | |
152 | ||
153 | gps@a8010000 { | |
154 | compatible = "sirf,prima2-gps"; | |
155 | reg = <0xa8010000 0x10000>; | |
156 | interrupts = <7>; | |
eb8b8f2e | 157 | clocks = <&clks 9>; |
02c981c0 BD |
158 | }; |
159 | ||
160 | dsp@a9000000 { | |
161 | compatible = "sirf,prima2-dsp"; | |
162 | reg = <0xa9000000 0x1000000>; | |
163 | interrupts = <8>; | |
eb8b8f2e | 164 | clocks = <&clks 8>; |
02c981c0 BD |
165 | }; |
166 | }; | |
167 | ||
168 | peri-iobg { | |
169 | compatible = "simple-bus"; | |
170 | #address-cells = <1>; | |
171 | #size-cells = <1>; | |
172 | ranges = <0xb0000000 0xb0000000 0x180000>; | |
173 | ||
174 | timer@b0020000 { | |
175 | compatible = "sirf,prima2-tick"; | |
176 | reg = <0xb0020000 0x1000>; | |
177 | interrupts = <0>; | |
178 | }; | |
179 | ||
180 | nand@b0030000 { | |
181 | compatible = "sirf,prima2-nand"; | |
182 | reg = <0xb0030000 0x10000>; | |
183 | interrupts = <41>; | |
eb8b8f2e | 184 | clocks = <&clks 26>; |
02c981c0 BD |
185 | }; |
186 | ||
187 | audio@b0040000 { | |
188 | compatible = "sirf,prima2-audio"; | |
189 | reg = <0xb0040000 0x10000>; | |
190 | interrupts = <35>; | |
eb8b8f2e | 191 | clocks = <&clks 27>; |
02c981c0 BD |
192 | }; |
193 | ||
194 | uart0: uart@b0050000 { | |
195 | cell-index = <0>; | |
196 | compatible = "sirf,prima2-uart"; | |
197 | reg = <0xb0050000 0x10000>; | |
198 | interrupts = <17>; | |
eb8b8f2e | 199 | clocks = <&clks 13>; |
02c981c0 BD |
200 | }; |
201 | ||
202 | uart1: uart@b0060000 { | |
203 | cell-index = <1>; | |
204 | compatible = "sirf,prima2-uart"; | |
205 | reg = <0xb0060000 0x10000>; | |
206 | interrupts = <18>; | |
eb8b8f2e | 207 | clocks = <&clks 14>; |
02c981c0 BD |
208 | }; |
209 | ||
210 | uart2: uart@b0070000 { | |
211 | cell-index = <2>; | |
212 | compatible = "sirf,prima2-uart"; | |
213 | reg = <0xb0070000 0x10000>; | |
214 | interrupts = <19>; | |
eb8b8f2e | 215 | clocks = <&clks 15>; |
02c981c0 BD |
216 | }; |
217 | ||
218 | usp0: usp@b0080000 { | |
219 | cell-index = <0>; | |
220 | compatible = "sirf,prima2-usp"; | |
221 | reg = <0xb0080000 0x10000>; | |
222 | interrupts = <20>; | |
eb8b8f2e | 223 | clocks = <&clks 28>; |
02c981c0 BD |
224 | }; |
225 | ||
226 | usp1: usp@b0090000 { | |
227 | cell-index = <1>; | |
228 | compatible = "sirf,prima2-usp"; | |
229 | reg = <0xb0090000 0x10000>; | |
230 | interrupts = <21>; | |
eb8b8f2e | 231 | clocks = <&clks 29>; |
02c981c0 BD |
232 | }; |
233 | ||
234 | usp2: usp@b00a0000 { | |
235 | cell-index = <2>; | |
236 | compatible = "sirf,prima2-usp"; | |
237 | reg = <0xb00a0000 0x10000>; | |
238 | interrupts = <22>; | |
eb8b8f2e | 239 | clocks = <&clks 30>; |
02c981c0 BD |
240 | }; |
241 | ||
242 | dmac0: dma-controller@b00b0000 { | |
243 | cell-index = <0>; | |
244 | compatible = "sirf,prima2-dmac"; | |
245 | reg = <0xb00b0000 0x10000>; | |
246 | interrupts = <12>; | |
eb8b8f2e | 247 | clocks = <&clks 24>; |
02c981c0 BD |
248 | }; |
249 | ||
250 | dmac1: dma-controller@b0160000 { | |
251 | cell-index = <1>; | |
252 | compatible = "sirf,prima2-dmac"; | |
253 | reg = <0xb0160000 0x10000>; | |
254 | interrupts = <13>; | |
eb8b8f2e | 255 | clocks = <&clks 25>; |
02c981c0 BD |
256 | }; |
257 | ||
258 | vip@b00C0000 { | |
259 | compatible = "sirf,prima2-vip"; | |
260 | reg = <0xb00C0000 0x10000>; | |
eb8b8f2e | 261 | clocks = <&clks 31>; |
02c981c0 BD |
262 | }; |
263 | ||
264 | spi0: spi@b00d0000 { | |
265 | cell-index = <0>; | |
266 | compatible = "sirf,prima2-spi"; | |
267 | reg = <0xb00d0000 0x10000>; | |
268 | interrupts = <15>; | |
eb8b8f2e | 269 | clocks = <&clks 19>; |
02c981c0 BD |
270 | }; |
271 | ||
272 | spi1: spi@b0170000 { | |
273 | cell-index = <1>; | |
274 | compatible = "sirf,prima2-spi"; | |
275 | reg = <0xb0170000 0x10000>; | |
276 | interrupts = <16>; | |
eb8b8f2e | 277 | clocks = <&clks 20>; |
02c981c0 BD |
278 | }; |
279 | ||
280 | i2c0: i2c@b00e0000 { | |
281 | cell-index = <0>; | |
282 | compatible = "sirf,prima2-i2c"; | |
283 | reg = <0xb00e0000 0x10000>; | |
284 | interrupts = <24>; | |
eb8b8f2e | 285 | clocks = <&clks 17>; |
02c981c0 BD |
286 | }; |
287 | ||
288 | i2c1: i2c@b00f0000 { | |
289 | cell-index = <1>; | |
290 | compatible = "sirf,prima2-i2c"; | |
291 | reg = <0xb00f0000 0x10000>; | |
292 | interrupts = <25>; | |
eb8b8f2e | 293 | clocks = <&clks 18>; |
02c981c0 BD |
294 | }; |
295 | ||
296 | tsc@b0110000 { | |
297 | compatible = "sirf,prima2-tsc"; | |
298 | reg = <0xb0110000 0x10000>; | |
299 | interrupts = <33>; | |
eb8b8f2e | 300 | clocks = <&clks 16>; |
02c981c0 BD |
301 | }; |
302 | ||
056876f6 | 303 | gpio: pinctrl@b0120000 { |
02c981c0 BD |
304 | #gpio-cells = <2>; |
305 | #interrupt-cells = <2>; | |
056876f6 | 306 | compatible = "sirf,prima2-pinctrl"; |
02c981c0 | 307 | reg = <0xb0120000 0x10000>; |
500b6ae3 | 308 | interrupts = <43 44 45 46 47>; |
02c981c0 BD |
309 | gpio-controller; |
310 | interrupt-controller; | |
056876f6 BS |
311 | |
312 | lcd_16pins_a: lcd0@0 { | |
313 | lcd { | |
314 | sirf,pins = "lcd_16bitsgrp"; | |
315 | sirf,function = "lcd_16bits"; | |
316 | }; | |
317 | }; | |
318 | lcd_18pins_a: lcd0@1 { | |
319 | lcd { | |
320 | sirf,pins = "lcd_18bitsgrp"; | |
321 | sirf,function = "lcd_18bits"; | |
322 | }; | |
323 | }; | |
324 | lcd_24pins_a: lcd0@2 { | |
325 | lcd { | |
326 | sirf,pins = "lcd_24bitsgrp"; | |
327 | sirf,function = "lcd_24bits"; | |
328 | }; | |
329 | }; | |
330 | lcdrom_pins_a: lcdrom0@0 { | |
331 | lcd { | |
332 | sirf,pins = "lcdromgrp"; | |
333 | sirf,function = "lcdrom"; | |
334 | }; | |
335 | }; | |
336 | uart0_pins_a: uart0@0 { | |
337 | uart { | |
338 | sirf,pins = "uart0grp"; | |
339 | sirf,function = "uart0"; | |
340 | }; | |
341 | }; | |
342 | uart1_pins_a: uart1@0 { | |
343 | uart { | |
344 | sirf,pins = "uart1grp"; | |
345 | sirf,function = "uart1"; | |
346 | }; | |
347 | }; | |
348 | uart2_pins_a: uart2@0 { | |
349 | uart { | |
350 | sirf,pins = "uart2grp"; | |
351 | sirf,function = "uart2"; | |
352 | }; | |
353 | }; | |
354 | uart2_noflow_pins_a: uart2@1 { | |
355 | uart { | |
356 | sirf,pins = "uart2_nostreamctrlgrp"; | |
357 | sirf,function = "uart2_nostreamctrl"; | |
358 | }; | |
359 | }; | |
360 | spi0_pins_a: spi0@0 { | |
361 | spi { | |
362 | sirf,pins = "spi0grp"; | |
363 | sirf,function = "spi0"; | |
364 | }; | |
365 | }; | |
366 | spi1_pins_a: spi1@0 { | |
367 | spi { | |
368 | sirf,pins = "spi1grp"; | |
369 | sirf,function = "spi1"; | |
370 | }; | |
371 | }; | |
372 | i2c0_pins_a: i2c0@0 { | |
373 | i2c { | |
374 | sirf,pins = "i2c0grp"; | |
375 | sirf,function = "i2c0"; | |
376 | }; | |
377 | }; | |
378 | i2c1_pins_a: i2c1@0 { | |
379 | i2c { | |
380 | sirf,pins = "i2c1grp"; | |
381 | sirf,function = "i2c1"; | |
382 | }; | |
383 | }; | |
384 | pwm0_pins_a: pwm0@0 { | |
385 | pwm { | |
386 | sirf,pins = "pwm0grp"; | |
387 | sirf,function = "pwm0"; | |
388 | }; | |
389 | }; | |
390 | pwm1_pins_a: pwm1@0 { | |
391 | pwm { | |
392 | sirf,pins = "pwm1grp"; | |
393 | sirf,function = "pwm1"; | |
394 | }; | |
395 | }; | |
396 | pwm2_pins_a: pwm2@0 { | |
397 | pwm { | |
398 | sirf,pins = "pwm2grp"; | |
399 | sirf,function = "pwm2"; | |
400 | }; | |
401 | }; | |
402 | pwm3_pins_a: pwm3@0 { | |
403 | pwm { | |
404 | sirf,pins = "pwm3grp"; | |
405 | sirf,function = "pwm3"; | |
406 | }; | |
407 | }; | |
408 | gps_pins_a: gps@0 { | |
409 | gps { | |
410 | sirf,pins = "gpsgrp"; | |
411 | sirf,function = "gps"; | |
412 | }; | |
413 | }; | |
414 | vip_pins_a: vip@0 { | |
415 | vip { | |
416 | sirf,pins = "vipgrp"; | |
417 | sirf,function = "vip"; | |
418 | }; | |
419 | }; | |
420 | sdmmc0_pins_a: sdmmc0@0 { | |
421 | sdmmc0 { | |
422 | sirf,pins = "sdmmc0grp"; | |
423 | sirf,function = "sdmmc0"; | |
424 | }; | |
425 | }; | |
426 | sdmmc1_pins_a: sdmmc1@0 { | |
427 | sdmmc1 { | |
428 | sirf,pins = "sdmmc1grp"; | |
429 | sirf,function = "sdmmc1"; | |
430 | }; | |
431 | }; | |
432 | sdmmc2_pins_a: sdmmc2@0 { | |
433 | sdmmc2 { | |
434 | sirf,pins = "sdmmc2grp"; | |
435 | sirf,function = "sdmmc2"; | |
436 | }; | |
437 | }; | |
438 | sdmmc3_pins_a: sdmmc3@0 { | |
439 | sdmmc3 { | |
440 | sirf,pins = "sdmmc3grp"; | |
441 | sirf,function = "sdmmc3"; | |
442 | }; | |
443 | }; | |
444 | sdmmc4_pins_a: sdmmc4@0 { | |
445 | sdmmc4 { | |
446 | sirf,pins = "sdmmc4grp"; | |
447 | sirf,function = "sdmmc4"; | |
448 | }; | |
449 | }; | |
450 | sdmmc5_pins_a: sdmmc5@0 { | |
451 | sdmmc5 { | |
452 | sirf,pins = "sdmmc5grp"; | |
453 | sirf,function = "sdmmc5"; | |
454 | }; | |
455 | }; | |
456 | i2s_pins_a: i2s@0 { | |
457 | i2s { | |
458 | sirf,pins = "i2sgrp"; | |
459 | sirf,function = "i2s"; | |
460 | }; | |
461 | }; | |
462 | ac97_pins_a: ac97@0 { | |
463 | ac97 { | |
464 | sirf,pins = "ac97grp"; | |
465 | sirf,function = "ac97"; | |
466 | }; | |
467 | }; | |
468 | nand_pins_a: nand@0 { | |
469 | nand { | |
470 | sirf,pins = "nandgrp"; | |
471 | sirf,function = "nand"; | |
472 | }; | |
473 | }; | |
474 | usp0_pins_a: usp0@0 { | |
475 | usp0 { | |
476 | sirf,pins = "usp0grp"; | |
477 | sirf,function = "usp0"; | |
478 | }; | |
479 | }; | |
480 | usp1_pins_a: usp1@0 { | |
481 | usp1 { | |
482 | sirf,pins = "usp1grp"; | |
483 | sirf,function = "usp1"; | |
484 | }; | |
485 | }; | |
486 | usp2_pins_a: usp2@0 { | |
487 | usp2 { | |
488 | sirf,pins = "usp2grp"; | |
489 | sirf,function = "usp2"; | |
490 | }; | |
491 | }; | |
492 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { | |
493 | usb0_utmi_drvbus { | |
494 | sirf,pins = "usb0_utmi_drvbusgrp"; | |
495 | sirf,function = "usb0_utmi_drvbus"; | |
496 | }; | |
497 | }; | |
498 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
499 | usb1_utmi_drvbus { | |
500 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
501 | sirf,function = "usb1_utmi_drvbus"; | |
502 | }; | |
503 | }; | |
504 | warm_rst_pins_a: warm_rst@0 { | |
505 | warm_rst { | |
506 | sirf,pins = "warm_rstgrp"; | |
507 | sirf,function = "warm_rst"; | |
508 | }; | |
509 | }; | |
510 | pulse_count_pins_a: pulse_count@0 { | |
511 | pulse_count { | |
512 | sirf,pins = "pulse_countgrp"; | |
513 | sirf,function = "pulse_count"; | |
514 | }; | |
515 | }; | |
516 | cko0_rst_pins_a: cko0_rst@0 { | |
517 | cko0_rst { | |
518 | sirf,pins = "cko0_rstgrp"; | |
519 | sirf,function = "cko0_rst"; | |
520 | }; | |
521 | }; | |
522 | cko1_rst_pins_a: cko1_rst@0 { | |
523 | cko1_rst { | |
524 | sirf,pins = "cko1_rstgrp"; | |
525 | sirf,function = "cko1_rst"; | |
526 | }; | |
527 | }; | |
02c981c0 BD |
528 | }; |
529 | ||
530 | pwm@b0130000 { | |
531 | compatible = "sirf,prima2-pwm"; | |
532 | reg = <0xb0130000 0x10000>; | |
eb8b8f2e | 533 | clocks = <&clks 21>; |
02c981c0 BD |
534 | }; |
535 | ||
536 | efusesys@b0140000 { | |
537 | compatible = "sirf,prima2-efuse"; | |
538 | reg = <0xb0140000 0x10000>; | |
eb8b8f2e | 539 | clocks = <&clks 22>; |
02c981c0 BD |
540 | }; |
541 | ||
542 | pulsec@b0150000 { | |
543 | compatible = "sirf,prima2-pulsec"; | |
544 | reg = <0xb0150000 0x10000>; | |
545 | interrupts = <48>; | |
eb8b8f2e | 546 | clocks = <&clks 23>; |
02c981c0 BD |
547 | }; |
548 | ||
549 | pci-iobg { | |
550 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
551 | #address-cells = <1>; | |
552 | #size-cells = <1>; | |
553 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
554 | ||
555 | sd0: sdhci@56000000 { | |
556 | cell-index = <0>; | |
557 | compatible = "sirf,prima2-sdhc"; | |
558 | reg = <0x56000000 0x100000>; | |
559 | interrupts = <38>; | |
560 | }; | |
561 | ||
562 | sd1: sdhci@56100000 { | |
563 | cell-index = <1>; | |
564 | compatible = "sirf,prima2-sdhc"; | |
565 | reg = <0x56100000 0x100000>; | |
566 | interrupts = <38>; | |
567 | }; | |
568 | ||
569 | sd2: sdhci@56200000 { | |
570 | cell-index = <2>; | |
571 | compatible = "sirf,prima2-sdhc"; | |
572 | reg = <0x56200000 0x100000>; | |
573 | interrupts = <23>; | |
574 | }; | |
575 | ||
576 | sd3: sdhci@56300000 { | |
577 | cell-index = <3>; | |
578 | compatible = "sirf,prima2-sdhc"; | |
579 | reg = <0x56300000 0x100000>; | |
580 | interrupts = <23>; | |
581 | }; | |
582 | ||
583 | sd4: sdhci@56400000 { | |
584 | cell-index = <4>; | |
585 | compatible = "sirf,prima2-sdhc"; | |
586 | reg = <0x56400000 0x100000>; | |
587 | interrupts = <39>; | |
588 | }; | |
589 | ||
590 | sd5: sdhci@56500000 { | |
591 | cell-index = <5>; | |
592 | compatible = "sirf,prima2-sdhc"; | |
593 | reg = <0x56500000 0x100000>; | |
594 | interrupts = <39>; | |
595 | }; | |
596 | ||
597 | pci-copy@57900000 { | |
598 | compatible = "sirf,prima2-pcicp"; | |
599 | reg = <0x57900000 0x100000>; | |
600 | interrupts = <40>; | |
601 | }; | |
602 | ||
603 | rom-interface@57a00000 { | |
604 | compatible = "sirf,prima2-romif"; | |
605 | reg = <0x57a00000 0x100000>; | |
606 | }; | |
607 | }; | |
608 | }; | |
609 | ||
610 | rtc-iobg { | |
684f7414 | 611 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; |
02c981c0 BD |
612 | #address-cells = <1>; |
613 | #size-cells = <1>; | |
614 | reg = <0x80030000 0x10000>; | |
615 | ||
616 | gpsrtc@1000 { | |
617 | compatible = "sirf,prima2-gpsrtc"; | |
618 | reg = <0x1000 0x1000>; | |
619 | interrupts = <55 56 57>; | |
620 | }; | |
621 | ||
622 | sysrtc@2000 { | |
623 | compatible = "sirf,prima2-sysrtc"; | |
624 | reg = <0x2000 0x1000>; | |
625 | interrupts = <52 53 54>; | |
626 | }; | |
627 | ||
628 | pwrc@3000 { | |
629 | compatible = "sirf,prima2-pwrc"; | |
630 | reg = <0x3000 0x1000>; | |
631 | interrupts = <32>; | |
632 | }; | |
633 | }; | |
634 | ||
635 | uus-iobg { | |
636 | compatible = "simple-bus"; | |
637 | #address-cells = <1>; | |
638 | #size-cells = <1>; | |
639 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
640 | ||
641 | usb0: usb@b00e0000 { | |
642 | compatible = "chipidea,ci13611a-prima2"; | |
643 | reg = <0xb8000000 0x10000>; | |
644 | interrupts = <10>; | |
eb8b8f2e | 645 | clocks = <&clks 40>; |
02c981c0 BD |
646 | }; |
647 | ||
648 | usb1: usb@b00f0000 { | |
649 | compatible = "chipidea,ci13611a-prima2"; | |
650 | reg = <0xb8010000 0x10000>; | |
651 | interrupts = <11>; | |
eb8b8f2e | 652 | clocks = <&clks 41>; |
02c981c0 BD |
653 | }; |
654 | ||
655 | sata@b00f0000 { | |
656 | compatible = "synopsys,dwc-ahsata"; | |
657 | reg = <0xb8020000 0x10000>; | |
658 | interrupts = <37>; | |
659 | }; | |
660 | ||
661 | security@b00f0000 { | |
662 | compatible = "sirf,prima2-security"; | |
663 | reg = <0xb8030000 0x10000>; | |
664 | interrupts = <42>; | |
eb8b8f2e | 665 | clocks = <&clks 7>; |
02c981c0 BD |
666 | }; |
667 | }; | |
668 | }; | |
669 | }; |