Commit | Line | Data |
---|---|---|
f335b8af KG |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
5 | #include <dt-bindings/soc/qcom,gsbi.h> | |
6 | ||
7 | / { | |
8 | model = "Qualcomm APQ8064"; | |
9 | compatible = "qcom,apq8064"; | |
10 | interrupt-parent = <&intc>; | |
11 | ||
12 | cpus { | |
13 | #address-cells = <1>; | |
14 | #size-cells = <0>; | |
15 | ||
16 | cpu@0 { | |
17 | compatible = "qcom,krait"; | |
18 | enable-method = "qcom,kpss-acc-v1"; | |
19 | device_type = "cpu"; | |
20 | reg = <0>; | |
21 | next-level-cache = <&L2>; | |
22 | qcom,acc = <&acc0>; | |
23 | qcom,saw = <&saw0>; | |
24 | }; | |
25 | ||
26 | cpu@1 { | |
27 | compatible = "qcom,krait"; | |
28 | enable-method = "qcom,kpss-acc-v1"; | |
29 | device_type = "cpu"; | |
30 | reg = <1>; | |
31 | next-level-cache = <&L2>; | |
32 | qcom,acc = <&acc1>; | |
33 | qcom,saw = <&saw1>; | |
34 | }; | |
35 | ||
36 | cpu@2 { | |
37 | compatible = "qcom,krait"; | |
38 | enable-method = "qcom,kpss-acc-v1"; | |
39 | device_type = "cpu"; | |
40 | reg = <2>; | |
41 | next-level-cache = <&L2>; | |
42 | qcom,acc = <&acc2>; | |
43 | qcom,saw = <&saw2>; | |
44 | }; | |
45 | ||
46 | cpu@3 { | |
47 | compatible = "qcom,krait"; | |
48 | enable-method = "qcom,kpss-acc-v1"; | |
49 | device_type = "cpu"; | |
50 | reg = <3>; | |
51 | next-level-cache = <&L2>; | |
52 | qcom,acc = <&acc3>; | |
53 | qcom,saw = <&saw3>; | |
54 | }; | |
55 | ||
56 | L2: l2-cache { | |
57 | compatible = "cache"; | |
58 | cache-level = <2>; | |
59 | }; | |
60 | }; | |
61 | ||
62 | cpu-pmu { | |
63 | compatible = "qcom,krait-pmu"; | |
64 | interrupts = <1 10 0x304>; | |
65 | }; | |
66 | ||
67 | soc: soc { | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | ranges; | |
71 | compatible = "simple-bus"; | |
72 | ||
73 | intc: interrupt-controller@2000000 { | |
74 | compatible = "qcom,msm-qgic2"; | |
75 | interrupt-controller; | |
76 | #interrupt-cells = <3>; | |
77 | reg = <0x02000000 0x1000>, | |
78 | <0x02002000 0x1000>; | |
79 | }; | |
80 | ||
81 | timer@200a000 { | |
82 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | |
83 | interrupts = <1 1 0x301>, | |
84 | <1 2 0x301>, | |
85 | <1 3 0x301>; | |
86 | reg = <0x0200a000 0x100>; | |
87 | clock-frequency = <27000000>, | |
88 | <32768>; | |
89 | cpu-offset = <0x80000>; | |
90 | }; | |
91 | ||
92 | acc0: clock-controller@2088000 { | |
93 | compatible = "qcom,kpss-acc-v1"; | |
94 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
95 | }; | |
96 | ||
97 | acc1: clock-controller@2098000 { | |
98 | compatible = "qcom,kpss-acc-v1"; | |
99 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
100 | }; | |
101 | ||
102 | acc2: clock-controller@20a8000 { | |
103 | compatible = "qcom,kpss-acc-v1"; | |
104 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | |
105 | }; | |
106 | ||
107 | acc3: clock-controller@20b8000 { | |
108 | compatible = "qcom,kpss-acc-v1"; | |
109 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | |
110 | }; | |
111 | ||
112 | saw0: regulator@2089000 { | |
113 | compatible = "qcom,saw2"; | |
114 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | |
115 | regulator; | |
116 | }; | |
117 | ||
118 | saw1: regulator@2099000 { | |
119 | compatible = "qcom,saw2"; | |
120 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | |
121 | regulator; | |
122 | }; | |
123 | ||
124 | saw2: regulator@20a9000 { | |
125 | compatible = "qcom,saw2"; | |
126 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; | |
127 | regulator; | |
128 | }; | |
129 | ||
130 | saw3: regulator@20b9000 { | |
131 | compatible = "qcom,saw2"; | |
132 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; | |
133 | regulator; | |
134 | }; | |
135 | ||
136 | gsbi7: gsbi@16600000 { | |
137 | status = "disabled"; | |
138 | compatible = "qcom,gsbi-v1.0.0"; | |
139 | reg = <0x16600000 0x100>; | |
140 | clocks = <&gcc GSBI7_H_CLK>; | |
141 | clock-names = "iface"; | |
142 | #address-cells = <1>; | |
143 | #size-cells = <1>; | |
144 | ranges; | |
145 | ||
146 | serial@16640000 { | |
147 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
148 | reg = <0x16640000 0x1000>, | |
149 | <0x16600000 0x1000>; | |
150 | interrupts = <0 158 0x0>; | |
151 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | |
152 | clock-names = "core", "iface"; | |
153 | status = "disabled"; | |
154 | }; | |
155 | }; | |
156 | ||
157 | qcom,ssbi@500000 { | |
158 | compatible = "qcom,ssbi"; | |
159 | reg = <0x00500000 0x1000>; | |
160 | qcom,controller-type = "pmic-arbiter"; | |
161 | }; | |
162 | ||
163 | gcc: clock-controller@900000 { | |
164 | compatible = "qcom,gcc-apq8064"; | |
165 | reg = <0x00900000 0x4000>; | |
166 | #clock-cells = <1>; | |
167 | #reset-cells = <1>; | |
168 | }; | |
169 | }; | |
170 | }; |