[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;

			sdc4_gpios: sdc4-gpios {
				pios {
					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
					function = "sdc4";
				};
			};

			ps_hold: ps_hold {
				mux {
					pins = "gpio78";
					function = "ps_hold";
				};
			};

			i2c1_pins: i2c1 {
				mux {
					pins = "gpio20", "gpio21";
					function = "gsbi1";
				};
			};

			i2c3_pins: i2c3 {
				mux {
					pins = "gpio8", "gpio9";
					function = "gsbi3";
				};
			};

			gsbi6_uart_2pins: gsbi6_uart_2pins {
				mux {
					pins = "gpio14", "gpio15";
					function = "gsbi6";
				};
			};

			gsbi6_uart_4pins: gsbi6_uart_4pins {
				mux {
					pins = "gpio14", "gpio15", "gpio16", "gpio17";
					function = "gsbi6";
				};
			};

			gsbi7_uart_2pins: gsbi7_uart_2pins {
				mux {
					pins = "gpio82", "gpio83";
					function = "gsbi7";
				};
			};

			gsbi7_uart_4pins: gsbi7_uart_4pins {
				mux {
					pins = "gpio82", "gpio83", "gpio84", "gpio85";
					function = "gsbi7";
				};
			};
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c1: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c1_pins>;
				pinctrl-names = "default";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c2: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi3: gsbi@16200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <3>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			i2c3: i2c@16280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c3_pins>;
				pinctrl-names = "default";
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI3_QUP_CLK>,
					 <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
			};
		};

		gsbi6: gsbi@16500000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <6>;
			reg = <0x16500000 0x03>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi6_serial: serial@16540000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16540000 0x100>,
				      <0x16500000 0x03>;
				interrupts = <0 156 0x0>;
				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 0x0>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic@0 {
				compatible = "qcom,pm8921";
				interrupt-parent = <&tlmm_pinmux>;
				interrupts = <74 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8921_gpio: gpio@150 {

					compatible = "qcom,pm8921-gpio";
					reg = <0x150>;
					interrupts = <192 1>, <193 1>, <194 1>,
						     <195 1>, <196 1>, <197 1>,
						     <198 1>, <199 1>, <200 1>,
						     <201 1>, <202 1>, <203 1>,
						     <204 1>, <205 1>, <206 1>,
						     <207 1>, <208 1>, <209 1>,
						     <210 1>, <211 1>, <212 1>,
						     <213 1>, <214 1>, <215 1>,
						     <216 1>, <217 1>, <218 1>,
						     <219 1>, <220 1>, <221 1>,
						     <222 1>, <223 1>, <224 1>,
						     <225 1>, <226 1>, <227 1>,
						     <228 1>, <229 1>, <230 1>,
						     <231 1>, <232 1>, <233 1>,
						     <234 1>, <235 1>;

					gpio-controller;
					#gpio-cells = <2>;

				};

				pm8921_mpps: mpps@50 {
					compatible = "qcom,pm8921-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupts =
					<128 1>, <129 1>, <130 1>, <131 1>,
					<132 1>, <133 1>, <134 1>, <135 1>,
					<136 1>, <137 1>, <138 1>, <139 1>;
				};

				rtc@11d {
					compatible = "qcom,pm8921-rtc";
					interrupt-parent = <&pmicintc>;
					interrupts = <39 1>;
					reg = <0x11d>;
					allow-set-time;
				};

				pwrkey@1c {
					compatible = "qcom,pm8921-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pmicintc>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};
			};
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-apq8064";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};
			};
		};

		usb1_phy: phy@12500000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS1_XCVR_CLK>,
					  <&gcc USB_HS1_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS1_RESET>;
			reset-names	= "link";
		};

		usb3_phy: phy@12520000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS3_XCVR_CLK>,
					  <&gcc USB_HS3_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS3_RESET>;
			reset-names	= "link";
		};

		usb4_phy: phy@12530000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS4_XCVR_CLK>,
					  <&gcc USB_HS4_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS4_RESET>;
			reset-names	= "link";
		};

		gadget1: gadget@12500000 {
			compatible	= "qcom,ci-hdrc";
			reg		= <0x12500000 0x400>;
			status		= "disabled";
			dr_mode		= "peripheral";
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			usb-phy		= <&usb1_phy>;
		};

		usb1: usb@12500000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb1_phy>;
		};

		usb3: usb@12520000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb3_phy>;
		};

		usb4: usb@12530000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb4_phy>;
		};

		sata_phy0: phy@1b400000 {
			compatible	= "qcom,apq8064-sata-phy";
			status		= "disabled";
			reg		= <0x1b400000 0x200>;
			reg-names	= "phy_mem";
			clocks		= <&gcc SATA_PHY_CFG_CLK>;
			clock-names	= "cfg";
			#phy-cells	= <0>;
		};

		sata0: sata@29000000 {
			compatible		= "generic-ahci";
			status			= "disabled";
			reg			= <0x29000000 0x180>;
			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;

			clocks			= <&gcc SFAB_SATA_S_H_CLK>,
						<&gcc SATA_H_CLK>,
						<&gcc SATA_A_CLK>,
						<&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			clock-names		= "slave_iface",
						"iface",
						"bus",
						"rxoob",
						"core_pmalive";

			assigned-clocks		= <&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates	= <100000000>, <100000000>;

			phys			= <&sata_phy0>;
			phy-names		= "sata-phy";
		};

		/* Temporary fixed regulator */
		sdcc1bam:dma@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 0>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc3bam:dma@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 0>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4bam:dma@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 0>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x2000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x2000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x2000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&sdc4_gpios>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};
};
Commit	Line	Data
f335b8af KG	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
223280b1	5	#include <dt-bindings/reset/qcom,gcc-msm8960.h>
3fe5e3ce	6	#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
f335b8af	7	#include <dt-bindings/soc/qcom,gsbi.h>
8b8936fc	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
f335b8af KG	9	/ {
	10	model = "Qualcomm APQ8064";
	11	compatible = "qcom,apq8064";
	12	interrupt-parent = <&intc>;
	13
	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17
	18	cpu@0 {
	19	compatible = "qcom,krait";
	20	enable-method = "qcom,kpss-acc-v1";
	21	device_type = "cpu";
	22	reg = <0>;
	23	next-level-cache = <&L2>;
	24	qcom,acc = <&acc0>;
	25	qcom,saw = <&saw0>;
06c49f2b	26	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	27	};
	28
	29	cpu@1 {
	30	compatible = "qcom,krait";
	31	enable-method = "qcom,kpss-acc-v1";
	32	device_type = "cpu";
	33	reg = <1>;
	34	next-level-cache = <&L2>;
	35	qcom,acc = <&acc1>;
	36	qcom,saw = <&saw1>;
06c49f2b	37	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	38	};
	39
	40	cpu@2 {
	41	compatible = "qcom,krait";
	42	enable-method = "qcom,kpss-acc-v1";
	43	device_type = "cpu";
	44	reg = <2>;
	45	next-level-cache = <&L2>;
	46	qcom,acc = <&acc2>;
	47	qcom,saw = <&saw2>;
06c49f2b	48	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	49	};
	50
	51	cpu@3 {
	52	compatible = "qcom,krait";
	53	enable-method = "qcom,kpss-acc-v1";
	54	device_type = "cpu";
	55	reg = <3>;
	56	next-level-cache = <&L2>;
	57	qcom,acc = <&acc3>;
	58	qcom,saw = <&saw3>;
06c49f2b	59	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	60	};
	61
	62	L2: l2-cache {
	63	compatible = "cache";
	64	cache-level = <2>;
	65	};
06c49f2b LI	66
	67	idle-states {
	68	CPU_SPC: spc {
	69	compatible = "qcom,idle-state-spc",
	70	"arm,idle-state";
	71	entry-latency-us = <400>;
	72	exit-latency-us = <900>;
	73	min-residency-us = <3000>;
	74	};
	75	};
f335b8af KG	76	};
	77
	78	cpu-pmu {
	79	compatible = "qcom,krait-pmu";
	80	interrupts = <1 10 0x304>;
	81	};
	82
	83	soc: soc {
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges;
	87	compatible = "simple-bus";
	88
8b8936fc PG	89	tlmm_pinmux: pinctrl@800000 {
	90	compatible = "qcom,apq8064-pinctrl";
	91	reg = <0x800000 0x4000>;
	92
	93	gpio-controller;
	94	#gpio-cells = <2>;
	95	interrupt-controller;
	96	#interrupt-cells = <2>;
	97	interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
cd6dd11a PG	98
	99	pinctrl-names = "default";
	100	pinctrl-0 = <&ps_hold>;
	101
0be5fef1 SK	102	sdc4_gpios: sdc4-gpios {
	103	pios {
	104	pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
	105	function = "sdc4";
	106	};
	107	};
	108
cd6dd11a PG	109	ps_hold: ps_hold {
	110	mux {
	111	pins = "gpio78";
	112	function = "ps_hold";
	113	};
	114	};
bc0d3076 SK	115
	116	i2c1_pins: i2c1 {
	117	mux {
	118	pins = "gpio20", "gpio21";
	119	function = "gsbi1";
	120	};
	121	};
3f62b46b SK	122
	123	i2c3_pins: i2c3 {
	124	mux {
	125	pins = "gpio8", "gpio9";
	126	function = "gsbi3";
	127	};
	128	};
86e252a4	129
7648c7bf SK	130	gsbi6_uart_2pins: gsbi6_uart_2pins {
	131	mux {
	132	pins = "gpio14", "gpio15";
	133	function = "gsbi6";
	134	};
	135	};
	136
	137	gsbi6_uart_4pins: gsbi6_uart_4pins {
86e252a4 PG	138	mux {
	139	pins = "gpio14", "gpio15", "gpio16", "gpio17";
	140	function = "gsbi6";
	141	};
	142	};
892d6733 SK	143
	144	gsbi7_uart_2pins: gsbi7_uart_2pins {
	145	mux {
	146	pins = "gpio82", "gpio83";
	147	function = "gsbi7";
	148	};
	149	};
	150
	151	gsbi7_uart_4pins: gsbi7_uart_4pins {
	152	mux {
	153	pins = "gpio82", "gpio83", "gpio84", "gpio85";
	154	function = "gsbi7";
	155	};
	156	};
8b8936fc PG	157	};
8b8936fc PG	158
f335b8af KG	159	intc: interrupt-controller@2000000 {
	160	compatible = "qcom,msm-qgic2";
	161	interrupt-controller;
	162	#interrupt-cells = <3>;
	163	reg = <0x02000000 0x1000>,
	164	<0x02002000 0x1000>;
	165	};
	166
	167	timer@200a000 {
	168	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	169	interrupts = <1 1 0x301>,
	170	<1 2 0x301>,
	171	<1 3 0x301>;
	172	reg = <0x0200a000 0x100>;
	173	clock-frequency = <27000000>,
	174	<32768>;
	175	cpu-offset = <0x80000>;
	176	};
	177
	178	acc0: clock-controller@2088000 {
	179	compatible = "qcom,kpss-acc-v1";
	180	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	181	};
	182
	183	acc1: clock-controller@2098000 {
	184	compatible = "qcom,kpss-acc-v1";
	185	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	186	};
	187
	188	acc2: clock-controller@20a8000 {
	189	compatible = "qcom,kpss-acc-v1";
	190	reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
	191	};
	192
	193	acc3: clock-controller@20b8000 {
	194	compatible = "qcom,kpss-acc-v1";
	195	reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
	196	};
	197
9fc23ce3 LI	198	saw0: power-controller@2089000 {
9fc23ce3 LI	199	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	200	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	201	regulator;
	202	};
	203
9fc23ce3 LI	204	saw1: power-controller@2099000 {
9fc23ce3 LI	205	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	206	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	207	regulator;
	208	};
	209
9fc23ce3 LI	210	saw2: power-controller@20a9000 {
9fc23ce3 LI	211	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	212	reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
	213	regulator;
	214	};
	215
9fc23ce3 LI	216	saw3: power-controller@20b9000 {
9fc23ce3 LI	217	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	218	reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
	219	regulator;
	220	};
	221
8c3166f5	222	gsbi1: gsbi@12440000 {
	223	status = "disabled";
	224	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	225	cell-index = <1>;
8c3166f5	226	reg = <0x12440000 0x100>;
	227	clocks = <&gcc GSBI1_H_CLK>;
	228	clock-names = "iface";
	229	#address-cells = <1>;
	230	#size-cells = <1>;
	231	ranges;
	232
4105d9d6 AG	233	syscon-tcsr = <&tcsr>;
4105d9d6 AG	234
8c3166f5	235	i2c1: i2c@12460000 {
8c3166f5	236	compatible = "qcom,i2c-qup-v1.1.1";
0fbf6104 SK	237	pinctrl-0 = <&i2c1_pins>;
0fbf6104 SK	238	pinctrl-names = "default";
8c3166f5	239	reg = <0x12460000 0x1000>;
	240	interrupts = <0 194 IRQ_TYPE_NONE>;
	241	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	242	clock-names = "core", "iface";
	243	#address-cells = <1>;
	244	#size-cells = <0>;
	245	};
	246	};
	247
	248	gsbi2: gsbi@12480000 {
	249	status = "disabled";
	250	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	251	cell-index = <2>;
8c3166f5	252	reg = <0x12480000 0x100>;
	253	clocks = <&gcc GSBI2_H_CLK>;
	254	clock-names = "iface";
	255	#address-cells = <1>;
	256	#size-cells = <1>;
	257	ranges;
	258
4105d9d6 AG	259	syscon-tcsr = <&tcsr>;
4105d9d6 AG	260
8c3166f5	261	i2c2: i2c@124a0000 {
	262	compatible = "qcom,i2c-qup-v1.1.1";
	263	reg = <0x124a0000 0x1000>;
	264	interrupts = <0 196 IRQ_TYPE_NONE>;
	265	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	266	clock-names = "core", "iface";
	267	#address-cells = <1>;
	268	#size-cells = <0>;
	269	};
	270	};
	271
3f62b46b SK	272	gsbi3: gsbi@16200000 {
	273	status = "disabled";
	274	compatible = "qcom,gsbi-v1.0.0";
504155ca	275	cell-index = <3>;
3f62b46b SK	276	reg = <0x16200000 0x100>;
	277	clocks = <&gcc GSBI3_H_CLK>;
	278	clock-names = "iface";
	279	#address-cells = <1>;
	280	#size-cells = <1>;
	281	ranges;
3f62b46b SK	282	i2c3: i2c@16280000 {
3f62b46b SK	283	compatible = "qcom,i2c-qup-v1.1.1";
0fbf6104 SK	284	pinctrl-0 = <&i2c3_pins>;
0fbf6104 SK	285	pinctrl-names = "default";
3f62b46b SK	286	reg = <0x16280000 0x1000>;
	287	interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
	288	clocks = <&gcc GSBI3_QUP_CLK>,
	289	<&gcc GSBI3_H_CLK>;
	290	clock-names = "core", "iface";
	291	};
	292	};
	293
86e252a4 PG	294	gsbi6: gsbi@16500000 {
	295	status = "disabled";
	296	compatible = "qcom,gsbi-v1.0.0";
	297	cell-index = <6>;
	298	reg = <0x16500000 0x03>;
	299	clocks = <&gcc GSBI6_H_CLK>;
	300	clock-names = "iface";
	301	#address-cells = <1>;
	302	#size-cells = <1>;
	303	ranges;
	304
	305	gsbi6_serial: serial@16540000 {
	306	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	307	reg = <0x16540000 0x100>,
	308	<0x16500000 0x03>;
	309	interrupts = <0 156 0x0>;
	310	clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
	311	clock-names = "core", "iface";
	312	status = "disabled";
	313	};
	314	};
	315
f335b8af KG	316	gsbi7: gsbi@16600000 {
	317	status = "disabled";
	318	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	319	cell-index = <7>;
f335b8af KG	320	reg = <0x16600000 0x100>;
	321	clocks = <&gcc GSBI7_H_CLK>;
	322	clock-names = "iface";
	323	#address-cells = <1>;
	324	#size-cells = <1>;
	325	ranges;
4105d9d6 AG	326	syscon-tcsr = <&tcsr>;
4105d9d6 AG	327
d5d4654e	328	gsbi7_serial: serial@16640000 {
f335b8af KG	329	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	330	reg = <0x16640000 0x1000>,
	331	<0x16600000 0x1000>;
	332	interrupts = <0 158 0x0>;
	333	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	334	clock-names = "core", "iface";
	335	status = "disabled";
	336	};
	337	};
	338
6a607e03 JS	339	rng@1a500000 {
	340	compatible = "qcom,prng";
	341	reg = <0x1a500000 0x200>;
	342	clocks = <&gcc PRNG_CLK>;
	343	clock-names = "core";
	344	};
	345
f335b8af KG	346	qcom,ssbi@500000 {
	347	compatible = "qcom,ssbi";
	348	reg = <0x00500000 0x1000>;
	349	qcom,controller-type = "pmic-arbiter";
874443fe SK	350
	351	pmicintc: pmic@0 {
	352	compatible = "qcom,pm8921";
	353	interrupt-parent = <&tlmm_pinmux>;
	354	interrupts = <74 8>;
	355	#interrupt-cells = <2>;
	356	interrupt-controller;
	357	#address-cells = <1>;
	358	#size-cells = <0>;
	359
	360	pm8921_gpio: gpio@150 {
	361
	362	compatible = "qcom,pm8921-gpio";
	363	reg = <0x150>;
	364	interrupts = <192 1>, <193 1>, <194 1>,
	365	<195 1>, <196 1>, <197 1>,
	366	<198 1>, <199 1>, <200 1>,
	367	<201 1>, <202 1>, <203 1>,
	368	<204 1>, <205 1>, <206 1>,
	369	<207 1>, <208 1>, <209 1>,
	370	<210 1>, <211 1>, <212 1>,
	371	<213 1>, <214 1>, <215 1>,
	372	<216 1>, <217 1>, <218 1>,
	373	<219 1>, <220 1>, <221 1>,
	374	<222 1>, <223 1>, <224 1>,
	375	<225 1>, <226 1>, <227 1>,
	376	<228 1>, <229 1>, <230 1>,
	377	<231 1>, <232 1>, <233 1>,
	378	<234 1>, <235 1>;
	379
	380	gpio-controller;
	381	#gpio-cells = <2>;
	382
	383	};
bce36046 SK	384
	385	pm8921_mpps: mpps@50 {
	386	compatible = "qcom,pm8921-mpp";
	387	reg = <0x50>;
	388	gpio-controller;
	389	#gpio-cells = <2>;
	390	interrupts =
	391	<128 1>, <129 1>, <130 1>, <131 1>,
	392	<132 1>, <133 1>, <134 1>, <135 1>,
	393	<136 1>, <137 1>, <138 1>, <139 1>;
	394	};
	395
bbf89b96 SK	396	rtc@11d {
	397	compatible = "qcom,pm8921-rtc";
	398	interrupt-parent = <&pmicintc>;
	399	interrupts = <39 1>;
	400	reg = <0x11d>;
	401	allow-set-time;
	402	};
	403
3050c5f5 SK	404	pwrkey@1c {
	405	compatible = "qcom,pm8921-pwrkey";
	406	reg = <0x1c>;
	407	interrupt-parent = <&pmicintc>;
	408	interrupts = <50 1>, <51 1>;
	409	debounce = <15625>;
	410	pull-up;
	411	};
874443fe	412	};
f335b8af KG	413	};
	414
	415	gcc: clock-controller@900000 {
	416	compatible = "qcom,gcc-apq8064";
	417	reg = <0x00900000 0x4000>;
	418	#clock-cells = <1>;
	419	#reset-cells = <1>;
	420	};
3fe5e3ce	421
1e1177bf KG	422	lcc: clock-controller@28000000 {
	423	compatible = "qcom,lcc-apq8064";
	424	reg = <0x28000000 0x1000>;
	425	#clock-cells = <1>;
	426	#reset-cells = <1>;
	427	};
	428
3fe5e3ce SB	429	mmcc: clock-controller@4000000 {
	430	compatible = "qcom,mmcc-apq8064";
	431	reg = <0x4000000 0x1000>;
	432	#clock-cells = <1>;
	433	#reset-cells = <1>;
	434	};
045644ff	435
dc2f8152 SK	436	l2cc: clock-controller@2011000 {
	437	compatible = "syscon";
	438	reg = <0x2011000 0x1000>;
	439	};
	440
	441	rpm@108000 {
	442	compatible = "qcom,rpm-apq8064";
	443	reg = <0x108000 0x1000>;
	444	qcom,ipc = <&l2cc 0x8 2>;
	445
	446	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	447	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	448	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	449	interrupt-names = "ack", "err", "wakeup";
	450
	451	regulators {
	452	compatible = "qcom,rpm-pm8921-regulators";
	453
	454	pm8921_hdmi_switch: hdmi-switch {
	455	bias-pull-down;
	456	};
	457	};
	458	};
	459
ea986611 SK	460	usb1_phy: phy@12500000 {
	461	compatible = "qcom,usb-otg-ci";
	462	reg = <0x12500000 0x400>;
	463	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	464	status = "disabled";
	465	dr_mode = "host";
	466
	467	clocks = <&gcc USB_HS1_XCVR_CLK>,
	468	<&gcc USB_HS1_H_CLK>;
	469	clock-names = "core", "iface";
	470
	471	resets = <&gcc USB_HS1_RESET>;
	472	reset-names = "link";
	473	};
	474
223280b1 SK	475	usb3_phy: phy@12520000 {
	476	compatible = "qcom,usb-otg-ci";
	477	reg = <0x12520000 0x400>;
	478	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	479	status = "disabled";
	480	dr_mode = "host";
	481
	482	clocks = <&gcc USB_HS3_XCVR_CLK>,
	483	<&gcc USB_HS3_H_CLK>;
	484	clock-names = "core", "iface";
	485
	486	resets = <&gcc USB_HS3_RESET>;
	487	reset-names = "link";
	488	};
	489
	490	usb4_phy: phy@12530000 {
	491	compatible = "qcom,usb-otg-ci";
	492	reg = <0x12530000 0x400>;
	493	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	494	status = "disabled";
	495	dr_mode = "host";
	496
	497	clocks = <&gcc USB_HS4_XCVR_CLK>,
	498	<&gcc USB_HS4_H_CLK>;
	499	clock-names = "core", "iface";
	500
	501	resets = <&gcc USB_HS4_RESET>;
	502	reset-names = "link";
	503	};
	504
ea986611 SK	505	gadget1: gadget@12500000 {
	506	compatible = "qcom,ci-hdrc";
	507	reg = <0x12500000 0x400>;
	508	status = "disabled";
	509	dr_mode = "peripheral";
	510	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	511	usb-phy = <&usb1_phy>;
	512	};
	513
	514	usb1: usb@12500000 {
	515	compatible = "qcom,ehci-host";
	516	reg = <0x12500000 0x400>;
	517	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	518	status = "disabled";
	519	usb-phy = <&usb1_phy>;
	520	};
	521
223280b1 SK	522	usb3: usb@12520000 {
	523	compatible = "qcom,ehci-host";
	524	reg = <0x12520000 0x400>;
	525	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	526	status = "disabled";
	527	usb-phy = <&usb3_phy>;
	528	};
	529
	530	usb4: usb@12530000 {
	531	compatible = "qcom,ehci-host";
	532	reg = <0x12530000 0x400>;
	533	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	534	status = "disabled";
	535	usb-phy = <&usb4_phy>;
	536	};
	537
e629335f SK	538	sata_phy0: phy@1b400000 {
	539	compatible = "qcom,apq8064-sata-phy";
	540	status = "disabled";
	541	reg = <0x1b400000 0x200>;
	542	reg-names = "phy_mem";
	543	clocks = <&gcc SATA_PHY_CFG_CLK>;
	544	clock-names = "cfg";
	545	#phy-cells = <0>;
	546	};
	547
	548	sata0: sata@29000000 {
	549	compatible = "generic-ahci";
	550	status = "disabled";
	551	reg = <0x29000000 0x180>;
	552	interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
	553
	554	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	555	<&gcc SATA_H_CLK>,
	556	<&gcc SATA_A_CLK>,
	557	<&gcc SATA_RXOOB_CLK>,
	558	<&gcc SATA_PMALIVE_CLK>;
	559	clock-names = "slave_iface",
	560	"iface",
	561	"bus",
	562	"rxoob",
	563	"core_pmalive";
	564
	565	assigned-clocks = <&gcc SATA_RXOOB_CLK>,
	566	<&gcc SATA_PMALIVE_CLK>;
	567	assigned-clock-rates = <100000000>, <100000000>;
	568
	569	phys = <&sata_phy0>;
	570	phy-names = "sata-phy";
	571	};
	572
045644ff	573	/* Temporary fixed regulator */
edb81ca3 SK	574	sdcc1bam:dma@12402000{
	575	compatible = "qcom,bam-v1.3.0";
	576	reg = <0x12402000 0x8000>;
	577	interrupts = <0 98 0>;
	578	clocks = <&gcc SDC1_H_CLK>;
	579	clock-names = "bam_clk";
	580	#dma-cells = <1>;
	581	qcom,ee = <0>;
	582	};
	583
	584	sdcc3bam:dma@12182000{
	585	compatible = "qcom,bam-v1.3.0";
	586	reg = <0x12182000 0x8000>;
	587	interrupts = <0 96 0>;
	588	clocks = <&gcc SDC3_H_CLK>;
	589	clock-names = "bam_clk";
	590	#dma-cells = <1>;
	591	qcom,ee = <0>;
	592	};
	593
0be5fef1 SK	594	sdcc4bam:dma@121c2000{
	595	compatible = "qcom,bam-v1.3.0";
	596	reg = <0x121c2000 0x8000>;
	597	interrupts = <0 95 0>;
	598	clocks = <&gcc SDC4_H_CLK>;
	599	clock-names = "bam_clk";
	600	#dma-cells = <1>;
	601	qcom,ee = <0>;
	602	};
	603
045644ff SK	604	amba {
	605	compatible = "arm,amba-bus";
	606	#address-cells = <1>;
	607	#size-cells = <1>;
	608	ranges;
	609	sdcc1: sdcc@12400000 {
	610	status = "disabled";
	611	compatible = "arm,pl18x", "arm,primecell";
	612	arm,primecell-periphid = <0x00051180>;
	613	reg = <0x12400000 0x2000>;
	614	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	615	interrupt-names = "cmd_irq";
	616	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	617	clock-names = "mclk", "apb_pclk";
	618	bus-width = <8>;
	619	max-frequency = <96000000>;
	620	non-removable;
	621	cap-sd-highspeed;
	622	cap-mmc-highspeed;
edb81ca3 SK	623	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
edb81ca3 SK	624	dma-names = "tx", "rx";
045644ff SK	625	};
	626
	627	sdcc3: sdcc@12180000 {
	628	compatible = "arm,pl18x", "arm,primecell";
	629	arm,primecell-periphid = <0x00051180>;
	630	status = "disabled";
	631	reg = <0x12180000 0x2000>;
	632	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	633	interrupt-names = "cmd_irq";
	634	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	635	clock-names = "mclk", "apb_pclk";
	636	bus-width = <4>;
	637	cap-sd-highspeed;
	638	cap-mmc-highspeed;
	639	max-frequency = <192000000>;
	640	no-1-8-v;
edb81ca3 SK	641	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
edb81ca3 SK	642	dma-names = "tx", "rx";
045644ff	643	};
0be5fef1 SK	644
	645	sdcc4: sdcc@121c0000 {
	646	compatible = "arm,pl18x", "arm,primecell";
	647	arm,primecell-periphid = <0x00051180>;
	648	status = "disabled";
	649	reg = <0x121c0000 0x2000>;
	650	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	651	interrupt-names = "cmd_irq";
	652	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	653	clock-names = "mclk", "apb_pclk";
	654	bus-width = <4>;
	655	cap-sd-highspeed;
	656	cap-mmc-highspeed;
	657	max-frequency = <48000000>;
0be5fef1 SK	658	dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
	659	dma-names = "tx", "rx";
	660	pinctrl-names = "default";
	661	pinctrl-0 = <&sdc4_gpios>;
	662	};
045644ff	663	};
4105d9d6 AG	664
	665	tcsr: syscon@1a400000 {
	666	compatible = "qcom,tcsr-apq8064", "syscon";
	667	reg = <0x1a400000 0x100>;
	668	};
f335b8af KG	669	};
f335b8af KG	670	};