[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;

			sdc4_gpios: sdc4-gpios {
				pios {
					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
					function = "sdc4";
				};
			};

			ps_hold: ps_hold {
				mux {
					pins = "gpio78";
					function = "ps_hold";
				};
			};
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c1: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c2: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 0x0>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-apq8064";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};
			};
		};

		/* Temporary fixed regulator */
		vsdcc_fixed: vsdcc-regulator {
			compatible = "regulator-fixed";
			regulator-name = "SDCC Power";
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
			regulator-always-on;
		};

		sdcc1bam:dma@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 0>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc3bam:dma@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 0>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4bam:dma@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 0>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x2000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				vmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x2000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				vmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x2000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				vmmc-supply = <&vsdcc_fixed>;
				vqmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&sdc4_gpios>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};
};
Commit	Line	Data
f335b8af KG	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
3fe5e3ce	5	#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
f335b8af	6	#include <dt-bindings/soc/qcom,gsbi.h>
8b8936fc	7	#include <dt-bindings/interrupt-controller/arm-gic.h>
f335b8af KG	8
	9	/ {
	10	model = "Qualcomm APQ8064";
	11	compatible = "qcom,apq8064";
	12	interrupt-parent = <&intc>;
	13
	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17
	18	cpu@0 {
	19	compatible = "qcom,krait";
	20	enable-method = "qcom,kpss-acc-v1";
	21	device_type = "cpu";
	22	reg = <0>;
	23	next-level-cache = <&L2>;
	24	qcom,acc = <&acc0>;
	25	qcom,saw = <&saw0>;
06c49f2b	26	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	27	};
	28
	29	cpu@1 {
	30	compatible = "qcom,krait";
	31	enable-method = "qcom,kpss-acc-v1";
	32	device_type = "cpu";
	33	reg = <1>;
	34	next-level-cache = <&L2>;
	35	qcom,acc = <&acc1>;
	36	qcom,saw = <&saw1>;
06c49f2b	37	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	38	};
	39
	40	cpu@2 {
	41	compatible = "qcom,krait";
	42	enable-method = "qcom,kpss-acc-v1";
	43	device_type = "cpu";
	44	reg = <2>;
	45	next-level-cache = <&L2>;
	46	qcom,acc = <&acc2>;
	47	qcom,saw = <&saw2>;
06c49f2b	48	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	49	};
	50
	51	cpu@3 {
	52	compatible = "qcom,krait";
	53	enable-method = "qcom,kpss-acc-v1";
	54	device_type = "cpu";
	55	reg = <3>;
	56	next-level-cache = <&L2>;
	57	qcom,acc = <&acc3>;
	58	qcom,saw = <&saw3>;
06c49f2b	59	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	60	};
	61
	62	L2: l2-cache {
	63	compatible = "cache";
	64	cache-level = <2>;
	65	};
06c49f2b LI	66
	67	idle-states {
	68	CPU_SPC: spc {
	69	compatible = "qcom,idle-state-spc",
	70	"arm,idle-state";
	71	entry-latency-us = <400>;
	72	exit-latency-us = <900>;
	73	min-residency-us = <3000>;
	74	};
	75	};
f335b8af KG	76	};
	77
	78	cpu-pmu {
	79	compatible = "qcom,krait-pmu";
	80	interrupts = <1 10 0x304>;
	81	};
	82
	83	soc: soc {
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges;
	87	compatible = "simple-bus";
	88
8b8936fc PG	89	tlmm_pinmux: pinctrl@800000 {
	90	compatible = "qcom,apq8064-pinctrl";
	91	reg = <0x800000 0x4000>;
	92
	93	gpio-controller;
	94	#gpio-cells = <2>;
	95	interrupt-controller;
	96	#interrupt-cells = <2>;
	97	interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
cd6dd11a PG	98
	99	pinctrl-names = "default";
	100	pinctrl-0 = <&ps_hold>;
	101
0be5fef1 SK	102	sdc4_gpios: sdc4-gpios {
	103	pios {
	104	pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
	105	function = "sdc4";
	106	};
	107	};
	108
cd6dd11a PG	109	ps_hold: ps_hold {
	110	mux {
	111	pins = "gpio78";
	112	function = "ps_hold";
	113	};
	114	};
8b8936fc PG	115	};
8b8936fc PG	116
f335b8af KG	117	intc: interrupt-controller@2000000 {
	118	compatible = "qcom,msm-qgic2";
	119	interrupt-controller;
	120	#interrupt-cells = <3>;
	121	reg = <0x02000000 0x1000>,
	122	<0x02002000 0x1000>;
	123	};
	124
	125	timer@200a000 {
	126	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	127	interrupts = <1 1 0x301>,
	128	<1 2 0x301>,
	129	<1 3 0x301>;
	130	reg = <0x0200a000 0x100>;
	131	clock-frequency = <27000000>,
	132	<32768>;
	133	cpu-offset = <0x80000>;
	134	};
	135
	136	acc0: clock-controller@2088000 {
	137	compatible = "qcom,kpss-acc-v1";
	138	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	139	};
	140
	141	acc1: clock-controller@2098000 {
	142	compatible = "qcom,kpss-acc-v1";
	143	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	144	};
	145
	146	acc2: clock-controller@20a8000 {
	147	compatible = "qcom,kpss-acc-v1";
	148	reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
	149	};
	150
	151	acc3: clock-controller@20b8000 {
	152	compatible = "qcom,kpss-acc-v1";
	153	reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
	154	};
	155
9fc23ce3 LI	156	saw0: power-controller@2089000 {
9fc23ce3 LI	157	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	158	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	159	regulator;
	160	};
	161
9fc23ce3 LI	162	saw1: power-controller@2099000 {
9fc23ce3 LI	163	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	164	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	165	regulator;
	166	};
	167
9fc23ce3 LI	168	saw2: power-controller@20a9000 {
9fc23ce3 LI	169	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	170	reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
	171	regulator;
	172	};
	173
9fc23ce3 LI	174	saw3: power-controller@20b9000 {
9fc23ce3 LI	175	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	176	reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
	177	regulator;
	178	};
	179
8c3166f5	180	gsbi1: gsbi@12440000 {
	181	status = "disabled";
	182	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	183	cell-index = <1>;
8c3166f5	184	reg = <0x12440000 0x100>;
	185	clocks = <&gcc GSBI1_H_CLK>;
	186	clock-names = "iface";
	187	#address-cells = <1>;
	188	#size-cells = <1>;
	189	ranges;
	190
4105d9d6 AG	191	syscon-tcsr = <&tcsr>;
4105d9d6 AG	192
8c3166f5	193	i2c1: i2c@12460000 {
	194	compatible = "qcom,i2c-qup-v1.1.1";
	195	reg = <0x12460000 0x1000>;
	196	interrupts = <0 194 IRQ_TYPE_NONE>;
	197	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	198	clock-names = "core", "iface";
	199	#address-cells = <1>;
	200	#size-cells = <0>;
	201	};
	202	};
	203
	204	gsbi2: gsbi@12480000 {
	205	status = "disabled";
	206	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	207	cell-index = <2>;
8c3166f5	208	reg = <0x12480000 0x100>;
	209	clocks = <&gcc GSBI2_H_CLK>;
	210	clock-names = "iface";
	211	#address-cells = <1>;
	212	#size-cells = <1>;
	213	ranges;
	214
4105d9d6 AG	215	syscon-tcsr = <&tcsr>;
4105d9d6 AG	216
8c3166f5	217	i2c2: i2c@124a0000 {
	218	compatible = "qcom,i2c-qup-v1.1.1";
	219	reg = <0x124a0000 0x1000>;
	220	interrupts = <0 196 IRQ_TYPE_NONE>;
	221	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	222	clock-names = "core", "iface";
	223	#address-cells = <1>;
	224	#size-cells = <0>;
	225	};
	226	};
	227
f335b8af KG	228	gsbi7: gsbi@16600000 {
	229	status = "disabled";
	230	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	231	cell-index = <7>;
f335b8af KG	232	reg = <0x16600000 0x100>;
	233	clocks = <&gcc GSBI7_H_CLK>;
	234	clock-names = "iface";
	235	#address-cells = <1>;
	236	#size-cells = <1>;
	237	ranges;
	238
4105d9d6 AG	239	syscon-tcsr = <&tcsr>;
4105d9d6 AG	240
f335b8af KG	241	serial@16640000 {
	242	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	243	reg = <0x16640000 0x1000>,
	244	<0x16600000 0x1000>;
	245	interrupts = <0 158 0x0>;
	246	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	247	clock-names = "core", "iface";
	248	status = "disabled";
	249	};
	250	};
	251
	252	qcom,ssbi@500000 {
	253	compatible = "qcom,ssbi";
	254	reg = <0x00500000 0x1000>;
	255	qcom,controller-type = "pmic-arbiter";
	256	};
	257
	258	gcc: clock-controller@900000 {
	259	compatible = "qcom,gcc-apq8064";
	260	reg = <0x00900000 0x4000>;
	261	#clock-cells = <1>;
	262	#reset-cells = <1>;
	263	};
3fe5e3ce	264
1e1177bf KG	265	lcc: clock-controller@28000000 {
	266	compatible = "qcom,lcc-apq8064";
	267	reg = <0x28000000 0x1000>;
	268	#clock-cells = <1>;
	269	#reset-cells = <1>;
	270	};
	271
3fe5e3ce SB	272	mmcc: clock-controller@4000000 {
	273	compatible = "qcom,mmcc-apq8064";
	274	reg = <0x4000000 0x1000>;
	275	#clock-cells = <1>;
	276	#reset-cells = <1>;
	277	};
045644ff	278
dc2f8152 SK	279	l2cc: clock-controller@2011000 {
	280	compatible = "syscon";
	281	reg = <0x2011000 0x1000>;
	282	};
	283
	284	rpm@108000 {
	285	compatible = "qcom,rpm-apq8064";
	286	reg = <0x108000 0x1000>;
	287	qcom,ipc = <&l2cc 0x8 2>;
	288
	289	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	290	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	291	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	292	interrupt-names = "ack", "err", "wakeup";
	293
	294	regulators {
	295	compatible = "qcom,rpm-pm8921-regulators";
	296
	297	pm8921_hdmi_switch: hdmi-switch {
	298	bias-pull-down;
	299	};
	300	};
	301	};
	302
045644ff SK	303	/* Temporary fixed regulator */
	304	vsdcc_fixed: vsdcc-regulator {
	305	compatible = "regulator-fixed";
	306	regulator-name = "SDCC Power";
	307	regulator-min-microvolt = <2700000>;
	308	regulator-max-microvolt = <2700000>;
	309	regulator-always-on;
	310	};
	311
edb81ca3 SK	312	sdcc1bam:dma@12402000{
	313	compatible = "qcom,bam-v1.3.0";
	314	reg = <0x12402000 0x8000>;
	315	interrupts = <0 98 0>;
	316	clocks = <&gcc SDC1_H_CLK>;
	317	clock-names = "bam_clk";
	318	#dma-cells = <1>;
	319	qcom,ee = <0>;
	320	};
	321
	322	sdcc3bam:dma@12182000{
	323	compatible = "qcom,bam-v1.3.0";
	324	reg = <0x12182000 0x8000>;
	325	interrupts = <0 96 0>;
	326	clocks = <&gcc SDC3_H_CLK>;
	327	clock-names = "bam_clk";
	328	#dma-cells = <1>;
	329	qcom,ee = <0>;
	330	};
	331
0be5fef1 SK	332	sdcc4bam:dma@121c2000{
	333	compatible = "qcom,bam-v1.3.0";
	334	reg = <0x121c2000 0x8000>;
	335	interrupts = <0 95 0>;
	336	clocks = <&gcc SDC4_H_CLK>;
	337	clock-names = "bam_clk";
	338	#dma-cells = <1>;
	339	qcom,ee = <0>;
	340	};
	341
045644ff SK	342	amba {
	343	compatible = "arm,amba-bus";
	344	#address-cells = <1>;
	345	#size-cells = <1>;
	346	ranges;
	347	sdcc1: sdcc@12400000 {
	348	status = "disabled";
	349	compatible = "arm,pl18x", "arm,primecell";
	350	arm,primecell-periphid = <0x00051180>;
	351	reg = <0x12400000 0x2000>;
	352	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	353	interrupt-names = "cmd_irq";
	354	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	355	clock-names = "mclk", "apb_pclk";
	356	bus-width = <8>;
	357	max-frequency = <96000000>;
	358	non-removable;
	359	cap-sd-highspeed;
	360	cap-mmc-highspeed;
	361	vmmc-supply = <&vsdcc_fixed>;
edb81ca3 SK	362	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
edb81ca3 SK	363	dma-names = "tx", "rx";
045644ff SK	364	};
	365
	366	sdcc3: sdcc@12180000 {
	367	compatible = "arm,pl18x", "arm,primecell";
	368	arm,primecell-periphid = <0x00051180>;
	369	status = "disabled";
	370	reg = <0x12180000 0x2000>;
	371	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	372	interrupt-names = "cmd_irq";
	373	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	374	clock-names = "mclk", "apb_pclk";
	375	bus-width = <4>;
	376	cap-sd-highspeed;
	377	cap-mmc-highspeed;
	378	max-frequency = <192000000>;
	379	no-1-8-v;
	380	vmmc-supply = <&vsdcc_fixed>;
edb81ca3 SK	381	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
edb81ca3 SK	382	dma-names = "tx", "rx";
045644ff	383	};
0be5fef1 SK	384
	385	sdcc4: sdcc@121c0000 {
	386	compatible = "arm,pl18x", "arm,primecell";
	387	arm,primecell-periphid = <0x00051180>;
	388	status = "disabled";
	389	reg = <0x121c0000 0x2000>;
	390	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	391	interrupt-names = "cmd_irq";
	392	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	393	clock-names = "mclk", "apb_pclk";
	394	bus-width = <4>;
	395	cap-sd-highspeed;
	396	cap-mmc-highspeed;
	397	max-frequency = <48000000>;
	398	vmmc-supply = <&vsdcc_fixed>;
	399	vqmmc-supply = <&vsdcc_fixed>;
	400	dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
	401	dma-names = "tx", "rx";
	402	pinctrl-names = "default";
	403	pinctrl-0 = <&sdc4_gpios>;
	404	};
045644ff	405	};
4105d9d6 AG	406
	407	tcsr: syscon@1a400000 {
	408	compatible = "qcom,tcsr-apq8064", "syscon";
	409	reg = <0x1a400000 0x100>;
	410	};
f335b8af KG	411	};
f335b8af KG	412	};